Attorney Docket Number: 20223727 / 24061.4732US01
Filing Date: 6/15/2023
Inventors: Chou et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendments filed 12/29/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as
subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing
from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art
relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Interpretation
Claim 1 contains a line reciting “…wherein the first, second, and third insulator layers include a metal oxide sandwich structure”, which will be interpreted as “…wherein the combination of the first, second, and third insulator layers include a metal oxide sandwich structure”.
Acknowledgement
The Amendments filed on 12/29/2025, responding to the Office action mailed 9/29/2025,
has been entered. Applicant amended claims 1, 13, 15, 18, and 20. Applicant cancelled claim 19 and added claim 21. The present Office action is made with all the suggested amendments being fully
considered.
Response to Arguments/Amendments
Applicant’s amendments to the claims have overcome the respective claim objections and claim
rejections under 35 U.S.C. 102 and 35 U.S.C. 103, as previously formulated in the Non-Final Office action mailed on 9/29/2025. Accordingly, all previous specification objections and claim rejections are hereby withdrawn. Accordingly, pending in this application are claims 1-18 and 20-21.
Applicant’s arguments filed on 12/29/2025 have been fully considered but they are not persuasive. In response to the applicant’s arguments that the secondary reference Jo teaches the structure serving a different function as compared to the claimed HZO layer, but it is noted that the examiner is entitled to the broadest reasonable interpretation of the claim language. Additionally, although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). In addition, it’s noted that Jo simply discloses a known material configuration to be included within a capacitor of a memory device, which is considered relevant within the instant application.
New grounds of rejections are presented below, however, as necessitated by applicant’s amendments to the claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13, 15, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 13 recites the limitation “…the stack of interleaving insulator layers…" in line 14. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, “the stack of interleaving insulator layers” will be construed to recite “the stack of interleaving HfO2 and ZrO2 layers”.
Claims 15 recites the limitation “…the stack of interleaving insulator layers…" in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, “the stack of interleaving insulator layers” will be construed to recite “the stack of interleaving HfO2 and ZrO2 layers”.
Claim 20 recites the limitation "…the first insulator layer" in line 9. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, “the first insulator layer” will be construed to recite “the insulator layer”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, and 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Yin (US 20210098564 A1) in view of De Rochement (US 20180358295 A1).
Regarding claim 1, Yin (see, e.g., fig. 16) shows most aspects of the instant invention including a device (e.g., semiconductor device 200) comprising:
A substrate (e.g., substrate 202) including one or more semiconductor devices (see, e.g., paragraph 18 “…the substrate 202 includes one or more active and/or passive semiconductor devices…”);
A first passivation layer (e.g., first passivation layer 252) disposed over the one or more semiconductor devices (see, e.g., paragraph 18 “…the substrate 202 includes one or more active and/or passive semiconductor devices…”);
A metal-insulator-metal (MIM) capacitor structure (e.g., MIM structure 260, composed of bottom conductor plate layer 262 + insulator layer 264 + middle conductor plate layer 266, etc.) includes a first conductor plate layer (e.g., bottom conductor plate layer 262), a first insulator layer (e.g., insulator layer 264) on the first conductor plate layer (e.g., bottom conductor plate layer 262), a second conductor plate layer (e.g., middle conductor plate layer 266) on the first insulator layer (e.g., insulator layer 264), a second insulator layer (e.g., insulator layer 268) on the second conductor plate layer (e.g., middle conductor plate layer 266), and a third conductor plate layer (e.g., top conductor plate layer 269) on the second insulator layer (e.g., insulator layer 268), a third insulator layer (e.g., first dielectric portion 271) on the third conductor plate layer (e.g., top conductor plate layer 269), and wherein the combination of the first (e.g., insulator layer 264), second (e.g., insulator layer 268), and third insulator layer (e.g., first dielectric portion 271) include a metal oxide sandwich structure (see, e.g., paragraph 31 “…the insulator layer 264 (or the insulator layer 268)… may include a tri-layer structure including, from bottom to top, a first zirconium oxide (ZrO.sub.2) layer, an aluminum oxide (Al.sub.2O.sub.3) layer, and a second zirconium oxide (ZrO.sub.2) layer…”, so note the combination of layers 264 + 268 + 271 includes a metal oxide sandwich structure).
Yin (see, e.g., fig. 16), however, fails to show a fourth conductor plate layer on the third insulator layer.
De Rochemont (see, e.g., fig. 4B), in a similar device to Yin, teaches a fourth conductor plate layer (e.g., primary conductor layer 316A) on a third insulator layer (e.g., high energy density capacitive dielectric layer 320A).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the fourth conductor plate layer of De Rochemont, on the metal-insulator-metal stack and third insulator layer of Yin, in order to achieve the expected result of improving capacitance density within the device.
Additionally, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the invention to duplicate at insulator layer conductor plate layer configuration of the stack of Yin onto the top of the stack, to achieve the expected
result of increasing the capacitance structure’s area and thus improving the capacitance density within the device, since it has been held that a mere duplication of working parts of a device involves only routine skill in the art. In re Harza 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04.
Regarding claim 2, Yin (see, e.g., fig. 16) shows a second passivation layer (e.g., second passivation layer 270) disposed over the MIM capacitor structure (e.g., MIM structure 260 composed of bottom conductor plate layer 262 + insulator layer 264 + middle conductor plate layer 266, etc.).
Regarding claim 3, Yin (see, e.g., fig. 16) shows the metal oxide sandwich structure (see, e.g., paragraph 31 “…the insulator layer 264… may include a tri-layer structure including, from bottom to top, a first zirconium oxide (ZrO.sub.2) layer, an aluminum oxide (Al.sub.2O.sub.3) layer, and a second zirconium oxide (ZrO.sub.2) layer…”) includes a bottom insulator layer (e.g., first zirconium oxide layer of paragraph 31), a middle insulator layer (e.g., aluminum oxide layer of insulator layer, see paragraph 31) over the bottom insulator layer (e.g., first zirconium oxide layer of insulator layer, see paragraph 31), and a top insulator layer (e.g., second zirconium oxide layer of insulator layer, see paragraph 31) over the middle insulator layer (e.g., aluminum oxide layer of insulator layer, see paragraph 31).
Regarding claim 6, Yin (see, e.g., fig. 16) shows the bottom insulator layer (e.g., first zirconium oxide layer of insulator layer, see paragraph 31) and the top insulator layer (e.g., second zirconium oxide layer of insulator layer, see paragraph 31) include a zirconium oxide (ZrO2) layer (see, e.g., paragraph 31).
Regarding claim 9, Yin (see, e.g., fig. 16) shows a multi-layer interconnect (MLI) structure (see, e.g., paragraph 19 “…the substrate 202 may also include an interconnect structure such as a multi-layer interconnect (MLI) structure…”) at least partially disposed within the substrate (e.g., substrate 202), wherein the first passivation layer (e.g., first passivation layer 252) is disposed over the MLI structure (e.g., MLI structure portion within substrate 202, see paragraph 19).
Regarding claim 10, Yin (see, e.g., fig. 16) shows a contact feature (e.g., contact feature 287) disposed over the second passivation layer (e.g., second passivation layer 270), wherein the contact feature (e.g., contact feature 287) is electrically coupled (see, e.g., paragraph 26 “…lower contact features…254…represent a top metal layer of the MLI structure, previously discussed” + see contact point between contact feature 287 and lower contact feature 254) to the MLI structure (e.g., MLI structure portion extending to the lower contact features, see paragraph 19) .
Regarding claim 11, Yin (see, e.g., fig. 16) shows an upper portion of the contact feature (e.g., contact feature 287) includes a redistribution layer (RDL) (see, e.g., paragraph 46 “…an upper portion of the upper contact features …287… are part of a redistribution layer…”).
Regarding claim 12, Yin (see, e.g., fig. 16) shows a third passivation layer (e.g., third passivation layer 290) disposed over the second passivation layer (e.g., second passivation layer 270), wherein the contact feature (e.g., MLI structure portion within substrate 202, see paragraph 19) is disposed within the third passivation layer (e.g., third passivation layer 290).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Yin in view of De Rochemont further in view of Basceri (US 20030213987 A1).
Regarding claim 4, Yin in view of De Rochemont fails to teach the middle insulator layer is composed of a stack of two types of interleaving insulator layers having different material composition, and wherein one type of insulator layer of the stack of two types of interleaving insulator layers has a same material composition as the bottom insulator layer and the top insulator layer.
Basceri (see, e.g., fig. 16), in a similar device to Yin in view of De Rochemont, teaches an insulator layer (e.g., Al.sub.2O.sub.3 composite stack layer) is composed of a stack of two types of interleaving insulator layers having a different material composition, and wherein one type of insulator layer of the stack of two types of interleaving insulator layers has a same material composition as the bottom insulator layer and the top insulator layer (see, e.g., paragraph 65 “ The Al.sub.2O.sub.3 composite stack layer 80 may be also formed as a plurality of interleaved layers of Al.sub.2O.sub.3 and a combination of dielectric metal oxides, for example, a combination of any of zirconium oxide (ZrO.sub.2), hafnium oxide (HfO)…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the interleaving insulator layers of Basceri within the middle insulator layer of Yin (note that the middle insulator of Yin is also Al.sub.2O.sub.3) in view of De Rochemont, in order to create a more effective multi-functional insulating structure. In addition, these interleaving materials were well-known in the art at the time of filing the invention to be included within an Al2O3, as taught by Basceri. Note that ZrO2 is one of the disclosed types of interleaving insulator layers, and hence shares a same material composition with the bottom insulator layer and top insulator layer of Yin.
Regarding claim 5, Basceri (see, e.g., fig. 16) does not explicitly teach a bottommost layer of the stack of interleaving insulating layers is composed of the same material as the bottom insulator layer and the top insulator layer.
However, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to arrange the ZrO2 layers disclosed within the insulating layer-stack of Basceri to the bottommost layer of said stack, as there are limited arrangements of the interleaved layers possible within the disclosure of Basceri, and this outcome would be obvious to try for one of ordinary skill in the art for the purpose of diversifying the insulator profile of Yin in view of De Rochemont.
Claims 7-8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yin in view of De Rochemont further in view of Jo (US 20240213349 A1).
Regarding claim 7, Yin in view of De Rochemont fails to teach the middle insulator layer includes a hafnium-zirconium oxide layer that includes interleaving HfO2 and ZrO2 layers.
Jo (see, e.g., fig. 1), in a similar device to Yin in view of De Rochemont, teaches an insulator layer (e.g., second oxide layer 35) includes a HZO layer (see, e.g., paragraph 59 “…the second oxide layer (e.g., the HZO layer)…”) that includes interleaving HfO2 and ZrO2 layers (see, e.g., paragraph 59 “ the second oxide layer may be formed of a solid solution layer formed using a solid solution deposition method in which HfO2 and ZrO2 are alternately deposited in one cycle or multiple cycles, and thus, the ferroelectric layer may have a ZrO2/HZO thin film structure”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the HZO layer including the interleaving HfO2 and ZrO2 layers of Jo within the middle insulator of Yin in view of De Rochemont, in order to achieve the expected result of providing the varied dielectric profile within the capacitor structure, as taught by Jo.
Regarding claim 8, Yin in view of De Rochemont fails to teach a first thickness of the middle insulator layer is at least ten times greater than a second thickness of either the bottom insulator layer or the top insulator layer.
Jo (see, e.g., fig. 1), in a similar device to Yin in view of De Rochemont, teaches a first thickness of an insulating HZO layer (e.g., second oxide layer 35 + paragraph 73 “…the second oxide layer 35 may be formed of…(HZO)…”) is at least ten times greater than a second thickness (see, e.g., paragraph 74 “…a thickness ratio of HZO to ZrO2 may be 2:1 to 10:1.”) of an insulating ZrO2 layer (e.g., first oxide layer 31 + paragraph 73 “…the first oxide layer 31 may be formed as a ZrO2 layer…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thickness ratio of Jo within the configuration of Yin in view of De Rochemont, in order to manipulate the capacitance within the capacitor structure of Yin to desirable magnitudes within the insulator layer of the capacitor, enhancing reliability of the device.
Regarding claim 16, Yin (see, e.g., fig. 16) fails to show a first thickness of the HZO layer is at least ten times greater than a second thickness of either the first ZrO2 layer or the second ZrO2 layer.
Jo (see, e.g., fig. 1), in a similar device to Yin, teaches a first thickness of a HZO layer (e.g., second oxide layer 35 + paragraph 73 “…the second oxide layer 35 may be formed of…(HZO)…”) is at least ten times greater than a second thickness (see, e.g., paragraph 74 “…a thickness ratio of HZO to ZrO2 may be 2:1 to 10:1.”) of a ZrO2 layer (e.g., first oxide layer 31 + paragraph 73 “…the first oxide layer 31 may be formed as a ZrO2 layer…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thickness ratio of Jo within the configuration of Yin, in order to manipulate the capacitance within the capacitor structure of Yin to desirable magnitudes within the insulator layer of the capacitor, enhancing reliability of the device.
Claims 13-15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yin in view of Kuo (US 20150048483 A1) further in view of Basceri.
Regarding claim 13, Yin (see, e.g., fig. 16) shows most aspects of the instant invention including a device (e.g., semiconductor device 200) comprising:
A first passivation layer (e.g., first passivation layer 252) over a substrate (e.g., substrate 202) including an active semiconductor device (see, e.g., paragraph 18 “…the substrate 202 includes one or more active and/or passive semiconductor devices…”)
A metal-insulator-metal (MIM) structure (e.g., MIM structure 260, composed of bottom conductor plate layer 262 + insulator layer 264 + middle conductor plate layer 266 + insulator layer 268 + top conductor plate layer 269) formed over the first passivation layer (e.g., first passivation layer 252), wherein the MIM structure comprises:
A plurality of conducive plate layers (e.g., bottom conductor plate layer 262 + middle conductor plate layer 266 + top conductor plate 269); and
An insulator layer (e.g., insulator layer 264) interposing adjacent conductor plate layers of the plurality of conductor plate layers (e.g., bottom conductor plate layer 262 + middle conductor plate layer 266 + top conductor plate 269);
Wherein the insulator layer (e.g., insulator layer 264) includes a multi-layer structure (see, e.g., paragraph 31 “…the insulator layer 264… may include a tri-layer structure including, from bottom to top, a first zirconium oxide (ZrO.sub.2) layer, an aluminum oxide (Al.sub.2O.sub.3) layer, and a second zirconium oxide (ZrO.sub.2) layer…”), and wherein the multilayer structure (see, e.g., paragraph 31 “…the insulator layer 264… may include a tri-layer structure including, from bottom to top, a first zirconium oxide (ZrO.sub.2) layer, an aluminum oxide (Al.sub.2O.sub.3) layer, and a second zirconium oxide (ZrO.sub.2) layer…”) includes a first zirconium oxide (ZrO2) layer (e.g., first zirconium oxide layer of paragraph 31), a second ZrO2 layer (e.g., second zirconium oxide layer of insulator layer, see paragraph 31), and a middle layer interposing the first (e.g., first zirconium oxide layer of paragraph 31) and second (e.g., second zirconium oxide layer of insulator layer, see paragraph 31) ZrO2 layers.
Yin (see, e.g., fig. 16), however, fails to show the middle layer includes a hafnium-zirconium oxide (HZO) layer, while it also fails to show wherein the HZO layer includes a stack of interleaving HfO2 and ZrO2 layers, and wherein adjacent layers of the stack of interleaving HfO2 and ZrO2 layers have different thicknesses.
Kuo (see, e.g., fig. 1), in a similar device to Yin, teaches a middle insulator (e.g., insulator layer 112) includes hafnium zirconium oxide (see, e.g., paragraph 23 “…insulator layer 112 includes…hafnium zirconium oxide”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the hafnium-zirconium oxide of Kuo within the middle insulator layer, as hafnium-zirconium oxide was a well-known medium in the art at the time of filing the invention as a material to be used as an insulation layer within a capacitor structure, as taught by Kuo.
Yin in view of Kuo, however, fails to teach wherein the HZO layer includes a stack of interleaving HfO2 and ZrO2 layers, wherein adjacent layers of the stack of interleaving HfO2 and ZrO2 layers have different thicknesses.
Basceri (see, e.g., fig. 16), in a similar device to Yin in view of Kuo, teaches an insulator layer (e.g., Al.sub.2O.sub.3 composite stack layer) includes a stack of interleaving insulating layers (see, e.g., paragraph 65 “The Al.sub.2O.sub.3 composite stack layer 80 may be also formed as a plurality of interleaved layers of Al.sub.2O.sub.3 and a combination of dielectric metal oxides, for example, a combination of any of zirconium oxide (ZrO.sub.2), hafnium oxide (HfO)…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the interleaving insulator layers of Basceri within the middle insulator layer of Yin (note that the middle insulator of Yin is also Al.sub.2O.sub.3), in order to create a more effective multi-functional insulating structure. In addition, these interleaving materials were well-known in the art at the time of filing the invention to be included within an Al2O3, as taught by Basceri. Note that ZrO2 is one of the disclosed types of interleaving insulator layers, and hence shares a same material composition with the bottom insulator layer and top insulator layer of Yin.
Yin in view of Kuo further in view of Basceri fails to explicitly teach wherein adjacent layers of the stack of interleaving HfO2 and ZrO2 layers have different thicknesses. However, ranges of
thickness will not support the patentability of subject matter encompassed by the prior art
unless there is evidence indicating such ranges are critical. “Where the general conditions
of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by
routine experimentation” In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). Since the applicant has not established criticality (see next paragraph below), it would have been obvious to modify the interleaving layer thicknesses of Yin in view of Kuo further in view of Basceri, in order to modify/diversify the insulating profile of the capacitor within the device as desired.
CRITICALITY: The specification contains no disclosure of either the critical nature of the
claimed length ranges or any unexpected results arising therefrom. Where patentability is
said to be based upon particular chosen dimensions or upon another variable recited in a
claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919
F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 14, Yin (see, e.g., fig. 16) shows a second passivation layer (e.g., second passivation layer 270) disposed over the MIM structure (e.g., MIM structure 260 composed of bottom conductor plate layer 262 + insulator layer 264 + middle conductor plate layer 266, et cetera).
Regarding claim 15, Basceri (see, e.g., fig. 16) teaches a stack of interleaving insulating layers includes ZrO2 (see, e.g., paragraph 65 “The Al.sub.2O.sub.3 composite stack layer 80 may be also formed as a plurality of interleaved layers of Al.sub.2O.sub.3 and a combination of dielectric metal oxides, for example, a combination of any of zirconium oxide (ZrO.sub.2).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to arrange the ZrO2 layers disclosed within the insulating layer-stack of Basceri to the bottommost layer of said stack, as there are limited arrangements of the interleaved layers possible within the disclosure of Basceri, and this outcome would be obvious to try for one of ordinary skill in the art within the layer of Yin in view of Kuo further in view of Basceri.
Regarding claim 17, Yin (see, e.g., fig. 16) shows a number of conductor plate layers in the plurality of conductor plate layers is between about 2 and 10 (e.g., bottom conductor plate layer 262 + middle conductor plate layer 266 + top conductor plate 269; three distinct conductor plate layers).
Yin (see, e.g., fig. 16), however, fails to show the middle layer includes a hafnium-zirconium oxide (HZO) layer.
Kuo (see, e.g., fig. 1) teaches a middle insulator (e.g., insulator layer 112) includes hafnium zirconium oxide (see, e.g., paragraph 23 “…insulator layer 112 includes…hafnium zirconium oxide”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the hafnium-zirconium oxide of Kuo within the middle insulator layer of Yin in view of Kuo further in view of Basceri, as hafnium-zirconium oxide was a well-known medium in the art at the time of filing the invention as a material to be used as an insulation layer within a capacitor structure, as taught by Kuo.
Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yin in view of Jo further in view of Lee (US 20120003808 A1).
Regarding claim 18, Yin (see, e.g., fig. 16) shows most aspects of the instant invention including a method comprising:
Depositing (see, e.g., paragraph 27) a first passivation layer (e.g., first passivation layer 252) over a substrate (e.g., substrate 202) including one or more semiconductor devices (see, e.g., paragraph 18 “…the substrate 202 includes one or more active and/or passive semiconductor devices…”)
Forming a metal-insulator-metal (MIM) capacitor (e.g., MIM structure 260) over the first passivation layer (e.g., first passivation layer 252), wherein forming the MIM capacitor (e.g., MIM structure 260, composed of bottom conductor plate layer 262 + insulator layer 264 + middle conductor plate layer 266 + insulator layer 268 + top conductor plate layer 269) includes:
Forming a patterned first conductor plate (e.g., bottom conductor plate 262 + paragraph 29 “…patterned bottom conductive layer 262…”) over the first passivation layer (e.g., first passivation layer 252);
Depositing (see, e.g., paragraph 29) an insulator layer (e.g., insulator layer 264) over the patterned first conductor plate (e.g., bottom conductor plate 262 + paragraph 29 “…patterned bottom conductive layer 262…”), wherein the insulator layer (e.g., insulator layer 264) includes:
a metal oxide sandwich structure (see, e.g., paragraph 31 “…the insulator layer 264… may include a tri-layer structure including, from bottom to top, a first zirconium oxide (ZrO.sub.2) layer, an aluminum oxide (Al.sub.2O.sub.3) layer, and a second zirconium oxide (ZrO.sub.2) layer…”) having a bottom layer (e.g., first zirconium oxide layer of paragraph 31) including a first zirconium oxide ZrO2 layer (see, e.g., paragraph 31), a middle layer (e.g., aluminum oxide layer of insulator layer, see paragraph 31) over the bottom layer (e.g., first zirconium oxide layer of insulator layer, see paragraph 31), and a top layer (e.g., second zirconium oxide layer of insulator layer, see paragraph 31) including a second ZrO2 layer (see, e.g., paragraph 31) over the middle layer (e.g., aluminum oxide layer of insulator layer, see paragraph 31);
Forming a patterned second conductor plate (e.g., top conductor plate 269 + paragraph 29 “…patterned top conductor plate layer 269…”) over the insulator layer (e.g., insulator layer 264)
Yin (see, e.g., fig. 16), however, fails to teach the middle insulator layer includes a half-zirconium oxide layer that includes interleaving HfO2 and ZrO2 layers, wherein the interleaving HfO2 and ZrO2 layers each have a different thickness, wherein the HZO layer is more than ten times thicker than the first ZrO2 layer and the second ZrO2 layer, and wherein each of the bottom layer, the middle layer, and the top layer are conformally deposited over each other using ALD.
Jo (see, e.g., fig. 1), in a similar device to Yin, teaches an insulator layer (e.g., second oxide layer 35) includes a HZO layer (see, e.g., paragraph 59 “…the second oxide layer (e.g., the HZO layer)…”) that includes interleaving HfO2 and ZrO2 layers (see, e.g., paragraph 59 “ the second oxide layer may be formed of a solid solution layer formed using a solid solution deposition method in which HfO2 and ZrO2 are alternately deposited in one cycle or multiple cycles, and thus, the ferroelectric layer may have a ZrO2/HZO thin film structure”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the HZO layer including the interleaving HfO2 and ZrO2 layers of Jo within the middle insulator of Yin, in order to achieve the expected result of providing the varied dielectric profile within the capacitor structure, as taught by Jo.
Jo (see, e.g., fig. 1), in a similar device to Yin, teaches an insulator layer (e.g., second oxide layer 35) includes a HZO layer (see, e.g., paragraph 59 “…the second oxide layer (e.g., the HZO layer)…”) that includes interleaving HfO2 and ZrO2 layers (see, e.g., paragraph 59 “ the second oxide layer may be formed of a solid solution layer formed using a solid solution deposition method in which HfO2 and ZrO2 are alternately deposited in one cycle or multiple cycles, and thus, the ferroelectric layer may have a ZrO2/HZO thin film structure”), and a first thickness of an insulating HZO layer (e.g., second oxide layer 35 + paragraph 73 “…the second oxide layer 35 may be formed of…(HZO)…”) is at least ten times greater than a second thickness (see, e.g., paragraph 74 “…a thickness ratio of HZO to ZrO2 may be 2:1 to 10:1.”) of an insulating ZrO2 layer (e.g., first oxide layer 31 + paragraph 73 “…the first oxide layer 31 may be formed as a ZrO2 layer…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the HZO layer including the interleaving HfO2 and ZrO2 layers of Jo within the middle insulator of Yin, in order to achieve the expected result of providing the varied dielectric profile within the capacitor structure, as taught by Jo. In addition, it also would have been obvious to include the thickness ratio of Jo within the configuration of Yin, in order to manipulate the capacitance within the capacitor structure to desirable magnitudes within the insulator layer of the capacitor, enhancing reliability of the device.
Yin in view of Jo fails to explicitly teach wherein adjacent layers of the stack of interleaving HfO2 and ZrO2 layers each have different thicknesses. However, ranges of thickness will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ranges are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). Since the applicant has not established criticality (see next paragraph below), it would have been obvious to modify the interleaving layer thicknesses of Yin in view of Jo, in order to modify/diversify the insulating profile of the capacitor within the device as desired.
CRITICALITY: The specification contains no disclosure of either the critical nature of the
claimed length ranges or any unexpected results arising therefrom. Where patentability is
said to be based upon particular chosen dimensions or upon another variable recited in a
claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919
F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Yin in view of Jo, however, fails to teach wherein each of the bottom layer, the middle layer, and the top layer are conformally deposited over each other using ALD.
Lee (see, e.g., fig 4), in a similar device to Yin in view of Jo, teaches ZrO2 can be deposited with atomic layer deposition (see, e.g., paragraph 44 “…The dielectric film used for the storage devices can be formed with Atomic Layer Deposition (ALD) films such as Al2O3, HfO2 and ZrO2…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the atomic layer deposition (ALD) of Lee within the method of Yin in view of Jo, as atomic layer deposition was a well-known technique at the time of filing the invention as a technique of depositing zirconium oxide dielectric layers.
Regarding claim 20, Yin (see, e.g., fig. 16) shows forming the MIM capacitor (e.g., MIM structure 260) further includes: prior to forming the patterned second conductor plate layer (e.g., top conductor plate 269 + paragraph 29 “…patterned top conductor plate layer 269…”), forming one or more additional conductor plates (e.g., middle conductor plate 266) over the insulator layer (e.g., insulator layer 264), wherein the one or more additional conductor plates (e.g., middle conductor plate 266) include the insulator layer (e.g., insulator layer 264) interposing at least one adjacent conductor plate of the one or more additional conductor plates (e.g., middle conductor plate 266), and wherein a second insulator layer (e.g., insulator layer 268) is also deposited over a topmost conductor plate (e.g., middle conductor plate 266) of the one or more additional conductor plates (e.g., middle conductor plate 266), the second insulator layer (e.g., insulator layer 268) having a same structure and composition (see, e.g., paragraph 31) as the insulator layer (e.g., insulator layer 264).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Yin in view of Jo further in view of Lee and Yang (US 11778809 B1).
Yang (see, e.g., claims 1 and 5), in a similar device to Yin in view of Jo further in view of Lee, teaches an HZO layer (e.g., HZO layer of claim 1) is conformally deposited (e.g., plasma atomic layer deposit of claim 1) to have a thickness in a range between 5-7 nm (see, e.g., claim 5 “…a thickness of the HZO layer is in a range between 4 nm and 6 nm”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the 6 nm HZO layer range of Yang within the HZO layer of Yin in view of Jo further in view of Lee, in order to limit the cost of fabrication during the manufacturing of the device while still providing a distinct HZO profile within the capacitor configuration.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas McCoy at (571) 272-0282 and between the hours of 9:30 AM to 6:30 PM (Eastern Standard Time) Monday through Friday or by e-mail via Thomas.McCoy@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit
https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and
https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional
questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like
assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or
571-272-1000.
/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814