DETAILED ACTION
This Office action responds to the patent application no. 18/336,183 filed on June 16, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 16, 2023, cited two identical U.S. Patent Numbers 9520482 (#8 and #18). Hence the first cited one (#8) is considered and the repeatedly cited second one (#18) is stroke-out.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: Claim 9 recites the limitation "the dipole layer is a first dipole layer and contains yttrium and scandium" in line 2. There is insufficient antecedent basis for this limitation in the claim. The specification teaches the dipole layer contains either yttrium or scandium, not yttrium and scandium.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 9 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 9 recites the limitation "the dipole layer is a first dipole layer and contains yttrium and scandium" in line 2. However, the specification (¶ [0017], [0031], [0052], [0058], [0070], [0079]) teaches the dipole layer contains either yttrium or scandium, not yttrium and scandium.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(2) as being clearly anticipated by Bao et al. (Bao hereinafter) (US 2023/0075740).
Regarding Claims 1 and 2:
Bao (see ¶ [0003], [0005], [0046], [0047] and FIGs. 1A, 1B, 2B, and 2C) teaches a device, comprising: an active region (109); a dipole layer (black bar) disposed over the active region; a doped gate dielectric layer (130) disposed over the dipole layer; and a metal-containing gate electrode (170/180) disposed over the doped gate dielectric layer and “the first high-k dielectric layer may be thicker than the second high-k dielectric layer … the first high-k dielectric layer and the second high-k dielectric layer are each a material independently selected from hafnium oxide, zirconium oxide, tantalum oxide, strontium titanate, titanium oxide, aluminum oxide, and yttrium oxide”, “the dopant in the Ti-dopant mixing layer can be lanthanum, magnesium, aluminum, or yttrium”, ”HK1 130 and HK2 150 are the same material (e.g., amorphous HfO2) … are not the same material … adjusting the thickness and composition of layers 130 and 150 may be used to adjust the threshold voltage”, and “the anneal may take place … for driving the lanthanum in the Ti-dopant mixing layer 140 far enough into the HK1 layer 130 to move the dipole to the HK1 layer 130/IL 120 interface”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Bao et al. (Bao hereinafter) (US 2023/0075740) as applied to claim 1 above, and in view of Kim et al. (Kim hereinafter) (US 2012/0270409).
Regarding Claims 3 and 4:
Bao teaches the instant invention except for wherein the dielectric material at least partially has a crystal phase.
Kim (see ¶ [0006], [0008], [0028]) teaches “As the gate length of silicon CMOS devices is scaled to less than 100 nm, new high dielectric constant (K) materials will likely replace silicon oxide”, “Insulators (referred to as high-k dielectrics) that have a larger dielectric constant than silicon dioxide … hafnium and zirconium silicates and oxides are being used to reduce the gate leakage … Increasing the dielectric constant of the gate dielectric allows a thicker layer while maintaining a high capacitance … a higher dielectric thickness reduces the quantum tunneling current through the dielectric between the gate and the channel”, “Hafnium oxide has several polymorphs, each with a different dielectric constant … amorphous (k~16-19), monoclinic (k~20-25), cubic (k~29) and tetragonal (k~70) …”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Bao to include the teaching of Kim to selectively anneal the gate structure to higher temperature so that the first and second high-k dielectric layer with amorphous phase being changed to cubic phase with higher dielectric constant in order to reduce the gate current leakage and quantum tunneling current.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Bao et al. (Bao hereinafter) (US 2023/0075740) as applied to claim 1 above, and in view of Wang et al. (Wang hereinafter) (US 2021/0376109).
Regarding Claim 5:
Bao teaches the instant invention except for the metal-containing gate electrode has a third concentration level of yttrium; and the third concentration level is less than the second concentration level.
Wang (see Abstract, ¶ [0007], [0008], [0012], [0051], [0052], and [0066]) teaches “a doped gate metal layer on the HK insulating layer to shift the modulated Vt in a second direction”, “the second direction may be opposite the first direction … may be the same as the first direction”, “the doped gate metal layer may include at least one of … LaO-doped TiN, … ZrO doped TaN, lanthanide metal-doped TiN, La-doped TaN, or a combination thereof”, “the doped gate metal layer may independently shift the modulated Vt in a second direction and/or in a second magnitude”, “the degree or magnitude of the modulation (shift) by the ultrathin dielectric dipole layer may be larger than that of the doped gate metal layer. The first direction, the second direction, and the magnitudes of each shift may be selected to yield a desired Vt value”, and “the doped gate metal layer may have a doped amount of greater than 0 atomic percent (at %) to 4 at %”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Bao to include the teaching of Wang to use doped gate metal layer to add another independent method to modulate the threshold voltage to a desired level for the transistor and to use known liked dopant, such as yttrium besides La, Zr in the doped gate metal layer to module the threshold voltage and to expect the increased doping concentration profile from the doped gate metal layer to the HK gate dielectric layer and to dipole layer to achieve the desired overall threshold voltage for the transistor.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Bao et al. (Bao hereinafter) (US 2023/0075740) as applied to claim 1 above, and in view of Wang (Wang2 hereinafter) (US 11,069,576).
Regarding Claims 6 and 7:
Bao teaches the instant invention except for a second active region; a second dipole layer disposed over the second active region, wherein the second dipole layer and the first dipole layer have different thicknesses.
Wang2 (see col.7/ll.44-47 and FIG. 2D) teaches the different thickness of the dipole layer 212A, 212B, 212C, and 210D being used for 4 different components 240, 242, 244, and 246 to form the gate structures and “the dipoles formed using the dipole combinations … may shift the baseline Vt up or down, depending upon the material(s) and thickness(es) used in the dipole layers …”
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Bao to include the teaching of Wang2 to form another gate structure consisting of dipole layer and gate dielectric layer and metal-containing gate electrode and varying the material and thickness of the dipole layers in order to attain the desired different threshold voltages as the instant invention.
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Bao et al. (Bao hereinafter) (US 2023/0075740) as applied to claim 1 above, and in view of Du (US 2014/0252306) and further in view of Wang (Wang2 hereinafter) (US 11,069,576).
Regarding Claims 8 and 9:
Bao teaches the instant invention except for components of a first gate structure of a top-tier device of a complementary field effect transistor (CFET); the CFET further includes a bottom-tier device that is bonded to the top-tier device; the bottom-tier device includes a second gate structure; and the second gate structure and the first gate structure include different types of dipole layers.
Du (see Abstract, ¶ [0019], [0024], [0042], FIGs. 1-3) teaches “a top tier nanowire transistors formed on a bottom tier of CMOS transistors … The first wafer is flipped and oxide bonded to a second wafer having CMOS devices”, “a p-type channel field pinched nanowire transistor 110, an n-type field pinched nanowire transistor 112 …”, “an active layer (top tier) comprising various n-type and p-type regions …”.
Wang2 (see col.6/ll.9-15 and col.7/ll.44-47 and Claims, and FIG. 2D) teaches the different thickness of the dipole layer 212A, 212B, 212C, and 210D being used for 4 different components 240, 242, 244, and 246 to form the gate structures and “for example, the first dipole layer may be LaSiOx, the second dipole layer may be AlSiOx, the first high dielectric constant layer may be HfO2 and the second high dielectric constant layer may be ZrAlOx …the second dipole combination is different from the first dipole combination and may provide a different shift in Vt”, “the dipoles formed using the dipole combinations … may shift the baseline Vt up or down, depending upon the material(s) and thickness(es) used in the dipole layers …” and “the first dipole layer and the second dipole layer being selected from lanthanum oxide, lanthanum silicon oxide, aluminum oxide and yttrium oxide”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Bao to include the teaching of Du to apply the technique of modulating the threshold voltage of MOSFETs to any known configurations of integrated circuits, such as 3D stacked and bonded wafers to achieve the desired device performance and utilization and to further include the teaching of Wang2 to select known dipole material, such as yttrium and lanthanum and use different dipole material in different dipole layers to modulate the threshold voltage of the MOSFET transistors for desired device performance and application.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Bao et al. (Bao hereinafter) (US 2023/0075740) in view of Du (US 2014/0252306) and further in view of Wang (Wang2 hereinafter) (US 11,069,576).
Regarding Claims 10 and 11:
Bao (see ¶ [0005] and [0047] and FIGs. 1A, 1B, 2B, and 2C) teaches a semiconductor device with the gate structure comprising of an interfacial layer, a dipole layer, a high-k dielectric layer, a gate electrode and “the dopant in the Ti-dopant mixing layer can be lanthanum, magnesium, aluminum, or yttrium” and “the anneal may take place … for driving the lanthanum in the Ti-dopant mixing layer 140 far enough into the HK1 layer 130 to move the dipole to the HK1 layer 130/IL 120 interface”. However, Bao does not explicitly teach the two-tier structure of the transistors nor two transistors with different material for the dipole layer.
Du (see Abstract, ¶ [0019], [0024], [0042], FIGs. 1-3) teaches “a top tier nanowire transistors formed on a bottom tier of CMOS transistors … The first wafer is flipped and oxide bonded to a second wafer having CMOS devices”, “a p-type channel field pinched nanowire transistor 110, an n-type field pinched nanowire transistor 112 …”, “an active layer (top tier) comprising various n-type and p-type regions …”.
Wang2 (see col.6/ll.9-15 and col.7/ll.44-47 and Claims, and FIG. 2D) teaches the different thickness of the dipole layer 212A, 212B, 212C, and 210D being used for 4 different components 240, 242, 244, and 246 to form the gate structures and “for example, the first dipole layer may be LaSiOx, the second dipole layer may be AlSiOx, the first high dielectric constant layer may be HfO2 and the second high dielectric constant layer may be ZrAlOx …the second dipole combination is different from the first dipole combination and may provide a different shift in Vt”, “the dipoles formed using the dipole combinations … may shift the baseline Vt up or down, depending upon the material(s) and thickness(es) used in the dipole layers …” and “the first dipole layer and the second dipole layer being selected from lanthanum oxide, lanthanum silicon oxide, aluminum oxide and yttrium oxide”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Bao to include the teaching of Du to apply the technique of modulating the threshold voltage of MOSFETs to any known configurations of integrated circuits, such as 3D stacked and bonded wafers to achieve the desired device performance and utilization and to further include the teaching of Wang2 to select known dipole material, such as yttrium and lanthanum and use different dipole material in different dipole layers and their associated gate dielectric layer to modulate the threshold voltage of the MOSFET transistors for desired device performance and application.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Bao et al. (Bao hereinafter) (US 2023/0075740) in view of Du (US 2014/0252306) and further in view of Wang (Wang2 hereinafter) (US 11,069,576) as applied to claim 10 above, and further in view of Kim et al. (Kim hereinafter) (US 2012/0270409).
Regarding Claim 12:
Bao in the device of Du in view of Wang teaches the instant invention except for the first gate dielectric layer contains hafnium oxide with a cubic crystal phase or zirconium oxide with a tetragonal crystal phase.
Kim (see ¶ [0006], [0008], [0028]) teaches “As the gate length of silicon CMOS devices is scaled to less than 100 nm, new high dielectric constant (K) materials will likely replace silicon oxide”, “Insulators (referred to as high-k dielectrics) that have a larger dielectric constant than silicon dioxide … hafnium and zirconium silicates and oxides are being used to reduce the gate leakage … Increasing the dielectric constant of the gate dielectric allows a thicker layer while maintaining a high capacitance … a higher dielectric thickness reduces the quantum tunneling current through the dielectric between the gate and the channel”, “Hafnium oxide has several polymorphs, each with a different dielectric constant … amorphous (k~16-19), monoclinic (k~20-25), cubic (k~29) and tetragonal (k~70) …”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teachings of Bao of Du in view of Wang to further include the teaching of Kim to selectively anneal the gate structure to higher temperature so that the first and second high-k dielectric layer with amorphous phase being changed to cubic phase with higher dielectric constant in order to reduce the gate current leakage.
Claims 13-15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (Wang2 hereinafter) (US 11,069,576) and in view of Ma et al. (Ma hereinafter) (US 6,297,539) and further in view of Kim et al. (Kim hereinafter) (US 2012/0270409).
Regarding Claims 13-15, and 17:
Wang2 (see col.4/ll.9-65, col.5/ll.33-46, col.7/ll.44-47, and col.9/ll.36-51 and FIGs. 1 and 2A-2D) teaches a method of providing a gate structure for components on the semiconductor/channel (202), an interfacial/natural oxide layer formed of silicon dioxide may be formed prior the deposition of the dipole layer (212A, 212B, 212C, 212D) formed of Y2O3, YSiOx, ZrO2, ZrSiOx, ScO, or ScSiOx; an undoped or doped high dielectric constant layer (214A, 214B, 214C, 214D) formed of ZrO2, HfO2, HfSiOx, HfZrOx, ZrAlOx on the dipole layer, and a work function metal layer (220, 222, 224, 226) and contact metal layer (230, 232, 234, 236) formed on the high dielectric layer and “a high dielectric constant layer for the exposed regions is provided on the dipole layer, via step 128 … step 128 may be performed using ALD at temperatures of around three hundred degrees Celsius”.
However, Wang2 does not teach the doped high dielectric constant layer containing an amorphous material nor the anneal process being performed prior to the formation of the metal-containing gate electrode.
Ma (see col.1/l.67-col.2/l.16, col.3/ll.11-40) teaches “the film including a doping metal, a metal selected from the group consisting of zirconium (Zr), and hafnium(Hf), and oxygen. The doping metal … scandium (Sc), lanthanum (La), yttrium (Y) … the presence of doping metal tends to produce amorphous dielectric materials … reduces, or eliminates, the formation of crystalline structure”, “atomic layer chemical vapor deposition (ALCVD), which is also known as atomic layer deposition (ALD) … annealing at a temperature in the range of approximately 300 to 900 degrees C to condition the deposited layers, whereby a thin film having a high dielectric constant and good barrier properties is formed”.
Kim (see ¶ [0027], [0028]. [0053]) teaches “a known film HfO2 doped with another oxide with a higher-k value … the hafnium oxide film … can be grown by either atomic layer deposition (ALD) … In some ALD processes, there are a first number of first cycles comprising contacting a substrate surface with a first precursor … followed by the oxidant … a second number of second cycles comprising flowing the second precursor … followed by flowing oxidant … After deposition, the film may go through a post-deposition treatment such as annealing … to improve the material quality or change the morphology (e.g., crystallinity) to benefit the device performance”, “Hafnium oxide has several polymorphs, each with a different dielectric constant … cubic (k~29) … doping the hafnium oxide film with cerium oxide stabilizes the cubic or tetragonal phases at lower temperature and the doped films described may be at least partially of the tetragonal phase”, and “after the deposition the high-k film, additional processing may be performed … further comprising performing one or more of a post-deposition annealing on the high-k dielectric layer and a decoupled plasma nitridation process on the high-k dielectric layer”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Wang2 to include the teaching of Ma to clearly anticipate the doped high-k layer formed by ALD substantially being at amorphous phase and to further include the teaching of Kim to anneal the doped high-k layer after its formation to change its amorphous phase partially into crystal phase at lower temperature, in order to increase its dielectric constant and to improve the device performance.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Wang (Wang2 hereinafter) (US 11,069,576) and in view of Ma et al. (Ma hereinafter) (US 6,297,539) and further in view of Kim et al. (Kim hereinafter) (US 2012/0270409) as applied to claim 13 above, and in view of Cheng et al. (Cheng hereinafter) (US 2021/0098457) and furth in view of Galatage et al (Galatage hereinafter) (US 2016/0056253).
Regarding Claim 16:
Wang2 in the method of Ma in view of Kim does not explicitly teach the forming the doped gate dielectric layer comprises performing a first number of deposition cycles, wherein each cycle of the first number of deposition cycles comprises: depositing a sub-layer of undoped gate dielectric material, repeating the depositing of the sub-layer for a second number of times; and depositing an yttrium oxide layer over an uppermost one of the sub-layers of the undoped gate dielectric material.
Cheng (see ¶ [0021], [0038], [0081], [0083], [0088] and FIGs. 9 and 11E) teaches “the doped gate dielectric layers can be hafnium-based high-k … dielectric layers doped with a suitable material, such as lanthanum or magnesium … the gate dielectric layers can be doped by depositing an intrinsic gate dielectric layer and depositing one or more dopant-containing dielectric films on the intrinsic gate dielectric layer … an anneal process can be used to drive in the dopant from the dopant-containing films into the intrinsic gate dielectric layer”, “gate dielectric layers 120A-120F can be a crystalline state”, “first gate dielectric material 1102 can be deposited using ALD”, “first dopant material 1104 can include material that contain suitable dopants that can be driven into first gate dielectric and subsequently forming electric dipoles … can be a dielectric material containing lanthanum, magnesium, silicon, yttrium, gadolinium, strontium…”, and “an anneal process 1150 is performed to drive in dopants, such as lanthanum from first and/or second dopant layers 1104A and 1104B into underlying first gate dielectric material 102 … a greater number of dopant layers or dopant layers having greater thicknesses … resulting in greater dopant concentration”.
Galatage (see ¶ [0028]) teaches “the second dielectric layer 5 is a substantially pure or doped hafnium oxide material … is deposited by ALD with any suitable precursor over about 15 to about 40 cycles and at about 100° C to about 400° C … to a thickness of about 1.7 nm to about 3.0m”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Wang2 in the method of Ma in view of Kim to include the teaching of Cheng to select an well-known manufacturing process of high-k dielectric metal oxide, such as atomic layer deposition (ALD) for the undoped/intrinsic gate dielectric layer and to apply an anneal process immediately after the formation of dopant-containing layer on the gate dielectric layer, in order to drive in the dopants to the intrinsic gate dielectric layer so that it can become a doped gate dielectric layer to meet the manufacturing requirements and to further include the teaching of Galatage to clearly anticipate the well-known ALD process comprising of number of repeated cycles to deposit the metal oxide dielectric layer to reach a desired thickness to meet the device performance expectation.
Claim 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (Wang2 hereinafter) (US 11,069,576) and in view of Ma et al. (Ma hereinafter) (US 6,297,539) and further in view of Kim et al. (Kim hereinafter) (US 2012/0270409) as applied to claim 13 above, and in view of Kil et al. (Kil hereinafter) (US 7,772,132) and Franco et al. (Franco hereinafter) (US 2020/0176446).
Regarding Claims 18 and 19:
Wang2 in the method of Ma in view of Kim does not explicitly teach the converting comprises converting the doped zirconium oxide layer into a layer that at least partially has a tetragonal crystal phase nor the annealing process is performed with a process temperature that is less than about 500 degrees Celsius with a reason.
Kil (see col.4/ll.39-44) teaches the including additional step of supplying extra O3 gas during a unit cycle of the ALD process would improve the tetragonality of ZrO2 layer and “after depositing the ZrO2 layer … a post-annealing process may be performed at approximately 400° C to improve the tetragonality of the ZrO2 layer … crystallization can be formed due to the post annealing process … using the rapid thermal annealing process … the chamber has a temperature ranging from approximately 400° C to approximately 800° C”.
Franco (see ¶ [0062]) teaches “a reliability anneal (also referred to as a post-deposition anneal or a post metal anneal) … typically at temperature above 800° C … unsuitable for a top tier device in stacked CMOS technologies as the back end of line (BEOL) or bottom tier devices can be harmed by the high temperature”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Wang2 in the method of Ma in view of Kim to include the teaching of Kil to add additional step of supplying O3 gas during each unit cycle of the ALD process and to perform post-annealing process after depositing doped or undoped ZrO2 layer at lower temperature, such as 400° C to improve the tetragonality of ZrO2 layer for higher dielectric constant and to further include the teaching of Franco to select an appropriate temperature range, such as below approximately 500° C for multiple processes suitable for its IC architecture in order to avoid damage to the bottom-tier.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wang (Wang2 hereinafter) (US 11,069,576) and in view of Ma et al. (Ma hereinafter) (US 6,297,539) and further in view of Kim et al. (Kim hereinafter) (US 2012/0270409) as applied to claim 13 above, and further in view of Du (US 2014/0252306).
Regarding Claim 20:
Wang2 in the method of Ma in view Kim does not teach the portions of a gate of a top device of a complementary field effect transistor (CFET), wherein method further comprises: before the dipole layer is formed, bonding the top device to a bottom device of the CFET.
Du (see Abstract, ¶ [0019], [0024], [0042], FIGs. 1-3) teaches “a top tier nanowire transistors formed on a bottom tier of CMOS transistors … The first wafer is flipped and oxide bonded to a second wafer having CMOS devices”, “a p-type channel field pinched nanowire transistor 110, an n-type field pinched nanowire transistor 112 …”, “an active layer (top tier) comprising various n-type and p-type regions …”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Wang2 and Bao in view of Kim to include the teaching of Du to apply the technique of modulating the threshold voltage of MOSFETs to any known configurations of integrated circuits, such as 3D stacked and bonded wafers to achieve the desired device performance and utilization.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm..
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/ALICE W TANG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814