DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (“Kim”), US 2008/0179598 (the US counterpart of KR 10-2008-0074574 listed in the IDS), in view of Lee, US 2020/0144349.
Regarding Claim 1, Kim discloses a display device (3; Fig. 8; ¶ 0111) comprising:
a first transistor (Tdr; Fig. 8; ¶ 0113) comprising a first semiconductor layer (21, 211, 212; Figs. 8-9; ¶ 0112) and a second transistor (Tsw; Fig. 8; ¶ 0063) comprising a second semiconductor layer (51; Fig. 8; ¶ 0063), the first semiconductor layer and the second semiconductor layer positioned on a substrate (11; Fig. 8; ¶ 0086); and
a light emitting diode (LD; Fig. 1; ¶ 0032) connected to the first transistor (Fig. 1; ¶ 0034), wherein
the first transistor is a driving transistor (¶ 0032 “driving TFT Tdr”);
the second transistor is a switching transistor (¶ 0032 “switching thin film transistor (TFT) Tsw”);
a first concentration of fluorine (¶ 0112 “In the first layer 211, the fluorine content ranges from 1 at. % through 3 at. %.”) in the first semiconductor layer (in this instance layer 211 of 21) is higher than a second concentration of fluorine in the second semiconductor layer (¶ 0097 “the switching semiconductor layer 51 is made of amorphous silicon containing no fluorine”, ); and
a first difference between the first concentration and the second concentration (the difference between 1 at. % through 3 at. %. and 0, as explained supra) substantially at or near a first interface (Fig. 8 the lower surfaces of 211 and 51 that are closest to substrate 11) of each of the first semiconductor layer and the second semiconductor layer is larger than a second difference (¶ 0114 layer 212 of 21 contains no fluorine, ¶ 0097 layer 51 contains no fluorine; thus the second difference is 0) between the first concentration and the second concentration at a second interface (Fig. 8 the upper surfaces of 212 and 51 that are furthest from substrate 11) of each of the first semiconductor layer and the second semiconductor layer, the second interface further from the substrate than the first interface (Fig. 8 the upper surfaces of 212 and 51 are further from the substrate than the lower surfaces of 211 and 51).
Kim does not specifically disclose wherein the first semiconductor layer and the second semiconductor layer are at a same level in a direction perpendicular to the substrate.
Lee discloses wherein the first semiconductor layer (A1; Fig. 8; ¶ 0095 “semiconductor layer Al of the driving TFT T1”) and the second semiconductor layer (A2; Fig. 8; ¶ 0095 “semiconductor layer A2 of the switching TFT T2”) are at a same level (Fig. 8; ¶ 0095 “Referring to FIG. 8, the semiconductor layer Al of the driving TFT T1, the semiconductor layer A2 of the switching TFT T2…are formed on the substrate 101.”, ¶ 0096) in a direction perpendicular (Fig. 8) to the substrate (101; Fig. 8; ¶ 0095 “substrate 101”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kim to have wherein the first semiconductor layer and the second semiconductor layer are at a same level in a direction perpendicular to the substrate, as taught by Lee, because “a higher (or high) aperture ratio may be obtained, and thus, a display device having a higher (or high) color reproduction rate and a higher (or high) resolution may be implemented” (Lee ¶ 0134, see also ¶ 0006) thereby “improving a life span of the display” (Lee ¶ 0006).
Regarding Claim 6, Kim discloses wherein the first semiconductor layer and the second semiconductor layer are positioned on the same layer (Fig. 8 in this instance 21 and 51 are both positioned on substrate 11).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (“Kim”), US 2008/0179598, and Lee, US 2020/0144349, in view of Jeong et al. (“Jeong”), US 2019/0088794 (the US counterpart of KR 10-2019-0032681 listed in the IDS).
Regarding Claim 3, Kim as modified by Lee does not disclose further comprising a barrier layer that is positioned between the substrate and the first transistor and between the substrate and the second transistor, wherein a third concentration of fluorine in a first area of the barrier layer overlapping the first semiconductor layer is higher than a fourth concentration of fluorine in a second area of the barrier layer overlapping the second semiconductor layer.
Jeong discloses further comprising a barrier layer (111; Fig. 5; ¶ 0089-0090) that is positioned between the substrate (110, Fig. 5; ¶ 0047) and the first transistor (T2; Fig. 5; ¶ 0077) and between the substrate and the second transistor (158 of T1; Fig. 5; ¶ 0085), wherein a third concentration of fluorine in a first area of the barrier layer overlapping the first semiconductor layer (155 of T2; Figs. 5-6; ¶ 0090 “an upper region of the first insulating layer 111, that is, the region thereof adjacent to or closest to the driving semiconductor layer 155, is doped with fluorine”) is higher than a fourth concentration of fluorine in a second area of the barrier layer overlapping the second semiconductor layer (Fig. 5 in this instance there is no fluorine in the upper region of layer 111 adjacent thereof or closest to the switching semiconductor layer 151 of T1; ¶ 0053 “only a part of the region of the first insulating layer 111…in contact with the semiconductor layer 155 may be doped with fluorine”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kim as modified to have further comprising a barrier layer that is positioned between the substrate and the first transistor and between the substrate and the second transistor, wherein a third concentration of fluorine in a first area of the barrier layer overlapping the first semiconductor layer is higher than a fourth concentration of fluorine in a second area of the barrier layer overlapping the second semiconductor layer, as taught by Jeong, so that “the hydrogen concentration of the insulating layer adjacent to the semiconductor layer 155 decreases in a direction toward the semiconductor layer 155” (Jeong ¶ 0051) “thereby improving the reliability of the display device” (Jeong ¶ 0052).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (“Kim”), US 2008/0179598, and Lee, US 2020/0144349, in view of Miyairi et al. (Miyairi”), US 2010/0224879.
Kim as modified by Lee does not disclose wherein a concentration of fluorine is measured by comparing Secondary-ion mass spectrometry (SIMS) intensity.
Miyairi discloses wherein a concentration of fluorine is measured by comparing Secondary-ion mass spectrometry (SIMS) intensity (¶ 0083 “the secondary ion intensity…and the concentration profiles of…fluorine in a depth direction, which are measured by SIMS, of the… semiconductor layer 115 formed over the substrate”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Kim as modified to have wherein a concentration of fluorine is measured by comparing Secondary-ion mass spectrometry (SIMS) intensity, as taught by Miyairi, because the secondary ion intensity is measured with a mass spectrometer and SIMS is the most sensitive surface analysis technique, capable of detecting elements down to parts per billion levels.
Allowable Subject Matter
Claims 2, 4-5, and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 2, the prior art does not teach or render obvious wherein the first difference between the first concentration and the second concentration is 2 to 10 times the second concentration. Specifically, Kim discloses a second semiconductor layer (the semiconductor layer of switching transistor), having zero fluorine concentration (so the second concentration amount is zero fluorine). Therefore, multiplying zero by any number still is zero and thus cannot read on the difference is 2 to 10 times the second concentration. As a result, the combination of the features of Claims 1 and 2 is considered to be allowable.
Regarding Claim 4, the prior art does not teach or render obvious wherein the third concentration is 2 to 10 times the fourth concentration. Specifically, Jeong discloses a barrier layer (the barrier layer adjacent switching transistor), having zero fluorine concentration (so the fourth concentration amount is zero fluorine). Therefore, multiplying zero by any number still is zero and thus cannot read on the difference is 2 to 10 times the second concentration. As a result, the combination of the features of Claims 1 and 4 is considered to be allowable.
Claim 5 incorporates all of the limitations of allowable Claim 4. Therefore, it is also allowable.
Regarding Claim 8, the prior art does not teach or render obvious further comprising a driving voltage line, a common voltage line, a data line, a scan line, a previous scan line, a bypass control line, an initialization voltage line, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor that are positioned on the substrate, wherein the first transistor includes a first electrode electrically connected to a second electrode of the fifth transistor and a second electrode electrically connected to a first electrode of the third transistor, and is constructed and arranged to control a driving current by application of a data voltage; the second transistor includes a first electrode electrically connected to the data line and a second electrode electrically connected to the first electrode of the first transistor, and is constructed and arranged to turn on according to a scan signal of the scan line; the third transistor includes a first electrode electrically connected to the second electrode of the first transistor and a second electrode electrically connected to a gate electrode of the first transistor, and is constructed and arranged to turn on according to the scan signal of the scan line; the fourth transistor includes a first electrode electrically connected to the initialization voltage line and a second electrode electrically connected to a second electrode of the third transistor, and is constructed and arranged to turn on according to a previous scan signal received through the previous scan line; the fifth transistor includes a first electrode electrically connected to the driving voltage line and a second electrode electrically connected to the first electrode of the first transistor, and is constructed and arranged to turn on by an emission signal of an emission control line; the sixth transistor includes a first electrode electrically connected to the second electrode of the first transistor and a second electrode electrically connected to an anode of the light emitting diode, and is constructed and arranged to turn on by the emission signal of the emission control line; the seventh transistor includes a first electrode electrically connected to the anode of the light emitting diode and a second electrode electrically connected to the initialization voltage line, and is constructed and arranged to turn on according to a bypass signal of the bypass control line; and the first concentration of fluorine included in the first semiconductor layer of the first transistor is higher than concentrations of fluorine included in a third semiconductor layer of the third transistor, a fourth semiconductor layer of the fourth transistor, a fifth semiconductor layer of the fifth transistor, a sixth semiconductor layer of the sixth transistor, and a seventh semiconductor layer of the seventh transistor. Therefore, the combination of Claims 1 and 8 is allowable.
Response to Arguments
In the amendments and remarks filed 4/24/2026, the Applicant states (page 11) that “Based on the agreement reached between Applicants and the Examiner during the Interview conducted on March 25, 2026, it is Applicants’ understanding that the rejections would be withdrawn in view of the above amendments.”
The amendments to Claim 1 has necessitated an updated rejection of Claim 1 over Kim and Lee, as discussed supra. In addition, Claim 3 is now rejected over Kim, Lee, and Jeong. Furthermore, Claim 7 is now rejected over Kim, Lee, and Miyairi.
Independent Claim 1 is rejected for at least the reasons stated supra. Dependent Claims 3, and 6-7 are rejected for at least the reasons stated supra.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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