DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 9-11, 16, 18-23, 25, and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen(USPGPUB DOCUMENT: 2018/0342438, hereinafter Chen) in view of Watts (USPGPUB DOCUMENT: 2021/0313286, hereinafter Watts) and Chen (USPGPUB DOCUMENT: 2023/0268318, hereinafter Chen-318).
Re claim 1 Chen discloses in Fig 2a/2b/2c, rotated 180 degrees, a semiconductor package, comprising: a submount(130) having a first surface(top/bottom) and a second surface(top/bottom) opposing the first surface(top/bottom); at least one semiconductor die(120) attached to the second surface(top/bottom) of submount(130); an insulating portion(150)[0038] on the second surface(top/bottom) of the submount(130) and on the at least one semiconductor die(120), the insulating portion(150)[0038] forming a first external surface(surface formed from 130/150) of the semiconductor package; at least one through-mold terminal(213/217/215) extending from the first external surface(surface formed from 130/150) through the insulating portion(150)[0038] to at least one of the semiconductor die(120) or the submount(130).
Chen does not disclose through-mold via; and wherein the at least one through-mold via is electrically coupled to at least one of the semiconductor die or the submount.
Watts discloses in Fig 2a, rotated 180 degrees, through-mold via(left/middle/right 290)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Watts to the teachings of Chen in order to increase the output power and current handling capabilities [0005, Watts].
Chen and Watts does not disclose and wherein the at least one through-mold via is electrically coupled to at least one of the semiconductor die or the submount.
Chen-318 disclose wherein the at least one through-mold via(left/right 132) is electrically coupled[0039] to at least one of the semiconductor die(420) or the submount(110).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Chen-318 to the teachings of Chen in order to have package and die strength [0001, Chen-318].
Re claim 2 Chen and Watts and Chen-318 disclose the semiconductor package of claim 1, wherein the first surface(top/bottom) of the submount(130) is a second external surface(surface formed from 130/150) of the semiconductor package, the second external surface(surface formed from 130/150) opposing the first external surface(surface formed from 130/150).
Re claim 3 Chen and Watts and Chen-318 disclose the semiconductor package of claim 2, wherein the at least one through-mold via(213/217/215) comprises a plurality of through-mold via(213/217/215)s, wherein the semiconductor package further comprises a plurality of interconnect structures, each interconnect structure coupled to at least one of the plurality of through-mold via(213/217/215)s, each interconnect structure on the first external surface(surface formed from 130/150) of the semiconductor package.
Re claim 4 Chen and Watts and Chen-318 disclose the semiconductor package of claim 3, wherein all interconnect structures for the semiconductor package are on the first external surface(surface formed from 130/150) to provide a flip-chip configuration for the semiconductor package.
Re claim 5 Chen and Watts and Chen-318 disclose the semiconductor package of claim 3, wherein each interconnect structure comprises a solder pad or a solder bump[0060 of Watts].
Re claim 6 Chen and Watts and Chen-318 disclose the semiconductor package of claim 1, wherein the at least one semiconductor die(120) comprises a first die surface(top/bottom) and a second die surface(top/bottom) opposing the first die surface(top/bottom), the first die surface(top/bottom) having a first die contact and the second die surface(top/bottom) having a second die contact.
Re claim 7 Chen and Watts and Chen-318 disclose the semiconductor package of claim 6, wherein the first die contact is coupled to the submount(130).
Re claim 9 Chen and Watts and Chen-318 disclose the semiconductor package of claim 6, wherein the at least one through-mold via(213/217/215) is coupled to the second die contact.
Re claim 10 Chen and Watts and Chen-318 disclose the semiconductor package of claim 6, wherein the at least one through- mold via(213/217/215) comprises:a first through-mold via(213/217/215) extending from the first external surface(surface formed from 130/150) through the insulating portion(150)[0038] to the second die contact on the at least one semiconductor die(120); anda second through-mold via(213/217/215) extending from the first external surface(surface formed from 130/150) through the insulating portion(150)[0038] to the submount(130), the second through-mold via(213/217/215) electrically coupled to the first die contact through the submount(130).
Re claim 11 Chen and Watts and Chen-318 disclose the semiconductor package of claim 10, wherein the at least one semiconductor die(120) comprises a third die contact on the second die surface;wherein the at least one through-mold via(213/217/215) comprises: a third through-mold via(213/217/215) extending from the first external surface(surface formed from 130/150) through the insulating portion(150)[0038] to the third die contact.
Re claim 16 Chen and Watts and Chen-318 disclose the semiconductor package of claim 1, wherein the submount(130) comprises a plurality of metal layers[0063 of Watts] with an isolating layer between the plurality of metal layers[0063 of Watts].
Re claim 18 Chen and Watts and Chen-318 disclose the semiconductor package of claim 1, wherein the submount(130) forms a thermally conductive cooling layer[0009 of Watts] for the semiconductor package.
Re claim 19 Chen and Watts and Chen-318 disclose the semiconductor package of claim 1, wherein the semiconductor package comprises a plurality of semiconductor die(120), wherein the semiconductor package further comprises a redistribution layer[0064 of Watts] coupling the at least one through-mold via(213/217/215) to the plurality of semiconductor die(120).
Re claim 20 Chen and Watts and Chen-318 disclose the semiconductor package of claim 1, wherein the semiconductor package does not include any wire bonds to the at least one semiconductor die(120).
Re claim 21 Chen and Watts and Chen-318 disclose the semiconductor package of claim 1, wherein the insulating portion(150)[0038] covers the at least one semiconductor die(120).
Re claim 22 Chen and Watts and Chen-318 disclose the semiconductor package of claim 1, wherein the insulating portion(150)[0038] comprises an epoxy mold compound[0036].
Re claim 23 Chen and Watts and Chen-318 disclose the semiconductor package of claim 1, wherein the at least one semiconductor die(120) comprises a wide band gap semiconductor, wherein the wide band gap semiconductor is silicon carbide or a Group III-nitride[0024 of Watts].
Re claim 25 Chen and Watts and Chen-318 disclose the semiconductor package of claim 1, wherein the at least one semiconductor die(120) comprises a silicon carbide-based MOSFET, a silicon carbide-based Schottky diode[0066 of Watts], or a Group III-nitride[0024 of Watts] based high electron mobility transistor.
Re claim 28 Chen discloses in Fig 2a/2b/2c, rotated 180 degrees, a semiconductor package, comprising: a submount(130) having a first surface(top/bottom) and a second surface(top/bottom), the second surface(top/bottom) opposing the first surface(top/bottom); at least one semiconductor die(120), the at least one semiconductor die(120) comprising a first die surface(top/bottom) and a second die surface(top/bottom) having a source contact[0061] and a gate contact[0064], the drain contact being coupled to the first surface(top/bottom) of the submount(130); an insulating portion(150)[0038] on the submount(130) and on the semiconductor die(120), the insulating portion(150)[0038] forming a first external surface(surface formed from 130/150) of the semiconductor package; a first through-mold terminal(213/217/215) extending from the first external surface(surface formed from 130/150) through the insulating portion(150)[0038] to the gate contact[0064 of Chen]; a second through-mold terminal(213/217/215) extending from the first external surface(surface formed from 130/150) through the insulating portion(150)[0038]; and a third through-mold terminal(213/217/215) extending from the first external surface(surface formed from 130/150) through the insulating portion(150)[0038] to the submount(130),
Chen does not disclose the at least one semiconductor die(120) comprising a first die surface(top/bottom) having a drain contact; a second through-mold via(213/217/215) extending from the first external surface(surface formed from 130/150) through the insulating portion(150)[0038] to the source contact; wherein the drain contact is electrically coupled to the third through-mold via(213/217/215) with the submount(130); wherein the first through-mold via is electrically coupled to the gate contact; wherein the second through-mold via is electrically coupled to the source contact;
Watts discloses in Fig 2a, rotated 180 degrees, the at least one semiconductor die(210) comprising a first die surface(top/bottom) having a source contact(253 of Watts); a second through-mold via(left/middle/right 290)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Watts to the teachings of Chen in order to increase the output power and current handling capabilities [0005, Watts]. In doing so, a second through-mold via(left/middle/right 290 of Watts) extending from the first external surface(surface formed from 130/150 of Chen) through the insulating portion(150)[0038 of Chen] to the drain contact(253 of Watts); wherein the drain contact(253 of Watts) is coupled to the third through-mold via(213/217/215 of Chen) with the submount(130 of Chen).
Chen and Watts does not disclose wherein the drain contact is electrically coupled to the third through-mold via(213/217/215) with the submount(130); wherein the first through-mold via is electrically coupled to the gate contact; wherein the second through-mold via is electrically coupled to the source contact;
Chen-318 disclose wherein the first through-mold via(left/right 132) is electrically coupled[0039]; wherein the second through-mold via(left/right 132) is electrically coupled[0039];
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Chen-318 to the teachings of Chen in order to have package and die strength [0001, Chen-318]. In doing so, wherein the drain contact is electrically coupled to the third through-mold via(213/217/215) with the submount(130); wherein the first through-mold via(left/right 132) is electrically coupled[0039] to the gate contact [0064 of Chen]; wherein the second through-mold via(left/right 132) is electrically coupled[0039] to the source contact(253 of Watts);
Response to Arguments
Applicant’s arguments with respect to claim 1-7, 9-11, 16, 18-23, 25, and 28 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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