Prosecution Insights
Last updated: October 01, 2026
Application No. 18/336,382

GALLIUM NITRIDE DEVICE WITH ARTIFICIAL FIELD PLATES

Non-Final OA §103
Filed
Jun 16, 2023
Examiner
NEWTON, VALERIE N
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
3 (Non-Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
776 granted / 922 resolved
+16.2% vs TC avg
Moderate +6% lift
Without
With
+5.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
33 currently pending
Career history
958
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
58.6%
+18.6% vs TC avg
§102
28.7%
-11.3% vs TC avg
§112
6.5%
-33.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 922 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10461161 (Kinzer) in view of US 20240339507 (Siemieniec et al). Concerning claim 1, Kinzer discloses a semiconductor device (Fig. 2), comprising: a gate structure (230) and first (222/247) and second (221/245) source/drain (S/D) regions on a substrate (205) (Fig. 2); a gate contact structure (223) electrically connected to the gate structure (col. 7 lines 4-6); first (227) and second (225) S/D contact structures electrically connected to the first and second S/D regions (col. 6 lines 58-65), respectively; and . . . artificial field plates (243a-243t) disposed between the gate contact structure and the first S/D contact structure, wherein . . . artificial field plates . . . and electrically separated from the first and second S/D contact structures (col. 5 lines 34-43). Kinzer does not disclose a plurality of columns of identical artificial field plates . . . each column of the plurality of columns of identical artificial plates comprises a plurality of identical artificial filed plates vertically aligned in a plan view. Siemieniec discloses a semiconductor power device configuration (Fig. 3A and 3B) in which a plurality of columns of identical artificial field plates (21) . . . each column of the plurality of columns of identical artificial plates comprises a plurality of identical artificial filed plates vertically aligned in a plan view (Figs. 3A and 3B). Siemieniec discloses that such configuration enables a further reduction of the RDS (on)×Area while keeping the FOMs at least constant or improving them ([0020]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of the field plates of Kinzer such that they are formed a plurality of columns of identical artificial field plates . . . each column of the plurality of columns of identical artificial plates comprises a plurality of identical artificial filed plates vertically aligned in a plan view as disclosed by Siemieniec in order to reduce the RDS (on)×Area while keeping the FOMs at least constant or improving them. Considering claim 2, Kinzer in view of Siemieniec discloses wherein the first S/D region is a drain region and the first S/D contact structure is electrically connected to the drain region (Kinzer col. 6 lines 58-65). Continuing to claim 3, Kinzer in view of Siemieniec discloses wherein a first distance between the first S/D contact structure and the gate contact structure is greater than a second distance between the second S/D contact structure and the gate contact structure (Kinzer Fig. 2). Referring to claim 4, Kinzer in view of Siemieniec discloses wherein a distance between the first S/D contact structure and the plurality of identical artificial field plates ranges from about 1 µm to about 18 µm (Kinzer col. 6 lines 16-30 note that it is disclosed that the gate-drain separation can be reduced below 18 microns and that the artificial field plates are formed within the region between the drain and gate region and therefore the distance between the one or mor artificial plate falls within the claimed range). Regarding claim 5, Kinzer in view of Siemieniec discloses wherein a size of each of the plurality of identical artificial field plates ranges from about 0.5 µm2 to about 10 µm2 (Kinzer col. 5 lines 15-33 and col. 8 lines 1-24). PNG media_image1.png 167 637 media_image1.png Greyscale (It is noted that feature 240 is square-shaped (examiner is interpreting that the square has 4 equal sides) and that the width (and height based on shape) of feature 240 is disclosed to be from 1 to 5 microns (with the examiner relying on the middle of this range 3 microns for examination purposes). It is also noted that the width of features 243a-243t (which have the same height as feature 240) are disclosed to be from 2 to 4 microns (with the examiner relying on the middle of this range 3 microns for examination purposes). Therefore the size of the one or more artificial plates would be 9 sq microns (µm2) which falls within the claimed range). Pertaining to claim 6, Kinzer in view of Siemieniec discloses wherein a number of the plurality of identical artificial field plates ranges from about 1 to about 1000 (Kinzer col. 8 lines 1-24, it is noted that the number of artificial field plates goes from “a” to “t” and therefore there are at least 20 field plates in the disclosed invention). As to claim 7, Kinzer in view of Siemieniec discloses further comprising an additional field plate (Kinzer 240) disposed between the gate contact structure and the first S/D contact structure and electrically connected to the second S/D contact structure (Kinzer Fig. 2 ), wherein the plurality of identical artificial field plates are disposed between the additional field plate and the first S/D contact structure (Kinzer Fig. 2 and Siemieniec Fig. 3B). Concerning claim 8, Kinzer in view of Siemieniec discloses wherein the plurality of identical artificial field plates comprise a conductive material in the gate structure, a conductive material in the gate contact structure, a conductive material in the first and second S/D contact structures, or a conductive material in an interconnect structure of the semiconductor device (Kinzer col. 7 lines 15-25). Claim(s) 9-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10461161 (Kinzer) in view of US 20080296618 (Suh et al). Considering claim 9, Kinzer discloses a semiconductor device (Fig. 2), comprising: a first gallium nitride (GaN) layer (210) on a substrate (205) (col. 6 lines 30-32); an aluminum gallium nitride (AlGaN) (215) layer on the first GaN layer (col. 6 lines 32-33); a second GaN layer (230) on the AlGaN layer (col. 7 lines 4-10, it is noted that this layer is disclosed as being a compound semiconductor including gallium and nitrogen (GaN) which the examiner is relying on for examination purposes); a gate contact structure (223) in . . . contact with the second GaN layer; first (227) and second (225) source/drain (S/D) contact structures. . . contact with the . . . AlGaN layer (Fig. 2, note that the source and drain contact structures are in contact with the source drain regions that are formed in the AlGaN layer), wherein the first and second S/D contact structures are disposed at opposite sides of the gate contact structure (Fig. 2); and one or more artificial field plates (243a-243t) disposed above the AlGaN layer and between the gate contact structure and the first S/D contact structure (Fig. 2), wherein the one or more artificial field plates are separated from the first and second S/D contact structures (col. 5 lines 34-43). Kinzer does not disclose that the gate contact structure is over and in direct physical contact with a top surface of the second Gan layer and first and second source/drain (S/D) contact structures over and in direct physical contact with a top surface of the AlGaN layer. However, Suh discloses a semiconductor power device configuration (Fig. 13) in which a first gallium nitride (GaN) layer (1304) ([0068]); an aluminum gallium nitride (AlGaN) (1306) layer on the first GaN layer ([0068]); a second GaN layer (1308) on the AlGaN layer ([0068]) the gate contact structure is over and in direct physical contact with a top surface of the second GaN layer and first and second source/drain (S/D) contact structures (1318 and 1320) are over and in direct physical contact with a top surface of the AlGaN layer (Fig. 13). Suh discloses that such configuration is beneficial for reducing an electron population under the gate (Abstract). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of the gate contact structure, first GaN layer, AlGaN layer, and second GaN layer such the gate contact structure is over and in direct physical contact with a top surface of the second Gan layer and first and second source/drain (S/D) contact structures over and in direct physical contact with a top surface of the AlGaN layer to arrive at the configuration of Suh and reduce electron population under the gate in the device. Continuing to claim 10, Kinzer in view of Suh discloses wherein the first S/D contact structure is a drain contact structure (Kinzer col. 6 lines 58-65) and the first and second GaN layers comprise different types of dopants (Kinzer col. 6 lines 32-33 and col. 7 lines 4-10, it is noted that the first GaN is not disclosed as being doped and the second GaN (for examination purposes) is disclosed as being doped with N or P dopants therefore these layers are disclosed as comprising different type of dopants (one with P and the other with none)). Referring to claim 11, Kinzer in view of Suh discloses wherein a first distance between the first S/D contact structure and the gate contact structure is greater than a second distance between the second S/D contact structure and the gate contact structure (Kinzer Fig. 2). Regarding claim 12, Kinzer in view of Suh discloses wherein a distance between the first S/D contact structure and the one or more artificial field plates ranges from about 1 µm to about 18 µm (Kinzer col. 6 lines 16-30 note that it is disclosed that the gate-drain separation can be reduced below 18 microns and that the artificial field plates are formed within the region between the drain and gate region and therefore the distance between the one or mor artificial plate falls within the claimed range). Pertaining to claim 13, Kinzer in view of Suh discloses wherein a size of each of the one or more artificial field plates ranges from about 0.5 µm2 to about 10 µm2 (Kinzer col. 5 lines 15-33 and col. 8 lines 1-24). PNG media_image1.png 167 637 media_image1.png Greyscale (It is noted that feature 240 is square-shaped (examiner is interpreting that the square has 4 equal sides) and that the width (and height based on shape) of feature 240 is disclosed to be from 1 to 5 microns (with the examiner relying on the middle of this range 3 microns for examination purposes). It is also noted that the width of features 243a-243t (which have the same height as feature 240) are disclosed to be from 2 to 4 microns (with the examiner relying on the middle of this range 3 microns for examination purposes). Therefore the size of the one or more artificial plates would be 9 sq microns (µm2) which falls within the claimed range) As to claim 14, Kinzer in view of Suh discloses wherein a number of the one or more artificial field plates ranges from about 1 to about 1000 (Kinzer col. 8 lines 1-24, it is noted that the number of artificial field plates goes from “a” to “t” and therefore there are at least 20 field plates in the disclosed invention). Concerning claim 15, Kinzer in view of Suh discloses further comprising an additional field plate (240) disposed between the gate contact structure and the first S/D contact structure and electrically connected to the second S/D contact structure (Kinzer Fig. 2), wherein the one or more artificial field plates are disposed between the additional field plate and the first S/D contact structure (Kinzer Fig. 2). Considering claim 16, Kinzer in view of Suh discloses wherein the one or more artificial field plates comprise GaN, titanium nitride, titanium, or copper (Kinzer col. 6 lines 4-15, note that the structure 235 which includes the artificial filed plates is disclosed as comprising GaN). Continuing to claim 17, Kinzer discloses a method (Fig. 2), comprising: forming a first gallium nitride (GaN) layer (210) on a substrate (205) (col. 6 lines 30-32); forming an aluminum gallium nitride (AlGaN) (215) layer on the first GaN layer (col. 6 lines 32-33); forming a second GaN layer (230) on the AlGaN layer (col. 7 lines 4-10, it is noted that this layer is disclosed as being a compound semiconductor including gallium and nitrogen (GaN) which the examiner is relying on for examination purposes); forming first (227) and second (225) source/drain (S/D) contact structures. . . in . . .contact with. . . the AlGaN layer (Fig. 2, note that the source and drain contact structures are in contact with the source drain regions that are formed in the AlGaN layer), wherein the first and second S/D contact structures are disposed at opposite sides of the second GaN layer (Fig. 2), forming a gate contact structure . . .(223) in . . . contact with . . .the second GaN layer (Fig. 2);and forming one or more artificial field plates (243a-243t) . . . between the gate contact structure and the first S/D contact structure (Fig. 2), wherein the one or more artificial field plates are separated from the first and second S/D contact structures (col. 5 lines 34-43). Kinzer does not disclose the gate contact structure is over and in direct physical contact with a top surface of the second Gan layer and first and second source/drain (S/D) contact structures over and in direct physical contact with a top surface of the AlGaN layer, forming a nitride layer on top surfaces of the first and second S/D contact structures; wherein a top surface of the gate contact structure extends above the nitride layer ,and forming one or more artificial field plates on the nitride layer and between the gate contact. However, Suh discloses a semiconductor power device configuration (Fig. 13) in which a first gallium nitride (GaN) layer (1304) ([0068]); an aluminum gallium nitride (AlGaN) (1306) layer on the first GaN layer ([0068]); a second GaN layer (1308) on the AlGaN layer ([0068]), and a nitride layer (1312) that is formed over a top surface of the source and drain contact structures and a portion of the gate (1310) is formed above a top portion of the nitride layer (Fig. 13, note that the nitride layer has a top surface that is formed over the source and drain contact structures and that top surface is lower than a top surface of the gate). The gate contact structure is over and in direct physical contact with a top surface of the second GaN layer and first and second source/drain (S/D) contact structures (1318 and 1320) are over and in direct physical contact with a top surface of the AlGaN layer (Fig. 13). Suh discloses that such configuration is beneficial for reducing an electron population under the gate (Abstract). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of the gate contact structure, first GaN layer, AlGaN layer, and second GaN layer such the gate contact structure is over and in direct physical contact with a top surface of the second Gan layer and first and second source/drain (S/D) contact structures over and in direct physical contact with a top surface of the AlGaN layer with one or more artificial field plates on the nitride layer and between the gate contact to reduce electron population under the gate in the device. Referring to claim 18, Kinzer in view of Suh discloses wherein forming the first and second S/D contact structures comprises: forming the first S/D contact structure having a first distance from the gate contact structure; and forming the second S/D contact structure having a second distance from the gate contact structure, wherein the first distance is greater than the second distance (Kinzer Fig. 2). Regarding claim 19, Kinzer in view of Suh discloses wherein forming the one or more artificial field plates comprises forming the one or more artificial field plates at a distance ranging from about 1 µm to about 18 µm from the first S/D contact structure. (Kinzer col. 6 lines 16-30 note that it is disclosed that the gate-drain separation can be reduced below 18 microns and that the artificial field plates are formed within the region between the drain and gate region and therefore the distance between the one or mor artificial plate falls within the claimed range) Pertaining to claim 20. Kinzer in view of Suh discloses wherein forming the one or more artificial field pates comprises forming the one or more artificial field plates having a size ranging from about 0.5 µm2 to about 10 µm2 (Kinzer col. 5 lines 15-33 and col. 8 lines 1-24). PNG media_image1.png 167 637 media_image1.png Greyscale (It is noted that feature 240 is square-shaped (examiner is interpreting that the square has 4 equal sides) and that the width (and height based on shape) of feature 240 is disclosed to be from 1 to 5 microns (with the examiner relying on the middle of this range 3 microns for examination purposes). It is also noted that the width of features 243a-243t (which have the same height as feature 240) are disclosed to be from 2 to 4 microns (with the examiner relying on the middle of this range 3 microns for examination purposes). Therefore the size of the one or more artificial plates would be 9 sq microns (µm2) which falls within the claimed range). Response to Arguments Applicant’s arguments with respect to claim(s) 1, 9, and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VALERIE N NEWTON/Examiner, Art Unit 2897 09/04/26/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Show 5 earlier events
Dec 30, 2025
Response Filed
Apr 29, 2026
Final Rejection mailed — §103
May 29, 2026
Interview Requested
Jun 04, 2026
Examiner Interview Summary
Jun 04, 2026
Applicant Interview (Telephonic)
Jul 01, 2026
Request for Continued Examination
Jul 07, 2026
Response after Non-Final Action
Sep 14, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751008
3D SYNAPSE DEVICE STACK, 3D STACKABLE SYNAPSE ARRAY USING THE 3D SYNAPSE DEVICE STACKS AND METHOD OF FABRICATING THE STACK
4y 1m to grant Granted Sep 29, 2026
Patent 12735313
MEMS DIE AND MEMS-BASED VIBRATION SENSOR
4y 1m to grant Granted Sep 15, 2026
Patent 12740128
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
2y 3m to grant Granted Sep 15, 2026
Patent 12727223
FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD
2y 1m to grant Granted Sep 01, 2026
Patent 12717075
DISPLAY DEVICE
3y 10m to grant Granted Aug 25, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
90%
With Interview (+5.9%)
2y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 922 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month