DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There is no support in the original specification for the claim limitations of “a contact length between the buffer layer and the package layer is equal to a length of the second surface of the buffer layer”, as recited in claim 1. The buffer layer formed below the dummy die how can the buffer and the package layer has a contact length is equal to a length of the second surface of the buffer layer?
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-6, 15-17, 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2010/0140779, as recited in previous office action).
As for claim 1, Lin et al. disclose in Figs. 3a-3f (upside down) and the related text a package structure, comprising:
a package component 164;
a dummy die (left 152) disposed over the package component;
a device die (right 152) adjacent to the dummy die;
a buffer layer 158 formed below the dummy die (fig. 3f), wherein the buffer layer 158 has a first (lower) surface and an opposite second (upper) surface, the first (lower) surface is in direct contact with a bottom (upper) surface of the dummy die and the second (lower) surface is separated from the package component (fig. 3f); and
a package layer 156/160/162 surrounding the device die, the dummy die and the buffer layer (Fig. 3f), wherein the second surface of the buffer layer 158 is covered by (a portion of) the package layer 160/162 (Fig. 3f), and a contact length between the buffer layer 158 and the package layer 156/160/162 is equal to a length of (a portion of) the second surface of the buffer layer 158 (Fig. 3f).
As for claim 3, Lin et al. disclose the package structure as claimed in claim 1, further comprising: a through via 150 formed adjacent to the device die, wherein a height of the through via is greater than a height of the dummy die (fig. 3f).
As for claim 4, Lin et al. disclose the package structure as claimed in claim 1, wherein the second (upper) surface of the buffer layer 158 is in direct contact with the package layer 156/160/162.
As for claim 5, Lin et al. disclose the package structure as claimed in claim 1, wherein a height of (half portion of) the dummy die is smaller than a height of (an entire of) the device die.
As for claim 6, Lin et al. disclose the package structure as claimed in claim 1, wherein the package component 164 is electrically connected to the device die (fig. 3f).
As for claim 15, Lin et al. disclose in Fig. 6 and the related text a package structure, comprising:
a first package component 444/446/448;
a first device die (left 452) formed on a top surface of the first package component (fig. 6);
a first dummy die (right 452) formed on the top surface of the first package component (fig. 6); and
a second device die 432 formed below a bottom surface of the first package component (Fig. 6), wherein the second device die 432 is directly below the first dummy die (fig. 6), and a height of the first dummy die (right 452) is different from a height of the second device die 432 (Fig. 6), and the second device die 432 is surrounded by a package layer 436
a second dummy die 433 adjacent to the second device die 432, and directly below the first device die (left 452).
As for claim 16, Lin et al. disclose the package structure as claimed in claim 15, wherein the second device die 432 comprises a conductive pad 434, and the conductive pad 434 is electrically connected to the first package component (fig. 6).
As for claim 17, Lin et al. disclose the package structure as claimed in claim 15, further comprising: a buffer layer 454 formed on the first dummy die, and the buffer layer 454 is between the first package component 444/446/448 and the first dummy die (right 452, fig. 6).
As for claim 19, Lin et al. disclose the package structure as claimed in claim 15, further comprising: a second package component 460/462 formed over the first device die and the first dummy die (fig. 6), wherein the second package component 460/462 is electrically connected to the first package component 444/446/448 (fig. 6).
As for claim 20, Lin et al. disclose the package structure as claimed in claim 15, further comprising: a third package component 412/414 formed below the second device die 432, wherein the third package component 412/414 is electrically connected to the first package component 444/446/448 (fig. 6).
Claim(s) 7-10 and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ray et al. (US 2015/0235988).
As for claim 7, Ray et al. disclose in Fig. 7C and the related text a package structure, comprising:
a first package component 760/763;
a second package component 700 formed over the first package component (fig. 7C);
a first memory die 706 between the first package component and the second package component (fig. 7C), wherein the first memory die 706 comprises a first substrate; and
a first dummy die 710 adjacent to the first memory die 706 (fig. 7C), wherein a first distance from a bottom (upper) surface of the first dummy die 710 to the first package component is larger than a second distance from a bottom (upper) surface of the first substrate of the first memory die 706 to the first package component, a top (lower) surface of the first dummy die 710 is substantially aligned with a top surface of the first memory die 706, and the first dummy die 710 is embedded in a package layer 720, and (a portion of) the bottom (upper) surface of the first dummy die 710 is covered by the package layer 720 (Fig. 7C) , and a contact length between the first dummy die 710 and the package layer 720 is equal to a length of (a portion of) the first dummy die 710 (Fig. 7C).
As for claim 8, Ray et al. disclose the package structure as claimed in claim 7, wherein the first memory die 706 further comprises a conductive pad 716 (fig. 7C), and the conductive pad is closer to the first package component than the first substrate (fig. 7C).
As for claim 9, Ray et al. disclose the package structure as claimed in claim 8, wherein the conductive pad 716 is electrically connected to the first package component (fig. 7C).
As for claim 10, Ray et al. disclose the package structure as claimed in claim 7, further comprising: a buffer layer (layer between 710 and 701) formed on the bottom (upper) surface of the first dummy die 710, and the buffer layer is in direct contact with the package layer (fig. 7C).
As for claim 13, Ray et al. disclose the package structure as claimed in claim 7, wherein the first package component 760/763 is electrically connected to the second package component 700 (fig. 7C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ray et al. in view of Nair et al. (US 2016/0276325).
As for claims 11-12, Ray et al. disclose the package structure as claimed in claim 7, except a through via formed adjacent to the first memory die, wherein a top surface of the through via is substantially aligned with the top surface of the first memory die; and a third distance between a bottom surface of the through via and the first package component is smaller than the second distance.
Nair et al. teach in Fig. 1B and the related text a through via 120 formed adjacent to the first memory die 120A, wherein a top (lower) surface of the through via 115 is substantially aligned with the top (lower) surface of the first memory die 120A (Fig. 1B); and wherein a third distance between a bottom surface of the through via 115 and the first package component 152/155 is smaller than the second distance (fig. 1B).
Ray et al. and Nair et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ray et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Ray et al. to include the limitations as taught by Nair, in order to improve interconnections.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ray et al. in view of Shin et al. (US 2017/0084579, as disclosed in previous office action)
As for claim 14, Ray et al. disclose the package structure as claimed in claim 7, except a third package component formed below the first package component.
Shin et al. teach in Fig. 1 and the related text a third package component 200 formed below the first package component 300.
Ray et al. and Shin et al. are analogous art because they both are directed the packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ray et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Ray et al. to include the limitations as taught by Shin et al. in order to increase density of the device.
Claim(s) 2 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. in view of Chung et al. (US 2016/0260695).
As for claims 2 and 18, Lin et al. disclose the package structure as claimed in claim 15, except the first device die comprises a memory die, and the memory die comprises a Static Random Access Memory (SRAM) die or a Dynamic Random Access Memory (DRAM) die.
Chung et al. teach a device die comprises a memory die, and the memory die comprises a Static Random Access Memory (SRAM) die or a Dynamic Random Access Memory (DRAM) die [0055].
Lin et al. and Chung et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lin et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Lin et al. to include the second device die is surrounded by a package layer as taught by Chung et al. in order to provide function to the device.
Response to Arguments
Applicant's response filed on 03/20/2026 is acknowledged and is answered as follows.
Applicant’s arguments, with respect to claim 1 rejection that Lin et al. do not disclose “a contact length between the buffer layer and the package layer is equal to a length of the second surface of the buffer layer ” have been fully considered but they are not persuasive in view of the following reasons:
Fig. 3f of Lin et al. teach a contact length between the buffer layer 158 and the package layer 156/160/162 is equal to a length of (a portion of) the second surface of the buffer layer 158.
Applicant’s arguments, with respect to claim 7 rejection that Ray et al. do not disclose “a contact length between the first dummy die and the package layer is equal to a length of the first dummy die” have been fully considered but they are not persuasive in view of the following reasons:
Ray et al. teach in Fig. 7A-7C and the related text a contact length between the first dummy die 710 and the package layer 720 is equal to a length of (/a portion of) the first dummy die 710.
Applicant’s arguments with respect to claim(s) 15-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In view of the foregoing reasons, the Examiner believes that all Applicant’s arguments and remarks are addressed. The Examiner has determined that the previous Office Action is still proper based on the above responses. Therefore, the rejections are sustained and maintained.
Conclusion
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/TRANG Q TRAN/ Primary Examiner, Art Unit 2811
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