DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/12/2023 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-7, 11-12, 15 and 17-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lilak (US 2020/0098756).
Regarding claim 1, Lilak discloses, in at least figures 1A-1B, 7-12, and related text, a semiconductor structure, comprising:
one or more first nanostructures (132b, lower 138, [40], [41], [64]) extending along a first lateral direction (Y direction, figures);
one or more second nanostructures (132a, upper 138, [40], [41], [64]) extending along the first lateral direction (Y direction, figures) and vertically disposed above the one or more first nanostructures (132b, lower 138, [40], [41], [64]); and
a gate structure (140 (142/144/145), [37]) extending along a second lateral direction (X direction, figures) perpendicular to the first lateral direction (Y direction, figures), and disposed around each of the one or more first nanostructures (132b, lower 138, [40], [41], [64]) and each of the one or more second nanostructures (132a, upper 138, [40], [41], [64]),
wherein the gate structure (140 (142/145/144), [37]) comprises: (i) a first metal material (145, [39]), (ii) a ferroelectric material (142, [90]), and (iii) a second metal material (144, [92]).
Regarding claim 3, Lilak discloses the semiconductor structure of claim 1 as described above.
Lilak further discloses, in at least figures 1A-1B, 7-12, and related text, the one or more first nanostructures (132b, lower 138, [40], [41], [64]) and the one or more second nanostructures (132a, upper 138, [40], [41], [64]) each include a semiconductor material ([40], [41], [64]).
Regarding claim 4, Lilak discloses the semiconductor structure of claim 1 as described above.
Lilak further discloses, in at least figures 1A-1B, 7-12, and related text, a first pair of source/drain structures (120b, [81]) in contact with the one or more first nanostructures (132b, lower 138, [40], [41], [64]) along the first lateral direction (Y direction, figures); and
a second pair of source/drain structures (120a, [81]) in contact with the one or more second nanostructures (132a, upper 138, [40], [41], [64]) along the first lateral direction (Y direction, figures).
Regarding claim 5, Lilak discloses the semiconductor structure of claim 4 as described above.
Lilak further discloses, in at least figures 1A-1B, 7-12, and related text, the first pair of source/drain structures (120b, [81]) are vertically spaced from the second pair of source/drain structures (120a, [81]).
Regarding claim 6, Lilak discloses the semiconductor structure of claim 1 as described above.
Lilak further discloses, in at least figures 1A-1B, 7-12, and related text, the first metal material (145, [39]) includes a plurality of first closed-loops surrounding the one or more first nanostructures (132b, lower 138, [40], [41], [64]) and the one or more second nanostructures (132a, upper 138, [40], [41], [64]), respectively.
Regarding claim 7, Lilak discloses the semiconductor structure of claim 6 as described above.
Lilak further discloses, in at least figures 1A-1B, 7-12, and related text, the ferroelectric material (142, [90]) includes a plurality of second closed-loops surrounding the first closed-loops (loops of 145, [39], figures), respectively.
Regarding claim 11, Lilak discloses, in at least figures 4A-4B, 7-12, and related text, a semiconductor structure, comprising:
a plurality of first nanostructures (lower 132, 132b, lower 138, [40], [41], [64], [88]) extending along a first lateral direction (Y direction, figures);
a plurality of second nanostructures (upper 132, 132a, upper 138, [40], [41], [64], [88]) extending along the first lateral direction (Y direction, figures) and vertically disposed above the plurality of first nanostructures (lower 132, 132b, lower 138, [40], [41], [64], [88]);
a first gate structure (lower 140 (142/144/145), [37]) extending along a second lateral direction (X direction, figures) perpendicular to the first lateral direction (Y direction, figures), and disposed around each of the plurality of first nanostructures (lower 132, 132b, lower 138, [40], [41], [64], [88]); and
a second gate structure (upper 140 (142/144/145), [37]) extending along the second lateral direction (X direction, figures) and disposed around each of the plurality of second nanostructures (upper 132, 132a, upper 138, [40], [41], [64], [88]),
wherein the first (lower 140 (142/144/145), [37]) and second (upper 140 (142/144/145), [37]) gate structures each comprise: (i) a first metal material (145, [39]), (ii) a ferroelectric material (142, [90]), and (iii) a second metal material (144, [92]).
Regarding claim 12, Lilak discloses the semiconductor structure of claim 11 as described above.
Lilak further discloses, in at least figures 4A-4B, 7-12, and related text, the first (lower 140 (142/144/145), [37]) and second (upper 140 (142/144/145), [37]) gate structures are physically connected to each other.
Regarding claim 15, Lilak discloses the semiconductor structure of claim 11 as described above.
Lilak further discloses, in at least figures 4A-4B, 7-12, and related text, the first nanostructures (lower 132, 132b, lower 138, [40], [41], [64], [88]) and the second nanostructures (upper 132, 132a, upper 138, [40], [41], [64], [88]) each include semiconductor material ([40], [41], [64]).
Regarding claim 17, Lilak discloses the semiconductor structure of claim 11 as described above.
Lilak further discloses, in at least figures 4A-4B, 7-12, and related text, a first pair of source/drain structures (120b, [81]) in contact with the first nanostructures (lower 132, 132b, lower 138, [40], [41], [64], [88]) along the first lateral direction (Y direction, figures); and
a second pair of source/drain structures (120a, [81]) in contact with the second nanostructures (upper 132, 132a, upper 138, [40], [41], [64], [88]) along the first lateral direction (Y direction, figures);
wherein the first pair of source/drain structures (120b, [81]) are vertically spaced from the second pair of source/drain structures (120a, [81]).
Regarding claim 18, Lilak discloses, in at least figures 3A-3B, 7-12, and related text, a method for fabricating semiconductor structures, comprising:
forming a plurality of first nanostructures (lower 132, 132b, lower 138, [40], [41], [64], [88]) vertically spaced from one another and a plurality of second nanostructures (upper 132, 132a, upper 138, [40], [41], [64], [88]) vertically spaced from one another, wherein the plurality of first nanostructures (lower 132, 132b, lower 138, [40], [41], [64], [88]) and the plurality of second nanostructures (upper 132, 132a, upper 138, [40], [41], [64], [88]) each extend along a first lateral direction (Y direction, figures);
exposing a middle portion of each of the plurality of first nanostructures (lower 132, 132b, lower 138, [40], [41], [64], [88]) and the plurality of second nanostructures (upper 132, 132a, upper 138, [40], [41], [64], [88]) ([85]-[88]); and
wrapping the exposed middle portion of each of the plurality of first nanostructures (lower 132, 132b, lower 138, [40], [41], [64], [88]) and the plurality of second nanostructures (upper 132, 132a, upper 138, [40], [41], [64], [88]) ([85]-[88]) with a gate structure (140 (142/144/145), [37], [89]),
wherein the gate structure (140 (142/144/145), [37], [89]) comprises: (i) a first metal material (145, [39]), (ii) a ferroelectric material (142, [90]), and (iii) a second metal material (144, [92]).
Regarding claim 19, Lilak discloses the method of claim 18 as described above.
Lilak further discloses, in at least figures 3A-3B, 7-12, and related text, forming a pair of first source/drain structures (120b, [81]) on opposite ends of the first nanostructures (lower 132, 132b, lower 138, [40], [41], [64], [88]) along the first lateral direction (Y direction, figures) and a pair of second source/drain structures (120a, [81]) on opposite ends of the second nanostructures (upper 132, 132a, upper 138, [40], [41], [64], [88]) ([85]-[88]) along the first lateral direction (Y direction, figures);
wherein the pair of first source/drain structures (120b, [81]) are separated from the pair of second source/drain structures (120a, [81]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 13-14 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lilak (US 2020/0098756) in view of Dewey (US 2020/0105751).
Regarding claim 2, Lilak discloses the semiconductor structure of claim 1 as described above.
Lilak does not explicitly disclose the one or more first nanostructures and the one or more second nanostructures each include a material selected from the group consisting of: indium oxide (In2O3), tin oxide (SnO2), indium gallium zinc oxide (InGaZnO), zinc oxide (ZnO), tin oxide (SnO), and combinations thereof.
Dewey teaches, in at least figure 2a and related text, the device comprising the one or more first nanostructures (205, [27], [29]) and the one or more second nanostructures (202, [27], [29]) each include a material selected from the group consisting of: indium oxide (In2O3) ([29]), tin oxide (SnO2) ([29]), indium gallium zinc oxide (InGaZnO) ([29]), zinc oxide (ZnO) ([29]), tin oxide (SnO) ([29]), and combinations thereof, for the purpose of providing stacked transistor structure configured with TFT nanowire or nanoribbon structures for the other device layer (e.g., top transistor) without requiring a native substrate to improved logic transistor density and performance ([20]).
Lilak and Dewey are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lilak with the specified features of Dewey because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lilak to have the one or more first nanostructures and the one or more second nanostructures each including a material selected from the group consisting of: indium oxide (In2O3), tin oxide (SnO2), indium gallium zinc oxide (InGaZnO), zinc oxide (ZnO), tin oxide (SnO), and combinations thereof, as taught by Dewey, for the purpose of providing stacked transistor structure configured with TFT nanowire or nanoribbon structures for the other device layer (e.g., top transistor) without requiring a native substrate to improved logic transistor density and performance ([20], Dewey).
Regarding claim 13, Lilak discloses the semiconductor structure of claim 11 as described above.
Lilak does not explicitly disclose the first and second gate structures are physically separated from each other.
Dewey teaches, in at least figure 2a and related text, the device comprising the first (206/203, [27]) and second (204/201, [27]) gate structures are physically separated from each other, for the purpose of providing stacked transistor structure configured with TFT nanowire or nanoribbon structures for the other device layer (e.g., top transistor) without requiring a native substrate to improved logic transistor density and performance ([20]).
Lilak and Dewey are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lilak with the specified features of Dewey because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lilak to have the first and second gate structures being physically separated from each other, as taught by Dewey, for the purpose of providing stacked transistor structure configured with TFT nanowire or nanoribbon structures for the other device layer (e.g., top transistor) without requiring a native substrate to improved logic transistor density and performance ([20], Dewey).
Regarding claim 14, Lilak discloses the semiconductor structure of claim 11 as described above.
Lilak does not explicitly disclose the first nanostructures and the second nanostructures each include a material selected from the group consisting of: indium oxide (In2O3), tin oxide (SnO2), indium gallium zinc oxide (InGaZnO), zinc oxide (ZnO), tin oxide (SnO), and combinations thereof.
Dewey teaches, in at least figure 2a and related text, the device comprising the first nanostructures (205, [27], [29]) and the second nanostructures (202, [27], [29]) each include a material selected from the group consisting of: indium oxide (In2O3) ([29]), tin oxide (SnO2) ([29]), indium gallium zinc oxide (InGaZnO) ([29]), zinc oxide (ZnO) ([29]), tin oxide (SnO) ([29]), and combinations thereof, for the purpose of providing stacked transistor structure configured with TFT nanowire or nanoribbon structures for the other device layer (e.g., top transistor) without requiring a native substrate to improved logic transistor density and performance ([20]).
Lilak and Dewey are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lilak with the specified features of Dewey because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lilak to have the first nanostructures and the second nanostructures each including a material selected from the group consisting of: indium oxide (In2O3), tin oxide (SnO2), indium gallium zinc oxide (InGaZnO), zinc oxide (ZnO), tin oxide (SnO), and combinations thereof, as taught by Dewey, for the purpose of providing stacked transistor structure configured with TFT nanowire or nanoribbon structures for the other device layer (e.g., top transistor) without requiring a native substrate to improved logic transistor density and performance ([20], Dewey).
Regarding claim 20, Lilak discloses the method of claim 18 as described above.
Lilak does not explicitly disclose the one or more first nanostructures and the one or more second nanostructures each include a material selected from the group consisting of: indium oxide (In2O3), tin oxide (SnO2), indium gallium zinc oxide (InGaZnO), zinc oxide (ZnO), tin oxide (SnO), and combinations thereof.
Dewey teaches, in at least figure 2a and related text, the device comprising the one or more first nanostructures (205, [27], [29]) and the one or more second nanostructures (202, [27], [29]) each include a material selected from the group consisting of: indium oxide (In2O3) ([29]), tin oxide (SnO2) ([29]), indium gallium zinc oxide (InGaZnO) ([29]), zinc oxide (ZnO) ([29]), tin oxide (SnO) ([29]), and combinations thereof, for the purpose of providing stacked transistor structure configured with TFT nanowire or nanoribbon structures for the other device layer (e.g., top transistor) without requiring a native substrate to improved logic transistor density and performance ([20]).
Lilak and Dewey are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lilak with the specified features of Dewey because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Lilak to have the one or more first nanostructures and the one or more second nanostructures each including a material selected from the group consisting of: indium oxide (In2O3), tin oxide (SnO2), indium gallium zinc oxide (InGaZnO), zinc oxide (ZnO), tin oxide (SnO), and combinations thereof, as taught by Dewey, for the purpose of providing stacked transistor structure configured with TFT nanowire or nanoribbon structures for the other device layer (e.g., top transistor) without requiring a native substrate to improved logic transistor density and performance ([20], Dewey).
Claim(s) 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lilak (US 2020/0098756) in view of Smith (US 2018/0040695).
Regarding claim 8, Lilak discloses the semiconductor structure of claim 7 as described above.
Lilak does not explicitly disclose the second metal material includes a plurality of third closed-loops surrounding the second closed-loops, respectively.
Smith teaches, in at least figure 5 and related text, the device comprising the second metal material (515, [28]) includes a plurality of third closed-loops surrounding the second closed-loops (loops of 513, [28], figure), respectively, for the purpose of providing a configuration that enables true 3D logic devices and complementary FET 3D logic where NFET and PFET wires are stacked over-top of one another in order to realize significant area scaling benefit of such devices as they allow stacking of devices overtop of one another ([90]).
Lilak and Smith are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lilak with the specified features of Smith because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lilak to have the second metal material including a plurality of third closed-loops surrounding the second closed-loops, respectively, as taught by Smith, for the purpose of providing a configuration that enables true 3D logic devices and complementary FET 3D logic where NFET and PFET wires are stacked over-top of one another in order to realize significant area scaling benefit of such devices as they allow stacking of devices overtop of one another ([90], Smith).
Regarding claim 16, Lilak discloses the semiconductor structure of claim 11 as described above.
Lilak does not explicitly disclose the first metal material includes a plurality of first closed-loops surrounding the one or more first nanostructures and the one or more second nanostructures, respectively, the ferroelectric material includes a plurality of second closed-loops surrounding the first closed-loops, respectively, and the second metal material includes a plurality of third closed-loops surrounding the second closed-loops, respectively.
Smith teaches, in at least figure 5 and related text, the device comprising the first metal material (513, [28]) includes a plurality of first closed-loops surrounding the one or more first nanostructures (lower 503, [28], figure) and the one or more second nanostructures (upper 503, [28], figure), respectively, the ferroelectric material (513, [29]) includes a plurality of second closed-loops surrounding the first closed-loops (loops of 513, [28], figure), respectively, and the second metal material (515, [28]) includes a plurality of third closed-loops surrounding the second closed-loops (loop of 513, [29], figure), respectively, for the purpose of providing a configuration that enables true 3D logic devices and complementary FET 3D logic where NFET and PFET wires are stacked over-top of one another in order to realize significant area scaling benefit of such devices as they allow stacking of devices overtop of one another ([90]).
Lilak and Smith are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lilak with the specified features of Smith because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lilak to have the first metal material including a plurality of first closed-loops surrounding the one or more first nanostructures and the one or more second nanostructures, respectively, the ferroelectric material including a plurality of second closed-loops surrounding the first closed-loops, respectively, and the second metal material including a plurality of third closed-loops surrounding the second closed-loops, respectively, as taught by Smith, for the purpose of providing a configuration that enables true 3D logic devices and complementary FET 3D logic where NFET and PFET wires are stacked over-top of one another in order to realize significant area scaling benefit of such devices as they allow stacking of devices overtop of one another ([90], Smith).
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lilak (US 2020/0098756) in view of Lin (US 2021/0083120).
Regarding claim 9, Lilak discloses the semiconductor structure of claim 1 as described above.
Lilak does not explicitly disclose the gate structure further comprises a high-k dielectric material interposed between the first metal material and each of the one or more first nanostructures and the one or more second nanostructures.
Lin teaches, in at least figures 2, 3A, and related text, the device comprising the gate structure (205G, [42]) further comprises a high-k dielectric material (304, [42]) interposed between the first metal material (305, [42]) and each of the one or more first nanostructures (one of 213A, [42]) and the one or more second nanostructures (another one of 213A, [42]), for the purpose of providing devices (e.g., FETs) to operate in a negative capacitance regime (e.g., in a negative-capacitance FET, or NCFET) for improved device performance ([19]).
Lilak and Lin are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lilak with the specified features of Lin because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lilak to have the gate structure further comprising a high-k dielectric material interposed between the first metal material and each of the one or more first nanostructures and the one or more second nanostructures, as taught by Lin, for the purpose of providing devices (e.g., FETs) to operate in a negative capacitance regime (e.g., in a negative-capacitance FET, or NCFET) for improved device performance ([19], Lin).
Regarding claim 10, Lilak in view of Lin discloses the semiconductor structure of claim 9 as described above.
Lin teaches, in at least figures 2, 3A, and related text, the one or more first nanostructures (one of 213A, [42]), the one or more second nanostructures (another one of 213A, [42]), the high-k dielectric material (304, [42]), and the first metal material (305, [42]) partially operate as a transistor, while the first metal material (305, [42]), the ferroelectric material (306, [42]), and the second metal material (307, [42]) operate as a capacitor connected to the transistor in series ([48]), for the purpose of providing devices (e.g., FETs) to operate in a negative capacitance regime (e.g., in a negative-capacitance FET, or NCFET) for improved device performance ([19]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811