DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 10-15 & 21-34 in the reply filed on 10/22/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 21 is rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Gomes et al. (US Pub. 2023/0197654).
Regarding claim 30, Gomes teaches a method of forming a semiconductor device, comprising:
forming a plurality of back end dielectric layers (e.g. M6-M13, Para [0029,0036,0044,0049,0054], Fig. 1-Fig. 6 & Fig. 10); and
forming a non-volatile memory structure (e.g. ROM 1032 or MRAM 1030, Fig. 10) included in the plurality of back end dielectric layers (ROM or MRAM in Fig. 10 is understood to be employed as one of the plurality of the memory cell array 150 shown in Fig. 1), comprising:
forming a gate structure 318 (Fig. 1 & fig. 3);
forming a channel layer over the gate structure (Para [0045] & Fig. 3);
forming a first source/drain region 302 and a second source/drain region 302 over the channel layer (Fig. 1 & Fig. 3);
forming a first interconnect structure 340 above and coupled to the first source/drain region 302 (see Fig. 3 below),
wherein the first interconnect structure 340 is coupled to a bit line conductive structure 348 in the semiconductor device (see Fig. 3 below); and
forming a second interconnect structure (the other 340) above and coupled to the second source/drain region 302 (see Fig. 3 below),
wherein the second interconnect structure 340 is adjacent to a select line conductive structure (portion of 305 in M6) in the semiconductor device (see Fig. 3 below), and
wherein a portion of a back end dielectric layer, M6 of the plurality of back end dielectric layers (M6-M13), is located between the second interconnect structure 340 and the select line conductive structure (portion of 305, see Fig. 3 below).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 30-34 are rejected under 35 U.S.C. 103 as being unpatentable over Gomes et al. (US Pub. 2023/0197654) in view of Lin et al. (US Pub. 2023/0136441).
Regarding claim 30, Gomes teaches a method, comprising:
forming a plurality of back end dielectric layers (e.g. M6-M13, Para [0029,0036,0044,0049,0054], Fig. 1-Fig. 6 & Fig. 10);
forming a volatile memory array (e.g. DRAM 1032 in Fig. 10), in the plurality of back end dielectric layers (DRAM is understood to be employed as one of the plurality of the memory array 150 in Fig. 1), comprising a plurality of volatile memory structures (Fig. 10 & Fig. 1: it is understood that a volatile memory array comprises a plurality of volatile memory structures); and
forming a non-volatile memory array (e.g. ROM 1035 or MRAM 1030, Fig. 10), in the plurality of back end dielectric layers (ROM or MRAM in Fig. 10 is understood to be employed as one or other if the plurality of the memory cell array 150 shown in Fig. 1), comprising a plurality of non-volatile memory structures ((Fig. 10 & Fig. 1: it is understood that a volatile memory array comprises a plurality of volatile memory structures).
Gomes is silent on wherein a non-volatile memory structure, of the plurality of non-volatile memory structures, includes a programmable resistance-based memory cell region that corresponds to a portion of a back end dielectric layer of the plurality of back end dielectric layers. However, Lin teaches in Fig. 9-10, wherein a non-volatile memory structure, of a plurality of non-volatile memory structures, includes a programmable resistance-based memory cell region 100 that corresponds to a portion of a back end dielectric layer of a plurality of back end dielectric layers (20, 28 & 30). This has the advantage of superior data retention, high speed program/erase (P/E) and low operating voltages for use in non-volatile memory application in BEOL process. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Gomes with the programmable resistance-based memory cell region, as taught by Lin, so as to obtain a semiconductor device with ultra high density, high speed and low power consumption.
Regarding claim 31, the combination of Gomes and Lin teaches the method of claim 30, wherein a volatile memory structure 150 of the plurality of volatile memory structures, includes a deep trench capacitor structure 20 (Fig.1, Fig. 3 & Fig. 10) configured to selectively store an electrical charge for the volatile memory structure; and wherein the programmable resistance-based memory cell region 100 (Lin’s Fig. 9-10) is configured to be selectively programmed by modifying an electrical resistance in the programmable resistance-based memory cell region (e.g. Gomes’ Fig. 1, Fig. 3-6 & Fig. 10 and Lin’s Fig. 9-10 and associated texts).
Regarding claim 32, the combination of Gomes and Lin teaches the method of claim 30, wherein the programmable resistance-based memory cell region 100 is configured to be programmed for a plurality of program-erase cycles (Gomes’ Fig. 1, Fig. 3-6 & Fig. 10 and Lin’s Fig. 9-10 and associated texts).
Regarding claim 33, the combination of Gomes and Lin teaches the method of claim 30, wherein the programmable resistance-based memory cell region 100 is configured to be programmed for a single programming operation (Gomes’ Fig. 1, Fig. 3-6 & Fig. 10 and Lin’s Fig. 9-10 and associated texts).
Regarding claim 34, the combination of Gomes and Lin teaches the method of claim 30, wherein the non-volatile memory structure is configured to provide a plurality of current pulses to the programmable resistance-based memory cell region 100 to modify an electrical resistance in the programmable resistance-based memory cell region (Gomes’ Fig. 1, Fig. 3-6 & Fig. 10 and Lin’s Fig. 9-10 and associated texts).
Regarding claims 31-34, please note that it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Gomes as applied to claim 1 above, and further in view of Lin et al.
Regarding claim 22, Gomes is silent on the method of claim 21, wherein the non-volatile memory structure is a resistive random access memory (ReRAM) structure; and wherein the portion of the back end dielectric layer, between the second interconnect structure and the select line conductive structure, corresponds to a programmable ReRAM cell of the ReRAM structure.
However, Lin teaches in Fig. 9-10, wherein a non-volatile memory structure is a resistive random access memory (ReRAM) structure 100; and once incorporated into Gomes’ device, the portion of the back end dielectric layer, between the second interconnect structure and the select line conductive structure (see Gomes’s Fig. 3 above), corresponds to a programmable ReRAM cell of the ReRAM structure (Lin’s Fig. 9-10). This has the advantage of superior data retention, high speed program/erase (P/E) and low operating voltages for use in non-volatile memory application in BEOL process. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Gomes with the programmable resistance-based memory cell region, as taught by Lin, so as to obtain a semiconductor device with ultra high density, high speed and low power consumption.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Gomes as applied to claim 1 above, and further in view of Kurz et al. (US Pub. 2013/0062728).
Regarding claim 23, Gomes is silent on the method of claim 21, wherein the non-volatile memory structure is a one-time programmable anti-fuse memory structure; and wherein the portion of the back end dielectric layer, between the second interconnect structure and the select line conductive structure, corresponds to a one-time programmable anti-fuse of the one-time programmable anti-fuse memory structure.
However, Kurz teaches in Fig. 1A-1B, wherein a non-volatile memory structure is a one-time programmable anti-fuse memory structure; and once incorporated into Gomes’ device, the portion of the back end dielectric layer, between the second interconnect structure and the select line conductive structure (see Gomes’s Fig. 3 above), corresponds to a one-time programmable anti-fuse of the one-time programmable anti-fuse memory structure (Kurz’s Fig. 1A-3 & Para [0027 & 0031]).This has the advantage of improved data retention and ensuring data integrity and security. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Gomes with the programmable anti-fuse memory structure, as taught by Kurz, so as to obtain a semiconductor device with improved data retention and to ensure data integrity and safety.
Allowable Subject Matter
Claims 10-15 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to claim 10, the prior art of record fails to teach or suggest, a method, comprising: forming a word line conductive structure in a semiconductor device; forming a plurality of back end of line (BEOL) dielectric layers over the word line conductive structure; forming, over the word line conductive structure, a recess through the plurality of BEOL dielectric layers to expose the word line conductive structure through the recess; forming a gate structure, of a non-volatile memory structure of the semiconductor device, in the recess such that the gate structure is coupled with the word line conductive structure; forming a first source/drain region and a second source/drain region of the non-volatile memory structure over the gate structure; forming a first interconnect structure on the first source/drain region; forming a bit line conductive structure over the first interconnect structure such that the bit line conductive structure is physically coupled with the first interconnect structure, wherein the bit line conductive structure is formed in a BEOL dielectric layer of the plurality of BEOL dielectric layers; and forming a select line conductive structure in the BEOL dielectric layer; and forming a second interconnect structure in the BEOL dielectric layer and on the second source/drain region, wherein the second interconnect structure is formed such that the second interconnect structure and the select line conductive structure are spaced apart by the BEOL dielectric layer.
Claims 2-15 are allowed as being directly or indirectly dependent of the allowed independent base claim 1.
Claims 24-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818