DETAILED ACTION
This Office action responds to the patent application no. 18/337,040 filed on June 19, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4-9, 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (Yu hereinafter) (US 9,601,463).
Regarding Claims 1, 2, 4-9, 14-16:
Yu (see FIGs. 1A and 2A-2O) teaches {1} a semiconductor device, comprising: a bridge carrier 101A/108A, comprising: a carrier substrate 101A; and a bridge redistribution structure 108A disposed on the carrier substrate; a first die 104A and a second die 104A disposed side by side on the bridge carrier, wherein the bridge redistribution structure electrically connects the first die and the second die; a first encapsulant 124 laterally encapsulating the first die and the second die; a cap carrier 130 disposed over the first die and the second die; a third die 104B located between the first die and the cap carrier; and a second encapsulant 124 laterally encapsulating the third die;
{2} the bridge carrier further comprises: a signal outputting redistribution structure 106 disposed on the carrier substrate opposite to the bridge redistribution structure; and through vias 126A penetrating through at least a portion of the carrier substrate to electrically connect the bridge redistribution structure and the signal outputting redistribution structure;
{4} a vertical projection of at least a portion of the bridge patterns 109A onto the carrier substrate is overlapped with a vertical projection of the first encapsulant 124 onto the carrier substrate;
{5} a bonding layer 108B located between the first die and the third die, between the first die and the second encapsulant, and between the first encapsulant and the second encapsulant, wherein the bonding layer comprises a bonding dielectric layer and bonding pads 109B embedded in the bonding dielectric layer, and a region directly above the first encapsulant is free of the bonding pads;
{6} a fourth die 104B located between the second die and the cap carrier, wherein the third die is completely located within a span of the first die, and the fourth die is completely located within a span of the second die;
{7} the first die 104A and the second die 104A respectively comprise an interconnection structure 114/116, and the interconnection structure of the first die and the interconnection structure of the second die are in physical contact with the bridge redistribution structure;
{8} the first encapsulant is in physical contact with the bridge redistribution structure;
{9} a semiconductor device, comprising: a bridge carrier 101A/108A; a first die 104A and a second die 104A disposed side by side on the bridge carrier, wherein the bridge carrier electrically connects the first die and the second die, and the first die has a central region and a peripheral region surrounding the central region; a first encapsulant 124 laterally encapsulating the first die and the second die; a bonding layer 108B disposed on the first die, the second die, and the first encapsulant, wherein the bonding layer comprises a bonding dielectric layer and bonding pads 109B embedded in the bonding dielectric layer, and the bonding pads are located in the central region of the first die; and a third die 104B bonded to the first die through the bonding layer;
{14} a fourth die 104B bonded to the second die through the bonding pads; a second encapsulant 124 laterally encapsulating the third die and the fourth die; and a cap carrier 130 attached to the third die, the fourth die, and the second encapsulant;
{15} the first die 104A and the second die 104A respectively comprise an interconnection structure, and the interconnection structure of the first die and the interconnection structure of the second die are in physical contact with the bridge carrier 101A/108; and
{16} the first encapsulant 124 is in physical contact with the bridge carrier 101A/108.
Yu (see col.3/l.28 – col.4/l.1, col.4/ll.14-63, col.5/ll.23-31, col.6/ll.20-22, col.7/ll.38-40, col.9/ll.23-25, col.11/ll.32-34, ) teaches
i) “Each fan-out tier of the device packages may include one or more of … the like memory chips … number of chips in each fan-out tier may be greater than or equal to one … each fan-out tier 101 includes one or more device dies such as a core logic die 102 and other dies 104 … Front side (FS) fan-out redistribution layers (RDLs) 108A and 108B are disposed between each tier 101, and back side (BS) RDLs 106 may be disposed on a backside of first fan-out tier 101. RDLs 106/108 may include various conductive features 107/109 (e.g., conductive lines and vias), respectively, formed between dielectric (e.g., polymer) layers … Die 102 may include an interconnect structure (not shown)”;
ii) “interconnect structure may include inter-layer dielectric (ILD) and/or inter-metal dielectric (IMD) layers containing conductive features … pillar bumps 110 may be disposed over contact pads, and a dielectric material 112 … pillar bumps 110 may electrically connect die 102 to FS RDLs 108A … under metallurgies (UBMs) 114 formed on an opposing side of FS RDLs 108A and die 102 … on a front side of dies 104A may be bonded … to UMBs 114 … dies 104A may be substantially similar to dies 102 although dies 104A may include different functional circuits … the dies 104 … may be bonded to and electrically interconnected by FS RDLs 108A … additional FS RDLs may be used to bond additional fan-out tiers having additional dies to tiers 101A and 101B”;
iii) “TIVs 126A and 126B (also referred to as through-molding vias) may extend through molding compounds 124 and may help to electrically connect dies 104 to die 102 and/or connector 120 by way of FS RDLs 108A/108B and/or BS RDLs 106 … a thermal interface material (TIM) 128 and a heat dissipation lid 130 may be disposed over a top-most fan-out tier”;
iv) “a conductive seed layer 138 (e.g., comprising copper) may optionally be formed over BS RDLs 106”;
v) “Dies 104A may be electrically connected to FS RDLs 108A, which may electrically connect dies 104A to die 102”; and
vi) “one or more FS RDLs (e.g., FS RDLs 108A) is formed over tier 101A … may include various conductive features in a dielectric material”, vii) “one or more FS RDLs (e.g., FS RDLs 108A) … may be electrically connected to dies 104A”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (Yu hereinafter) (US 9,601,463) as applied to claim 1 above, and further in view of Kim et al. (Kim hereinafter) (US 9,230,936).
Regarding Claims 3 and 10-12:
Yu (col.7/ll.38-40) teaches “Dies 104A may be electrically connected to FS RDLs 108A, which may electrically connect dies 104A to die 102”, but does not explicitly teach {3} the bridge redistribution structure comprises: a dielectric layer; routing patterns 109A embedded in the dielectric layer; bridge patterns 109A embedded in the dielectric layer, wherein the bridge patterns 109A extend from the first die to the second die to electrically connect the first die and the second die; {10} the peripheral region of the first die is free of the bonding pads; {11} the bridge carrier comprises: a carrier substrate 101A; a bridge redistribution structure 108A disposed on one side of the carrier substrate and comprising: a dielectric layer; routing patterns 109A embedded in the dielectric layer; and bridge patterns 109A embedded in the dielectric layer, wherein the bridge patterns are located in the peripheral region of the first die; a signal outputting redistribution structure 106 disposed on another side of the carrier substrate; and through vias 126A penetrating through at least a portion of the carrier substrate to electrically connect the bridge redistribution structure and the signal outputting redistribution structure; and {12} a vertical projection of at least a portion of the bridge patterns onto the carrier substrate is overlapped with a vertical projection of the first encapsulant onto the carrier substrate.
Kim (see FIGs. 5, 6, and 7D) teaches the first die 506/606 may be electrically coupled to the second die 508/608 through a fifth set of redistribution interconnections 580/680.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Yu to include the teaching of Kim to form a patterned bridge interconnection between two adjacent dies at the closest peripheral region of the dies within any one of the redistribution layers to achieve high density interconnections and shortest distance between two adjacent dies per design requirements.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (Yu hereinafter) (US 9,601,463) as applied to claim 9 above, and further in view of Hung et al. (Hung hereinafter) (US 9,184,128).
Regarding Claim 13:
Yu teaches multi-tiered die packaging structures with different sizes of the dies, but does not explicitly teach the third die is located in the central region.
Hung (see FIGs. 18-29 and 35B) teaches the dies 200 located in the central region of the dies 100 or two small dies 200 located on one large die 100.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Yu to include the teaching of Hung to stack the small die in the middle of the larger die to meet the design requirements when different sizes of dies are stacked together.
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (Yu hereinafter) (US 9,601,463) in view of Kim et al. (Kim hereinafter) (US 9,230,936) and further in view of Jeng et al. (Jeng hereinafter) (US 2021/0193637).
Regarding Claims 17-20:
Yu (see FIGs. 2A-2O) teaches {17} manufacturing method of a semiconductor device, comprising: forming a bridge carrier , comprising: providing a carrier substrate 134; forming a bridge redistribution structure 106 on the carrier substrate; placing a first die 102 and a second die 104 side by side on the bridge carrier so that the bridge redistribution structure electrically connects the first die and the second die; laterally encapsulating the first die and the second die by a first encapsulant 124; bonding a third die 104A to the first die; laterally encapsulating the third die by a second encapsulant 124; {20} forming a bonding layer 108A between the first die and the third die, between the first die and the second encapsulant, and between the first encapsulant and the second encapsulant, wherein the bonding layer comprises a bonding dielectric layer and bonding pads 109A embedded in the bonding dielectric layer, and a region directly above the first encapsulant is free of the bonding pads; {18} the bridge redistribution structure comprises bridge patterns 107; and {19} a vertical projection of at least a portion of the bridge patterns onto the carrier substrate is overlapped with a vertical projection of the first encapsulant onto the carrier substrate.
Yu (see col.3/l.28 – col.4/l.1, col.5/ll.28-31, and col.7/ll.38-40) teaches i) “Each fan-out tier of the device packages may include one or more of … the like memory chips … number of chips in each fan-out tier may be greater than or equal to one … each fan-out tier 101 includes one or more device dies such as a core logic die 102 and other dies 104 … Front side (FS) fan-out redistribution layers (RDLs) 108A and 108B are disposed between each tier 101, and back side (BS) RDLs 106 may be disposed on a backside of first fan-out tier 101. RDLs 106/108 may include various conductive features 107/109 (e.g., conductive lines and vias), respectively, formed between dielectric (e.g., polymer) layers … Die 102 may include an interconnect structure (not shown)”; ii) “package 100 may also include additional features … a thermal interface material (TIM) 128 and a heat dissipation lid 130 may be disposed over a top-most fan-out tier”; and iii) “Dies 104A may be electrically connected to FS RDLs 108A, which may electrically connect dies 104A to die 102”.
However, Yu does not explicitly teach {17} attaching a cap carrier to the third die and the second encapsulant and {18} the bridge patterns extend from the first die to the second die to electrically connect the first die and the second die.
Kim (see FIGs. 5, 6, and 7D) teaches the first die 506/606 may be electrically coupled to the second die 508/608 through a fifth set of redistribution interconnections 580/680.
Jeng (see ¶ [0016] and FIGs. 11-12) teaches an interconnect structure 28 formed on a package component 20 including a substrate 24, dielectric layer 26, and through-vias 42; System-on-Chip (Soc) package 50 including a single device die or a plurality of device dies bonded together to form a system; backside interconnect structure; and solder regions 72.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Yu to limit the number of fan-out tiers only to two so that the a cap carrier can be attached to the top-most fan-out tier by design requirements and to include the teaching of Kim to form a patterned bridge interconnection between two adjacent dies at the closest peripheral region of the dies within any one of the redistribution layers to achieve high density interconnections and shortest distance between two adjacent dies per design requirements and to further include the teaching of Jeng to attach the dies to different kind of carrier with through-vias not only to provide the mechanical strength support during the manufacturing process of forming additional dies or fan-out tiers on top of the carrier and also can be planarized on the other/back side to receive backside interconnect structure and solders for further connection to avoid the removal of the carrier completely for cost saving and for reducing waste.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm..
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/ALICE W TANG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814