CTNF 18/337,262 CTNF 74962 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. DETAILED ACTION This office action is in response to response to application 18/337262 filed on 06/19/23. Summary of claims Claims 1-20 are pending. Claims 1-20 are rejected. Oath/Declaration The oath/declaration filed on June 19 th , 2023 is acceptable. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-20 rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Choi et al. (US Pub. 2021/0165940) . As to claims 1 the prior art teaches a method, comprising: tagging, by a processor, source process design kit (PDK) devices (see fig 1 element S20) in a source- circuit design (see fig 1 element S20 paragraph 0031-0035); generating, by the processor, a source design simulation database based (see fig 1 element S40) on source design key performance indicator (KPI) simulation data (see fig 1 element S60) of the source-PDK devices in the source-circuit design (see fig 1 element S20 paragraph 0033-0040); generating, by the processor, a target-PDK simulation database based on target design KPI simulation data of a plurality of target-PDK devices (see fig 1, fig 2 paragraph 0038-0044) creating, by the processor, a matching table based on the source design simulation database (see fig 1-3 paragraph 0044-0048); matching, by the processor based on the matching table, one or more target-PDK devices from the target-PDK simulation database with each source-PDK device in the source design simulation database based on source-PDK device KPIs (see fig 1-4 paragraph 0047-0052); ranking, by the processor, the one or more target-PDK devices matched from the target-PDK simulation database with each source-PDK device in the source design simulation database based on the source-PDK device KPIs (see fig 1-3 and 6-7 paragraph 0056-0061); and exchanging, by the processor based on a migration mapping table that includes a one-to-one relationship for target-PDK devices to the source-PDK devices in the source- circuit design, one or more source-PDK devices in the source-circuit design with one-to- one relational target-PDK devices (see fig 1-3 and 6-9 paragraph 0060-0067). As to claims 2 and 14, the prior art teaches wherein the tagging the source-PDK devices in the source- circuit design comprises: reducing, by the processor, the source-circuit design into the source-PDK devices, where each source-PDK device includes one or more physical or functional parameters (see fig 1 paragraph 0038-0042). As to claims 3 and 15 the prior art teaches wherein the tagging the source-PDK devices in the source- circuit design comprises: categorizing, by the processor, each source-PDK device through a hierarchical tagging, where a user is able to input hierarchies based on a plurality of source-PDK device parameters (see fig 1-3 paragraph 0041-0045). As to claims 4 the prior art teaches wherein the tagging the source-PDK devices in the source- circuit design comprises: determining, by the processor, functionality of each source-PDK device in the source-circuit design (see fig 1 paragraph 0030-0033); filling, by the processor, PDK parameters for each physical or functional parameter (see fig 1 paragraph 0032-0036); and creating, by the processor, a tagging table that includes each source-PDK device along with each source-PDK device's PDK parameter (see fig 1 paragraph 0035-0039). As to claim 5 the prior art teaches wherein the generating the source design simulation database based on the source design KPI simulation data of the source-PDK devices in the source-circuit design comprises: converting, by the processor, the tagging table into a simulation netlist format to create a netlist (see fig 1-3 paragraph 0040-0044); executing, by the processor, a simulation with the netlist (see fig 1-3 paragraph 0043-0046); and sending, by the processor, the source design KPI simulation data to the source design simulation database (see fig 1-3 paragraph 0045-0050). As to claims 6 and 19 the prior art teaches wherein the generating the target-PDK simulation database based on target design KPI simulation data of the plurality of target-PDK devices comprises: parsing, by the processor, a list of target-PDK devices; and creating, by the processor, a device list of the target-PDK devices (see fig 1-4 paragraph 0051-0055). As to claims 7, 16 and 20 the prior art teaches wherein the generating the target-PDK simulation database based on the target design KPI simulation data of the plurality of target-PDK devices comprises: categorizing, by the processor, each target-PDK device through a hierarchical tagging, where a user is able to input hierarchies based on a plurality of target-PDK device parameters (see fig 1-4 paragraph 0054-0058); and creating, by the processor, a tagging table that includes each of target-PDK devices along with each of target-PDK device's PDK parameters (see fig 1-4 paragraph 0057-0063). As to claims 8 and 18 the prior art teaches wherein the generating the target-PDK simulation database based on the target design KPI simulation data of the plurality of target-PDK devices comprises: converting, by the processor, the tagging table into a simulation netlist format to create a netlist (see fig 4-7 paragraph 0063-0068); executing, by the processor, a simulation with the netlist (see fig 4-7 paragraph 0066-0070); and sending, by the processor, the target design KPI simulation data to the target-PDK simulation database (see fig 4-7 paragraph 0069-0074). As to claim 9 the prior art teaches a system, comprising: a processor; a memory operably coupled to the processor, the memory containing stored instructions, that in response to being executed by the processor cause the system to: identify source process design kit (PDK) devices and source-device parameters for each source-PDK device in a source-circuit design (see fig 1 element S20 paragraph 0031-0035); generate a source design simulation database based on source design key performance indicator (KPI) simulation data created by a netlist simulation of the source- PDK devices in the source-circuit design(see fig 1 element S20 paragraph 0033-0040); generate a target-PDK simulation database based on target design KPI simulation data of a plurality of target-PDK devices (see fig 1, fig 2 paragraph 0038-0044); match, based on a screening condition table, one or more target-PDK devices from the target-PDK simulation database with each source-PDK device in the source design simulation database based on source-PDK device KPIs (see fig 1-4 paragraph 0047-0052); and exchange, based on a migration mapping table that includes a one-to-one relationship for target-PDK devices to the source-PDK devices in the source-circuit design, one or more source-PDK devices in the source-circuit design with one-to-one relational target-PDK devices (see fig 1-3 and 6-9 paragraph 0060-0067). As to claims 10 the prior art teaches wherein the matching the one or more target-PDK devices from the target-PDK simulation database with each source-PDK device in the source design simulation database based on the source-PDK device KPIs comprises: identify equations within the matching table, where each equation includes device variables (see fig 1-4 paragraph 0048-0051); identify the device variables; identify, based upon a location of the device variables in the matching table, correlating conditions for each device variable within the source design simulation database (see fig 1-4 paragraph 0050-0053); and identify, based on each correlating condition, a matched device in the target- PDK simulation database (see fig 1-4 paragraph 0053-0057). As to claims 11, the prior art teaches wherein the stored instructions, that in response to being executed by the processor further cause the system to: screen the target-PDK simulation database; retain each matched target-PDK device that meets a corresponding correlating condition (see fig 1-6 paragraph 0054-0059); and store retained matched target-PDK devices in a screened database (see fig 1-6 paragraph 0075-0078). As to claims 12 the prior art teaches wherein the stored instructions, that in response to being executed by the processor further cause the system to: rank, based on a ranking equation, each retained matched target-PDK device (see fig 1-4 paragraph 0030-0036); select each matched target-PDK device that satisfies the ranking equation; output a one-to-one table correlating each source-PDK device in the source- circuit design with the selected matched target-PDK device that satisfies the ranking equation (see fig 1-4 paragraph 0033-0039). As to claims 13 the prior art teaches wherein the exchange, based on the migration mapping table that includes the one-to-one relationship for the target-PDK devices to the source- PDK devices in the source-circuit design, the one or more source-PDK devices in the source-circuit design with the one-to-one relational target-PDK devices comprises: generate a mapping table, based the migration mapping table, that retains PDK related parameters from the migration mapping table (see fig 1-4 paragraph 0037-0043); locate the source-PDK devices in a source design schematic open Access (OA) database according to the mapping table (see fig 1-4 paragraph 0042-0047); and write a source-PDK device parameter with a matched target-PDK device's parameter (see fig 1-4 paragraph 0049-0057). As to claim 17 the prior art teaches a non-transitory computer-readable media having computer-readable instructions stored thereon, which when executed by a processor causes an apparatus to: identify source process design kit (PDK) devices and source-PDK device KPI parameters for each source-PDK device in a source-circuit design (see fig 1 element S20 paragraph 0031-0035); generate a source design simulation key performance indicator (KPI) database based on a netlist simulation of source-PDK devices in the source-circuit design (see fig 1 element S20 paragraph 0033-0040); generate a target-PDK device simulation KPI database based on hierarchical tagging of target-PDK devices and on a netlist simulation of the target-PDK devices (see fig 1, fig 2 paragraph 0038-0044); match, based on a matching table, one or more target-PDK devices from the target- PDK device simulation KPI database with each source-PDK device in the source-circuit design based on source-PDK device KPIs (see fig 1-4 paragraph 0047-0052); and exchange, based on each matched target-PDK device satisfying source-PDK KPI criteria for the source-circuit design, one or more source-PDK devices in the source- circuit design with a ranked matched target-PDK device (see fig 1-3 and 6-9 paragraph 0060-0067). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on flex 7:00Am-8PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BINH C TAT/Primary Examiner, Art Unit 2851 Application/Control Number: 18/337,262 Page 2 Art Unit: 2851 Application/Control Number: 18/337,262 Page 3 Art Unit: 2851 Application/Control Number: 18/337,262 Page 4 Art Unit: 2851 Application/Control Number: 18/337,262 Page 5 Art Unit: 2851 Application/Control Number: 18/337,262 Page 6 Art Unit: 2851 Application/Control Number: 18/337,262 Page 7 Art Unit: 2851 Application/Control Number: 18/337,262 Page 8 Art Unit: 2851
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