DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed November 14, 2025.
Claims 1-4 and 6-21 are pending. Claim 5 is canceled. Claim 21 is new. Claims 1, 9-11 and 20 are amended. Claims 1, 10 and 20 are independent.
Continued Examination Under 37 CFR 1.114 After Final Rejection
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 15, 2025 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 10-14, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lung et al. (U.S. 2010/0195378; hereinafter “Lung”) in view of Augustine et al. (U.S. 2024/0053987; hereinafter “Augustine”).
Regarding independent claim 1, Lung teaches a memory circuit (Fig. 1), comprising:
a first bit line (Fig. 1: 41);
a memory cell (Fig. 1:35) coupled to the first bit line (Fig. 1: 41);
a selection circuit (Fig. 1: 52/53) coupled to the memory cell (Fig. 1:35), the selection circuit (Fig. 1: 52/53) comprising:
a first transistor on a first level (Fig. 1: 52); and
a second transistor on a second level different from the first level (Fig. 1: 53);
a first word line (Fig. 1: 23a) coupled to at least the first transistor (Fig. 1: 52) or the second transistor;
a first source line (Fig. 1: 28a) coupled to at least the first transistor (Fig. 1: 52) or the second transistor;
the first transistor is configured to perform a write operation of the memory cell in response to the memory cell being configured to store a first logical value (see page 3, par. 0040), and
the second transistor is configured to perform a read operation of the memory ell, and the write operation of the memory cell in response to the memory cell being configured to store a second logical value different from the first logical value (see pages 1-2, par. 0011-0012 and page 3, par. 0038-0040).
However, Lung is silent with respect to wherein the first transistor and the second transistor are part of a complementary field-effect transistor (CFET) in a vertical configuration.
Similar to Lung, Augustine teaches a memory circuit (Fig. 13) comprising a first transistor on a first level and a second transistor on a second level different from the first level (Fig. 1).
Furthermore, Augustine teaches wherein the first transistor and the second transistor are part of a complementary field-effect transistor (CFET) in a vertical configuration (Fig. 1; see also pages 1-2, par. 0020).
Since Augustine and Lung are from the same field of endeavor, the teachings described by Augustine would have been recognized in the pertinent art of Lung.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Augustine with the teachings of Lung for the purpose of improve transistor scaling, see Augustine’s page 1, par. 0019.
Regarding claim 2, Lung in combination with Augustine teaches the limitations with respect to claim 1.
Furthermore, Lung teaches wherein the first transistor (Fig. 1: 52) comprises:
a first gate terminal coupled to the first word line (Fig. 1: 52 comprises a gate terminal coupled to 23a);
a first drain terminal coupled to a first end of the memory cell (Fig. 1: 52 comprises a drain terminal coupled to 35); and
a first source terminal coupled to the first source line (Fig. 1: 52 comprises a source terminal coupled to 28a); and
the second transistor (Fig. 1: 53) comprises:
a second gate terminal (Fig. 1: 53 comprises a gate terminal coupled to 23b);
a second drain terminal coupled to the first drain terminal and the first end of the memory cell (Fig. 1: 53 comprises a drain terminal coupled to 35 and drain terminal of 52); and
a second source terminal (Fig. 1: 53 comprises a source terminal coupled to 28b).
Regarding claim 3, Lung in combination with Augustine teaches the limitations with respect to claim 1.
Furthermore, Lung teaches a second word line coupled to the second gate terminal of the second transistor (Fig. 1: 53 comprises a gate terminal coupled to 23b); and
a second source line coupled to the second source terminal of the second transistor (Fig. 1: 53 comprises a source terminal coupled to 28b).
Regarding claim 4, Lung in combination with Augustine teaches the limitations with respect to claim 3.
Furthermore, Augustine teaches wherein the first transistor is a first type (Fig. 1: PMOS), the second transistor is a second type (Fig. 1: NMOS) different from the first type, and the second transistor is on the second level (Fig. 1 shows NMOS transistor on top of the PMOS transistor).
Regarding independent claim 10, Lung teaches a memory circuit (Fig. 1), comprising:
a first bit line (Fig. 1: 41);
a second bit line (Fig. 1: 42);
a memory cell array (see page 2, par. 0015) comprising:
a first memory cell (Fig. 1: 35) coupled to the first bit line (Fig. 1: 41); and
a second memory cell (Fig. 1: 45) coupled to the second bit line (Fig. 1: 42);
a selection circuit array (Fig. 1: a plurality of 52s/53s and 50s/51s) coupled to the memory cell array (Fig. 1: 35s and 36s), the selection circuit array comprising:
a first selection circuit (Fig. 1: 52/53) coupled to the first memory cell (Fig. 1: 35), the first selection circuit (Fig. 1: 52/53) comprising:
a first transistor (Fig. 1: 52); and
a second transistor (Fig. 1: 53);
a second selection circuit (Fig. 1: 52/53 coupled to 45) coupled to the second memory cell (Fig. 1: 45);
the first transistor is configured to perform a write operation of the first memory cell in response to the first memory cell being configured to store a first logical value (see page 3, par. 0040), and
the second transistor is configured to perform a read operation of the first memory cell, and the write operation of the first memory cell in response to the first memory cell being configured to store a second logical value different from the first logical value (see pages 1-2, par. 0011-0012 and page 3, par. 0038-0040).
However, Lung is silent with respect to wherein the first transistor and the second transistor are part of a complementary field-effect transistor (CFET) in a vertical configuration.
Similar to Lung, Augustine teaches a memory circuit (Fig. 13) comprising a first transistor and a second transistor (Fig. 1).
Furthermore, Augustine teaches wherein the first transistor and the second transistor are part of a complementary field-effect transistor (CFET) in a vertical configuration (Fig. 1; see also pages 1-2, par. 0020).
Since Augustine and Lung are from the same field of endeavor, the teachings described by Augustine would have been recognized in the pertinent art of Lung.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Augustine with the teachings of Lung for the purpose of improve transistor scaling, see Augustine’s page 1, par. 0019.
Regarding claim 11, Lung in combination with Augustine teaches the limitations with respect to claim 10.
Furthermore, Lung teaches a first word line coupled to one of the first memory cell or the second memory cell (Fig. 1: 23a electrically coupled to 35 and 45);
a first source line coupled to at least the first memory cell (Fig. 1: 28a electrically coupled to 35 and 45); and
a second source line coupled to at least the second memory cell (Fig. 1: 28b electrically coupled to 35 and 45).
Regarding claim 12, Lung in combination with Augustine teaches the limitations with respect to claim 11.
Furthermore, Lung teaches wherein the second selection circuit (Fig. 1: 52/53 coupled to 45) comprises:
a third transistor (Fig. 1: 52 coupled to 45); and
a fourth transistor (Fig. 1: 53 coupled to 45).
Regarding claim 13, Lung in combination with Augustine teaches the limitations with respect to claim 12.
Furthermore, Lung teaches wherein the first transistor (Fig. 1: 52) comprises:
a first gate terminal coupled to the first word line (Fig. 1: 52 coupled to 23a);
a first drain terminal coupled to a first end of the first memory cell (Fig. 1: 52 coupled to 35); and
a first source terminal coupled to the first source line (Fig. 1: 52 coupled to 28a); and
the second transistor (Fig. 1: 53) comprises:
a second gate terminal (Fig. 1: 53 coupled to 23b);
a second drain terminal coupled to the first drain terminal and the first end of the first memory cell (Fig. 1: 53 coupled to 35 and 52); and
a second source terminal (Fig. 1: 53 coupled to 28b).
Regarding claim 14, Lung in combination with Augustine teaches the limitations with respect to claim 13.
Furthermore, Lung teaches wherein the third transistor (Fig. 1: 52 coupled to 45) comprises:
a third gate terminal coupled to the first word line (Fig. 1: 52 coupled to 45 comprises gate coupled to 23a);
a third drain terminal coupled to a first end of the second memory cell (Fig. 1: 52 having drain terminal coupled to 45); and
a third source terminal coupled to the second source line (Fig. 1: transistor 52 coupled to 45 comprises a source terminal coupled to 28a); and
the fourth transistor (Fig. 1: 53 coupled to 45) comprises:
a fourth gate terminal (Fig. 1: 53 coupled to 45 comprises a gate terminal coupled to 23b);
a fourth drain terminal coupled to the third drain terminal and the first end of the second memory cell (Fig. 1: 53 having drain terminal coupled to 45); and
a fourth source terminal (Fig. 1: transistor 53 coupled to 45 comprises a source terminal coupled to 28b).
Regarding claim 17, Lung in combination with Augustine teaches the limitations with respect to claim 14.
Furthermore, Lung teaches a second word line coupled to the second gate terminal of the second transistor and the fourth gate terminal of the fourth transistor (Fig. 1: word line 23b coupled to the gate of transistors 53 that are coupled to 35 and 45 respectively),
wherein the second source terminal of the second transistor is coupled to the first source line (Fig. 1: source terminal of 53 is electrically coupled to 28a), and the fourth source terminal of the fourth transistor is coupled to the second source line (Fig. 1: source terminal of 53 coupled to 45 is coupled to 28b).
Regarding independent claim 20, Lung teaches a method of operating a memory circuit (see page 1, par. 0004), the method comprising:
performing a write operation of a memory cell, the performing the write operation of the memory cell comprises (“set” and “reset” operations, see pages 1-2, par. 0012):
storing a first logical value in the memory cell by a first transistor of a selection circuit, the selection circuit being coupled to the memory cell (see page 3, par. 0038); or
storing a second logical value in the memory cell by a second transistor of the selection circuit, the second logical value being different from the first logical value (see page 3, par. 0040); and
performing a read operation of the memory cell by the first transistor of the selection circuit (see page 3, par. 0039).
However, Lung is silent with respect to wherein the first transistor is on a first level and the second transistor is on a second level different from the first level, and the first transistor and the second transistor are part of a complementary field-effect transistor (CFET) in a vertical configuration.
Augustine teaches wherein the first transistor is on a first level and the second transistor is on a second level different from the first level, and the first transistor and the second transistor are part of a complementary field-effect transistor (CFET) in a vertical configuration (Fig. 1; see also pages 1-2, par. 0020).
Since Augustine and Lung are from the same field of endeavor, the teachings described by Augustine would have been recognized in the pertinent art of Lung.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Augustine with the teachings of Lung for the purpose of improve transistor scaling, see Augustine’s page 1, par. 0019.
Claims 6-7, 15-16, 18-19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Lung and Augustine as applied to claim 2 above, and further in view of Pyo et al. (U.S. 2018/0122467; hereinafter “Pyo”).
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Regarding claim 6, Lung in combination with Augustine teaches the limitations with respect to claim 2.
Furthermore, Lung teaches a second word line coupled to the second gate terminal of the second transistor (Fig. 1: 23b coupled to the gate of 53).
However, the combination is silent with respect to wherein the second source terminal of the second transistor is coupled to the first source line.
Similar to Lung in combination with Augustine, Pyo teaches a memory circuit (Fig. 1) comprising a first bit line (Fig. 9: BL), a memory cell coupled to the first bit line (Fig. 9: MTJ coupled to BL), and a selection circuit (Fig. 9: TG) coupled to the memory cell (Fig. 9: MTJ), the selection circuit (Fig. 9: TG) comprising a first transistor (Fig. 9: PMOS) and a second transistor (Fig. 9: NMOS), the first transistor (Fig. 9: PMOS) comprises a first gate terminal (Fig. 11: gate terminal of the PMOS coupled to wWL<1>), a first drain terminal (Fig. 11: drain terminal of the PMOS coupled to MTJ), and a first source terminal (Fig. 11: source terminal of the PMOS coupled to SL<X>), the second transistor (Fig. 9: NMOS) comprises a second gate terminal (Fig. 11: gate terminal of the NMOS coupled to WL<1>), a second drain terminal (Fig. 11: drain terminal of the NMOS coupled to MTJ), and a second source terminal (Fig. 11: source terminal of the NMOS coupled to SL<X>).
Furthermore, Pyo teaches wherein the second source terminal of the second transistor is coupled to the first source line (Fig. 11: source terminal of the NMOS coupled to SL<X>).
Since Pyo, Augustine and Lung are from the same field of endeavor, the teachings described by Pyo would have been recognized in the pertinent art of Lung in combination with Augustine.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Pyo with the teachings of Lung in combination with Augustine for the purpose of improve reliability and operating method and provide a reduce chip size, see Pyo’s page 1, par. 0005.
Regarding claim 7, Lung in combination with Augustine and Pyo teaches the limitations with respect to claim 6.
Furthermore, Augustine teaches wherein the first transistor is a first type (Fig. 1: PMOS), the second transistor is a second type (Fig. 1: NMOS) different from the first type, and the second transistor is on the second level (Fig. 1 shows NMOS transistor on top of the PMOS transistor).
Regarding claim 15, Lung in combination with Augustine teaches the limitations with respect to claim 14.
Furthermore, Lung teaches a second word line coupled to the second gate terminal of the second transistor and the fourth gate terminal of the fourth transistor (Fig. 1: word line 23b is coupled to the gates of the transistors 53 that are coupled to 35 and 45 respectively).
However, the combination is silent with respect to a third source line coupled to the second source terminal of the second transistor and a fourth source line coupled to the fourth source terminal of the fourth transistor.
Similar to Lung in combination with Augustine, Pyo teaches a memory circuit (Fig. 14) comprising first and second memory cells (Fig. 14 shows a plurality of memory cells MTJ) coupled to first and second selection circuit respectively (Fig. 14 shows a plurality of memory cells MTJ coupled to selection circuit comprising PMOS and NMOS), and the first selection circuit comprising a first transistor and a second transistor (Fig. 14: selection circuit comprising PMOS and NMOS), and the second selection circuit comprising a third transistor and a fourth transistor (Fig. 14: selection circuit comprising PMOS and NMOS).
Furthermore, Pyo teaches a third source line coupled to the second source terminal of the second transistor and a fourth source line coupled to the fourth source terminal of the fourth transistor (see Examiner’s Markup Pyo’s Figure 14).
Since Pyo, Augustine and Lung are from the same field of endeavor, the teachings described by Pyo would have been recognized in the pertinent art of Lung in combination with Augustine.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Pyo with the teachings of Lung in combination with Augustine for the purpose of improve reliability and operating method and provide a reduce chip size, see Pyo’s page 1, par. 0005.
Regarding claim 16, Lung in combination with Augustine and Pyo teaches the limitations with respect to claim 15.
Furthermore, Pyo teaches wherein the first transistor is a first type;
the second transistor is a second type different from the first type;
the third transistor is the first type;
the fourth transistor is the second type;
the first transistor is on a first level;
the second transistor is on a second level different from the first level;
the third transistor is on the first level; and
the fourth transistor is on the second level (Fig. 14 shows a plurality of PMOS and NMOS transistor one on top of the other).
Regarding claim 18, Lung in combination with Augustine teaches the limitations with respect to claim 17.
However, the combination is silent with respect to the first transistor is a first type, the second transistor is a second type different from the first type, the third transistor is the first type, the fourth transistor is the second type, the first transistor is on a first level, the second transistor is on a second level different from the first level, the third transistor is on the first level and the fourth transistor is on the second level
Similar to Lung in combination with Augustine, Pyo teaches a memory circuit (Fig. 14) comprising first and second memory cells (Fig. 14 shows a plurality of memory cells MTJ) coupled to first and second selection circuit respectively (Fig. 14 shows a plurality of memory cells MTJ coupled to selection circuit comprising PMOS and NMOS), and the first selection circuit comprising a first transistor and a second transistor (Fig. 14: selection circuit comprising PMOS and NMOS), and the second selection circuit comprising a third transistor and a fourth transistor (Fig. 14: selection circuit comprising PMOS and NMOS).
Furthermore, Pyo teaches wherein the first transistor is a first type;
the second transistor is a second type different from the first type;
the third transistor is the first type;
the fourth transistor is the second type;
the first transistor is on a first level;
the second transistor is on a second level different from the first level;
the third transistor is on the first level; and
the fourth transistor is on the second level (Fig. 14 shows a plurality of PMOS and NMOS transistor one on top of the other).
Since Pyo, Augustine and Lung are from the same field of endeavor, the teachings described by Pyo would have been recognized in the pertinent art of Lung in combination with Lung.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Pyo with the teachings of Lung in combination with Augustine for the purpose of improve reliability and operating method and provide a reduce chip size, see Pyo’s page 1, par. 0005.
Regarding claim 21, Lung in combination with Augustine teaches the limitations with respect to claim 19.
However, the combination is silent with respect to the first transistor is a first type the second transistor is a second type different from the first type, the third transistor is the first type, the fourth transistor is the second type, the first transistor is on a first level, the second transistor is on a second level different from the first level, the third transistor is on the first level and the fourth transistor is on the second level
Pyo teaches wherein the first transistor is a first type;
the second transistor is a second type different from the first type;
the third transistor is the first type;
the fourth transistor is the second type;
the first transistor is on a first level;
the second transistor is on a second level different from the first level;
the third transistor is on the first level; and
the fourth transistor is on the second level (Fig. 14 shows a plurality of PMOS and NMOS transistor one on top of the other).
Since Pyo, Augustine and Lung are from the same field of endeavor, the teachings described by Pyo would have been recognized in the pertinent art of Lung in combination with Lung.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Pyo with the teachings of Lung in combination with Augustine for the purpose of improve reliability and operating method and provide a reduce chip size, see Pyo’s page 1, par. 0005.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lung and Augustine as applied to claim 2 above, and further in view of Roy et al. (U.S. 2020/0211643; hereinafter “Roy”).
Regarding claim 8, Lung in combination with Augustine teaches the limitations with respect to claim 2.
Furthermore, Lung teaches a second source line coupled to the second source terminal of the second transistor (Fig. 1: 28b coupled to second source terminal of 53).
However, the combination is silent with respect to wherein the second gate terminal of the transistor is coupled to the first word line and the first gate terminal.
Similar to Lung in combination with Augustine, Roy teaches a memory circuit (Fig. 1) comprising a memory cell (Fig. 1: 138), a selection circuit (Fig. 1: 134/136) coupled to the memory cell (Fig. 1: 138), the selection circuit (Fig. 1: 134/136) comprising, a first transistor (Fig. 1: 134) comprising a first gate terminal (Fig. 1: 134 comprising a first gate terminal coupled to WL1), a first drain terminal (Fig. 1: 134 comprising a first drain terminal coupled to 138) and a first source terminal (Fig. 1: 134 comprising a source terminal coupled to SL1), a second transistor (Fig. 1: 136) comprising, a second gate terminal (Fig. 1: 136 comprising a gate terminal coupled to WL1), a second drain terminal (Fig. 1: 136 comprising a drain terminal coupled to 138), and a second source terminal (Fig. 1: 136 comprising a second source terminal coupled to INTsense1), and a first word line coupled to at least the first transistor or the second transistor (Fig. 1: WL1 coupled to 134 and 136).
Furthermore, Roy teaches wherein the second gate terminal of the transistor is coupled to the first word line and the first gate terminal (Fig. 1: WL1 coupled to 134 and 136).
Since Roy, Augustine and Lung are from the same field of endeavor, the teachings described by Roy would have been recognized in the pertinent art of Lung in combination with Augustine.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Roy with the teachings of Lung in combination with Augustine for the purpose of increase a transistor strength, see Roy’s page 2, par. 0022.
Regarding claim 9, Lung in combination with Augustine and Roy teaches the limitations with respect to claim 8.
Furthermore, Augustine teaches wherein the first transistor is a first type (Fig. 1: PMOS), the second transistor is a second type (Fig. 1: NMOS) different from the first type, and the second transistor is on the second level (Fig. 1 shows NMOS transistor on top of the PMOS transistor).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lung and Augustine as applied to claim 14 above, and further in view of Pyo et al. (U.S. 2018/0122467; hereinafter “Pyo”) and Roy et al. (U.S. 2020/0211643; hereinafter “Roy”).
Regarding claim 19, Lung in combination with Augustine teaches the limitations with respect to claim 14.
However, the combination is silent with respect to a third source line coupled to the second source terminal of the second transistor, and a fourth source line coupled to the fourth source terminal of the fourth transistor, wherein the second gate terminal of the second transistor and the fourth gate terminal of the fourth transistor are coupled to each other, and are further coupled to the first word line and the first gate terminal and the third gate terminal.
Similar to Lung and Augustine, Pyo teaches a memory circuit (Fig. 14) comprising first and second memory cells (Fig. 14 shows a plurality of memory cells MTJ) coupled to first and second selection circuit respectively (Fig. 14 shows a plurality of memory cells MTJ coupled to selection circuit comprising PMOS and NMOS), and the first selection circuit comprising a first transistor and a second transistor (Fig. 14: selection circuit comprising PMOS and NMOS), and the second selection circuit comprising a third transistor and a fourth transistor (Fig. 14: selection circuit comprising PMOS and NMOS).
Furthermore, Pyo teaches a third source line coupled to the second source terminal of the second transistor and a fourth source line coupled to the fourth source terminal of the fourth transistor (see Examiner’s Markup Pyo’s Figure 14).
Since Pyo, Augustine and Lung are from the same field of endeavor, the teachings described by Pyo would have been recognized in the pertinent art of Lung in combination with Augustine.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Pyo with the teachings of Lung in combination with Augustine for the purpose of improve reliability and operating method and provide a reduce chip size, see Pyo’s page 1, par. 0005.
However, the combination is silent with respect to wherein the second gate terminal of the second transistor and the fourth gate terminal of the fourth transistor are coupled to each other, and are further coupled to the first word line and the first gate terminal and the third gate terminal.
Similar to the combination, Roy teaches a memory circuit (Fig. 1) comprising a memory cell (Fig. 1: 138), a selection circuit (Fig. 1: 134/136) coupled to the memory cell (Fig. 1: 138), the selection circuit (Fig. 1: 134/136) comprising, a first transistor (Fig. 1: 134) comprising a first gate terminal (Fig. 1: 134 comprising a first gate terminal coupled to WL1), a second transistor (Fig. 1: 136) comprising, a second gate terminal (Fig. 1: 136 comprising a gate terminal coupled to WL1), a first word line coupled to at least the first transistor or the second transistor (Fig. 1: WL1 coupled to 134 and 136), and a second memory cell coupled to a second selection transistor comprising a third transistor having a third gate terminal and a fourth transistor having a fourth gate terminal (Fig. 1: second memory cell 208 comprising a pair of transistor having gate terminals).
Furthermore, Roy teaches wherein the second gate terminal of the second transistor and the fourth gate terminal of the fourth transistor are coupled to each other, and are further coupled to the first word line and the first gate terminal and the third gate terminal (Fig. 1 shows first and second memory cells 202 and 208 comprising a plurality of transistor having gates coupled to word line WL1).
Since Roy, Pyo, Augustine and Lung are from the same field of endeavor, the teachings described by Roy would have been recognized in the pertinent art of Lung in combination with Augustine and Pyo.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Roy with the teachings of Lung in combination with Augustine and Pyo for the purpose of increase a transistor strength, see Roy’s page 2, par. 0022.
Response to Arguments
Applicant’s arguments with respect to claims 1-4 and 6-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825