DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed July 13, 2026.
Claims 1-4 and 6-21 are pending. Claims 10-11 are amended. Claims 1, 10 and 20 are independent.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lung et al. (U.S. 2010/0195378; hereinafter “Lung”) in view of Augustine et al. (U.S. 2024/0053987; hereinafter “Augustine”).
Regarding independent claim 1, Lung teaches a memory circuit (Fig. 1), comprising:
a first bit line (Fig. 1: 41);
a memory cell (Fig. 1:35) coupled to the first bit line (Fig. 1: 41);
a selection circuit (Fig. 1: 52/53) coupled to the memory cell (Fig. 1:35), the selection circuit (Fig. 1: 52/53) comprising:
a first transistor on a first level (Fig. 1: 52); and
a second transistor on a second level different from the first level (Fig. 1: 53);
a first word line (Fig. 1: 23a) coupled to at least the first transistor (Fig. 1: 52) or the second transistor;
a first source line (Fig. 1: 28a) coupled to at least the first transistor (Fig. 1: 52) or the second transistor;
the first transistor is configured to perform a write operation of the memory cell in response to the memory cell being configured to store a first logical value (see page 3, par. 0040), and
the second transistor is configured to perform a read operation of the memory ell, and the write operation of the memory cell in response to the memory cell being configured to store a second logical value different from the first logical value (see pages 1-2, par. 0011-0012 and page 3, par. 0038-0040).
However, Lung is silent with respect to wherein the first transistor and the second transistor are part of a complementary field-effect transistor (CFET) in a vertical configuration.
Similar to Lung, Augustine teaches a memory circuit (Fig. 13) comprising a first transistor on a first level and a second transistor on a second level different from the first level (Fig. 1).
Furthermore, Augustine teaches wherein the first transistor and the second transistor are part of a complementary field-effect transistor (CFET) in a vertical configuration (Fig. 1; see also pages 1-2, par. 0020).
Since Augustine and Lung are from the same field of endeavor, the teachings described by Augustine would have been recognized in the pertinent art of Lung.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Augustine with the teachings of Lung for the purpose of improve transistor scaling, see Augustine’s page 1, par. 0019.
Regarding claim 2, Lung in combination with Augustine teaches the limitations with respect to claim 1.
Furthermore, Lung teaches wherein the first transistor (Fig. 1: 52) comprises:
a first gate terminal coupled to the first word line (Fig. 1: 52 comprises a gate terminal coupled to 23a);
a first drain terminal coupled to a first end of the memory cell (Fig. 1: 52 comprises a drain terminal coupled to 35); and
a first source terminal coupled to the first source line (Fig. 1: 52 comprises a source terminal coupled to 28a); and
the second transistor (Fig. 1: 53) comprises:
a second gate terminal (Fig. 1: 53 comprises a gate terminal coupled to 23b);
a second drain terminal coupled to the first drain terminal and the first end of the memory cell (Fig. 1: 53 comprises a drain terminal coupled to 35 and drain terminal of 52); and
a second source terminal (Fig. 1: 53 comprises a source terminal coupled to 28b).
Regarding claim 3, Lung in combination with Augustine teaches the limitations with respect to claim 1.
Furthermore, Lung teaches a second word line coupled to the second gate terminal of the second transistor (Fig. 1: 53 comprises a gate terminal coupled to 23b); and
a second source line coupled to the second source terminal of the second transistor (Fig. 1: 53 comprises a source terminal coupled to 28b).
Regarding claim 4, Lung in combination with Augustine teaches the limitations with respect to claim 3.
Furthermore, Augustine teaches wherein the first transistor is a first type (Fig. 1: PMOS), the second transistor is a second type (Fig. 1: NMOS) different from the first type, and the second transistor is on the second level (Fig. 1 shows NMOS transistor on top of the PMOS transistor).
Regarding independent claim 20, Lung teaches a method of operating a memory circuit (see page 1, par. 0004), the method comprising:
performing a write operation of a memory cell, the performing the write operation of the memory cell comprises (“set” and “reset” operations, see pages 1-2, par. 0012):
storing a first logical value in the memory cell by a first transistor of a selection circuit, the selection circuit being coupled to the memory cell (see page 3, par. 0038); or
storing a second logical value in the memory cell by a second transistor of the selection circuit, the second logical value being different from the first logical value (see page 3, par. 0040); and
performing a read operation of the memory cell by the first transistor of the selection circuit (see page 3, par. 0039).
However, Lung is silent with respect to wherein the first transistor is on a first level and the second transistor is on a second level different from the first level, and the first transistor and the second transistor are part of a complementary field-effect transistor (CFET) in a vertical configuration.
Augustine teaches wherein the first transistor is on a first level and the second transistor is on a second level different from the first level, and the first transistor and the second transistor are part of a complementary field-effect transistor (CFET) in a vertical configuration (Fig. 1; see also pages 1-2, par. 0020).
Since Augustine and Lung are from the same field of endeavor, the teachings described by Augustine would have been recognized in the pertinent art of Lung.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Augustine with the teachings of Lung for the purpose of improve transistor scaling, see Augustine’s page 1, par. 0019.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lung and Augustine as applied to claim 2 above, and further in view of Pyo et al. (U.S. 2018/0122467; hereinafter “Pyo”).
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Regarding claim 6, Lung in combination with Augustine teaches the limitations with respect to claim 2.
Furthermore, Lung teaches a second word line coupled to the second gate terminal of the second transistor (Fig. 1: 23b coupled to the gate of 53).
However, the combination is silent with respect to wherein the second source terminal of the second transistor is coupled to the first source line.
Similar to Lung in combination with Augustine, Pyo teaches a memory circuit (Fig. 1) comprising a first bit line (Fig. 9: BL), a memory cell coupled to the first bit line (Fig. 9: MTJ coupled to BL), and a selection circuit (Fig. 9: TG) coupled to the memory cell (Fig. 9: MTJ), the selection circuit (Fig. 9: TG) comprising a first transistor (Fig. 9: PMOS) and a second transistor (Fig. 9: NMOS), the first transistor (Fig. 9: PMOS) comprises a first gate terminal (Fig. 11: gate terminal of the PMOS coupled to wWL<1>), a first drain terminal (Fig. 11: drain terminal of the PMOS coupled to MTJ), and a first source terminal (Fig. 11: source terminal of the PMOS coupled to SL<X>), the second transistor (Fig. 9: NMOS) comprises a second gate terminal (Fig. 11: gate terminal of the NMOS coupled to WL<1>), a second drain terminal (Fig. 11: drain terminal of the NMOS coupled to MTJ), and a second source terminal (Fig. 11: source terminal of the NMOS coupled to SL<X>).
Furthermore, Pyo teaches wherein the second source terminal of the second transistor is coupled to the first source line (Fig. 11: source terminal of the NMOS coupled to SL<X>).
Since Pyo, Augustine and Lung are from the same field of endeavor, the teachings described by Pyo would have been recognized in the pertinent art of Lung in combination with Augustine.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Pyo with the teachings of Lung in combination with Augustine for the purpose of improve reliability and operating method and provide a reduce chip size, see Pyo’s page 1, par. 0005.
Regarding claim 7, Lung in combination with Augustine and Pyo teaches the limitations with respect to claim 6.
Furthermore, Augustine teaches wherein the first transistor is a first type (Fig. 1: PMOS), the second transistor is a second type (Fig. 1: NMOS) different from the first type, and the second transistor is on the second level (Fig. 1 shows NMOS transistor on top of the PMOS transistor).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lung and Augustine as applied to claim 2 above, and further in view of Roy et al. (U.S. 2020/0211643; hereinafter “Roy”).
Regarding claim 8, Lung in combination with Augustine teaches the limitations with respect to claim 2.
Furthermore, Lung teaches a second source line coupled to the second source terminal of the second transistor (Fig. 1: 28b coupled to second source terminal of 53).
However, the combination is silent with respect to wherein the second gate terminal of the transistor is coupled to the first word line and the first gate terminal.
Similar to Lung in combination with Augustine, Roy teaches a memory circuit (Fig. 1) comprising a memory cell (Fig. 1: 138), a selection circuit (Fig. 1: 134/136) coupled to the memory cell (Fig. 1: 138), the selection circuit (Fig. 1: 134/136) comprising, a first transistor (Fig. 1: 134) comprising a first gate terminal (Fig. 1: 134 comprising a first gate terminal coupled to WL1), a first drain terminal (Fig. 1: 134 comprising a first drain terminal coupled to 138) and a first source terminal (Fig. 1: 134 comprising a source terminal coupled to SL1), a second transistor (Fig. 1: 136) comprising, a second gate terminal (Fig. 1: 136 comprising a gate terminal coupled to WL1), a second drain terminal (Fig. 1: 136 comprising a drain terminal coupled to 138), and a second source terminal (Fig. 1: 136 comprising a second source terminal coupled to INTsense1), and a first word line coupled to at least the first transistor or the second transistor (Fig. 1: WL1 coupled to 134 and 136).
Furthermore, Roy teaches wherein the second gate terminal of the transistor is coupled to the first word line and the first gate terminal (Fig. 1: WL1 coupled to 134 and 136).
Since Roy, Augustine and Lung are from the same field of endeavor, the teachings described by Roy would have been recognized in the pertinent art of Lung in combination with Augustine.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Roy with the teachings of Lung in combination with Augustine for the purpose of increase a transistor strength, see Roy’s page 2, par. 0022.
Regarding claim 9, Lung in combination with Augustine and Roy teaches the limitations with respect to claim 8.
Furthermore, Augustine teaches wherein the first transistor is a first type (Fig. 1: PMOS), the second transistor is a second type (Fig. 1: NMOS) different from the first type, and the second transistor is on the second level (Fig. 1 shows NMOS transistor on top of the PMOS transistor).
Response to Arguments
Applicant's arguments filed with respect to claim 1 have been fully considered but they are not persuasive.
With respect to independent claim 1, Applicant asserts that the combination of Augustine and Lung is not proper because the benefits of Augustine’s CFET configuration will not be achieved since the first and second access transistors of Lung are both N-type transistor and the Office has not provided any reason why one of ordinary skill in the art would replace the first and second N-type access transistors of Lung with complementary (N-type and P-type) access transistors, see Applicant’s Remarks page 11. This particular remark is not considered persuasive.
MPEP cites different rationales to support a conclusion of obviousness than can be relies upon by Office personnel, for example, the rationale used in the applied rejection: MPEP 2143(I)(G) “Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.” A teaching, suggestion, or motivation to combine references that is found in the prior art is an appropriate rationale for determining obviousness.
The teaching, suggestion or motivation test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Further, the teaching, suggestion, or motivation test is flexible and an explicit suggestion to combine the prior art is not necessary, see MPEP 2143(I)(G).
Furthermore, Applicant asserts that the combination is in error because Augustine is directed to SRAM cells which is a volatile memory and Lung is directed to phase change memory which is a non-volatile memory, therefore these features are architecturally incompatible, see Applicant’s Remark page 11. This particular remark is not considered.
Claim 1 does not require the recited memory to be either volatile or non-volatile, nor does the claim otherwise distinguish between these types of memory. Accordingly, Applicant’s argument is not commensurate in scope with the claim and relies on limitations that are not recited therein.
Moreover, Augustine teaches that the memory may includes volatile and non-volatile memory and the rejection does not rely merely on both references using the general term “memory”. Rather, the references disclose the relevant claimed features, including a memory arrangement comprising two transistors. Although the references may employ different types of memory, the claim does not recite any structural, operational, or functional limitation that excludes either disclosed memory type or requires the distinguishing characteristics identified by Applicant.
For the above reasons, the previously applied rejection is considered proper and maintained.
The other claims were argued for substantially the same reasons as claim 1, and the arguments are not persuasive for the same reasons.
Allowable Subject Matter
Claims 10-19 and 21 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to independent claim 10, there is no teaching or suggestion in the prior art of record to provide the recited CFET coupled to the first source line, in combination with the other limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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