Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment & Argument
The amendment filed on 04/20/2026 under 37 CFR 1.131 has been considered but is ineffective to overcome the cited references below.
Applicant argues that the field plate of prior art Chiu comprising metal is part of the back-end-process (BEOL) and field plate of prior art Cho is part of the gate and front-end process (FEOL). Therefore, the combination is inoperable.
The examiner would like to note that the specification of Chiu does not disclose anywhere that the field plate is part of back-end-process (BEOL) and the applicant has not cited any relevant portion of the specification. Applicant’s argument cannot be construed as evidence. Furthermore, it is known in the art that the field plate is part of the gate structure which is a front-end process (FEOL) (Note the specification recites “At this time, a metal-insulator-polysilicon (MIP) structure is consisted of the polysilicon layer, the metal electrode and the insulating layer which is between the polysilicon layer and the metal electrode. It generates an effect of lateral field plate when the metal electrode extends to directly above the isolation structure”) to optimize the electric field at the gate edge near the drain, thereby increasing the device’ s breakdown voltage and improving overall reliability in high voltage power devices. Accordingly, the combination of Chiu and Cho is operable.
DETAILED ACTION
This action is responsive to application No. 18337396 filed on 06/19/2023.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of claims 1-11 in the reply filed on 10/31/2025 is acknowledged.
Claim 6 has been cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US 9,853,145) in view of Cho (US 2022/0336658).
Regarding independent claim 1, Chiu et al. teach a semiconductor device, comprising:
a gate structure (Fig. 7, element 108, Col. 3, line 64), located on a substrate (Fig. 7, element 102, Col. 3, line 22);
a first doped region (Fig. 7, element 114, Col. 5, line 22) and a second doped region (Fig. 7, element 116, Col. 5, lines 22-23), located at two sides of the gate structure;
an isolation structure (Fig. 7, element 104, Col. 5, line 24), located in the substrate between the first doped region and the second doped region, and separated from the gate structure by a non-zero distance (Fig. 7);
an insulating layer (Fig. 7, element 118, Col. 5, lines 37-38), extending continuously from a portion of a top surface of the gate structure to a portion of a top surface of the isolation structure; and
a field plate (Fig. 7, element 122, specification discloses “At this time, a metal-insulator-polysilicon (MIP) structure is consisted of the polysilicon layer, the metal electrode and the insulating layer which is between the polysilicon layer and the metal electrode. It generates an effect of lateral field plate when the metal electrode extends to directly above the isolation structure”), located on the insulating layer,
wherein the field plate and the gate structure are equipotential (Fig. 7 discloses field plate 122 and gate electrode 108b connected through interconnect 126 & 128 analogous to the instant application).
Chiu et al. do not explicitly disclose wherein the field plate comprises a semiconductor.
Before the effective filling date of the invention it would have been obvious to one having ordinary skill in the art to select a field plate comprising polysilicon as shown by Cho in paragraph 0057, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Regarding claim 2, Chiu et al. teach wherein a thickness of the insulating layer is greater (Fig. 7) than a thickness of a gate dielectric layer (Fig. 7, element 108a, Col. 3, lines 66-67) of the gate structure.
Regarding claim 4, Chiu et al. teach wherein the insulating layer is a salicide block layer (Col. 5, lines 40-43 disclose silicon oxide which is the same material as the instant application).
Regarding claim 5, Chiu et al. teach wherein the salicide block layer comprises silicon oxide (Col. 5, lines 40-43 disclose silicon oxide which is the same material as the instant application).
Regarding claim 7, Chiu et al. modified by Cho teach wherein the field plate comprises undoped polysilicon (paragraph 0057 of Cho).
Regarding claim 8, Chiu et al. teach all of the limitations as discussed above.
Chiu et al. do not explicitly disclose further comprising a plurality of metal silicide layers, located on a top surface of the first doped region, a top surface of the second doped region, a top surface of the field plate, and a top surface of a gate conductive layer of the gate structure uncovered by the insulating layer, respectively.
Cho teaches a LDMOS device comprising a plurality of metal silicide layers (Fig. 12, element 180, paragraph 0064), located on a top surface of the first doped region (Fig. 12, element 150, paragraph 0053), a top surface of the second doped region (Fig. 12, element 140, paragraph 0051), a top surface of the field plate (Fig. 12, element 173, paragraph 0057), and a top surface of a gate conductive layer (Fig. 12, element 163, paragraph 0055) of the gate structure uncovered by the insulating layer (Fig. 12, element 171), respectively.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Chiu et al. according to the teachings of Cho with the motivation to reduce contact resistance (paragraph 0064).
Regarding claim 9, Chiu et al. modified by Cho teach further comprising an interconnect structure electrically connected to the field plate and the gate conductive layer of the gate structure (Fig. 7 of Chiu discloses interconnect structures 126 electrically connected to the field plate and the gate conductive layer of the gate structure).
Regarding claim 10, Chiu et al. modified by Cho teach wherein the interconnect structure comprises: a first contact (Fig. 7, element 126), electrically connected to the field plate; a second contact (Fig. 7, element 126), electrically connected to the gate conductive layer of the gate structure; and a conductive line (Fig. 7, element 128), connected to the first contact and the second contact.
Regarding claim 11, Chiu et al. modified by Cho teach wherein the first contact is electrically connected to the field plate through one of the plurality of metal silicide layers, and the second contact is electrically connected to the gate conductive layer through another of the plurality of metal silicide layers (Fig. 7 of Chiu & Fig. 12 of Cho disclose the first contact 126 of Chiu connected to the field plate 122 of Chiu through one of the plurality of metal silicide layers 180 of Cho and the second contact 126 of Chiu is electrically connected to the gate conductive layer 180b of Chiu through another of the plurality of metal silicide layers 180 of Cho).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US 9,853,145) in view of Cho (US 2022/0336658) and further in view of Su et al. (US 2020/0013888).
Regarding claim 3, Chiu et al. modified by Cho teach all of the limitations as discussed above.
Chiu et al. modified by Cho do not explicitly disclose wherein a width of the isolation structure covered by the insulating layer is greater than 30% to 80% of a top width of the isolation structure.
Su et al. teach an LDMOS comprising wherein a width of the isolation structure (Fig. 2, element 107b, paragraph 0027) covered by the insulating layer (Fig. 2, element 110, paragraph 0019) is greater than 30% to 80% of a top width of the isolation structure (Fig. 2, it would have been obvious to one or ordinary skill in the art before the effective filling date of the invention to vary the width of the insulating layer with the motivation to optimize the separation between the field plate 122 and the drift region 105 (paragraph 0019). Therefore, the width is an art recognized variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the width as the width has identified the area as a result-effective variable. Furthermore, the applicant has not presented persuasive evidence that the claimed area is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed width).
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/Primary Examiner, Art Unit 2813
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