DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 14-20 in the reply filed on 10/27/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 14-17 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YEN [US 2021/0366911].
With respect to claim 14, Yen (fig. 2M-1) discloses a DRAM, comprising:
a substrate (102, pp [0014]) comprising an active region (104a, 104b, pp [0023]), wherein the active region comprises two active pillars with neck channel regions(138, pp [0038]) , and a shallow recess (136, pp [0030]) is formed on surfaces of each of the neck channel regions;
a buried bit line (106, pp [0026]) between the active pillars, and a top surface of the buried bit line is lower than a top surface of the substrate;
an insulating structure (110, pp [0036]) over the buried bit line to separate the active pillars of the active regions; and
a plurality of buried word lines (112, pp [0031]), wherein each of the buried word lines is contained in the shallow recess to surround the neck channel region of each of the active pillars, and the insulating structure is between the buried word lines.
With respect to claim 15, Yen (fig. 2M-1) discloses wherein the buried word line comprises: a gate dielectric layer (112a, pp [0031]) formed on surfaces of the neck channel region of each of the active pillars; a barrier layer (112b, pp [0031]) formed over the gate dielectric layer; and a gate electrode layer (112c, pp [0031]) formed over the barrier layer.
With respect to claim 16, Yen (fig. 2M-1) discloses wherein the gate electrode layer (112c, pp [0031]) is embedded in a recess formed on a surface of the barrier layer (112b, pp [0031]).
With respect to claim 17, Yen (fig. 2M-1) discloses further comprising: a bit line contact structure (108, pp [0025]) disposed between the buried bit line and the substrate; a capacitor contact structure (142, pp [0039]) formed over top portions of each of the active pillars; and a capacitor (116, pp [0042]) formed over the capacitor contact structure.
With respect to claim 19, Yen (fig. 2M-2) discloses wherein the active region (104a, 104b, pp [0023]) has a rounded corner.
With respect to claim 20, Yen (fig. 2M-2) discloses further comprising: an isolation structure (110a, pp [0021]) to define the active region, and the isolation structure has a width less than a width of the insulating structure (110, pp [0036]).
Allowable Subject Matter
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V PHAM whose telephone number is (571)272-1715. The examiner can normally be reached M-F 8:30a.m-10:00p.m.
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/HOAI V PHAM/Primary Examiner, Art Unit 2892