DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/20/2023 and 12/12/2023 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 16 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 13 of U.S. Patent No. 11,721,663. Although the claims at issue are not identical, they are not patentably distinct from each other because Claim 16 of the present application encompasses claim 13 of US patent 11,721,663
18/338,107
US patent 11,721,663
16. A method comprising: bonding a front side of a wafer to a carrier;
13. A method comprising: bonding a front side of a first wafer to a first carrier; with the first wafer bonding to the first carrier, thinning a semiconductor substrate of the first wafer to reveal a plurality of through-vias in the first wafer;
forming a plurality of bond pads on a backside of the wafer; forming a dielectric layer on the backside of the wafer, wherein the plurality of bond pads are in the dielectric layer;
forming a first plurality of bond pads and a first dielectric layer on a backside of the first wafer;
bonding a plurality of chips to the plurality of bond pads and the dielectric layer;
bonding a plurality of chips to the first plurality of bond pads and the first dielectric layer
through hybrid bonding;
de-bonding the carrier from the wafer and the plurality of chips; and
de-bonding the first carrier from the first wafer and the plurality of chips,
wherein in the de-bonding, a blank silicon layer in the first carrier is removed from the first wafer, and a surface layer in the first carrier is left attached to the first wafer;
forming electrical connectors on the front side of the wafer,
and forming electrical connectors on the front side of the first wafer,
wherein the electrical connectors are electrically connected to the plurality of chips through a plurality of through-vias in the wafer.
wherein the electrical connectors are electrically connected to the plurality of through-vias.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation "the plurality of gap-filling region" in line 5. The examiner suggests “the plurality of gap-filling regions”. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Yu (US 2018/0158749)
Regarding claim 12, Yu (749) discloses:
a method comprising: forming gap-filling regions (fig 9:257;[para 0049]) to fill gaps (fig 4-9;[para 0044]) between a plurality of chips (fig 9:253;[para 0055]) to form a reconstructed wafer (fig 9:261;[para 0049]), wherein the reconstructed wafer (fig 9:261;[para 0055]) is attached to a device wafer (fig 9:111;[para 0055]), and the device wafer (fig 9:111;[para 0037]) comprises a semiconductor substrate (fig 1:115;[para 0020]) extending to all edges of the device wafer (fig 1,2:111;[para 0028]); thinning (fig 2,3 ;[para 0037]) the semiconductor substrate (fig 2:115;[para 0037]) to reveal a plurality of through-vias (fig 1,3:120;[para 0021]) in the semiconductor substrate (fig 3:115;[para 0037]); forming a plurality of electrical connectors (fig 22:985;[para 0077]) electrically connecting to the plurality of chips (fig 9,22:253;[para 0049]) through the plurality of through-vias (fig 22:120;[para 0022]); and sawing through the device wafer (fig 23:111;[para 0079]) and the gap-filling regions (fig 9:257;[para 0049]) to form a plurality of packages (fig 24:102a,b;[para 0079]).
Regarding claim 13, Yu (749) discloses the method of claim 12.
bonding the reconstructed wafer to a carrier (fig 20:206;[para 0075]), wherein at a time after the sawing (fig 23 ;[0079]), some pieces (fig 24:206a,b; ;[para 0079]) of the carrier (fig 22:206; ;[para 0075]) remain as parts of the plurality of packages (fig 24 ;[para 0;[para 0079]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 through 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0158749) in view of Yu (2019/0244947)
Regarding claim 1, Yu (749) discloses a method comprising: bonding a wafer (fig 1:110; para 0020]) to a first carrier (fig 2:205;[para 0;[para 0033]), wherein the wafer (fig 1:110;[para 0;[para 0020]) comprises a semiconductor substrate (fig 1:115;[para 0;[para 0020]); […]bonding a first plurality of chips (fig 9:253;[para 0;[para 0049]) over the wafer (fig 4-9:111, thinned wafer 110;[para 0037,0038]), with gaps located between the first plurality of chips (fig 4-9:253;[para 0038]),
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performing a gap-filling process to form gap-filling regions (fig 9:257;[para 0049]) in the gaps,[…] bonding a second carrier (fig 20:206;[para 0075]) onto the first plurality of chips (fig 20:253;[para 0075]) and the gap-filling regions (fig 20:257;[para 0075]); and de-bonding the first carrier (fig 20:205;[para 0075]) from the wafer (fig 22:111;[para 0076]).
Yu (749) does not teach forming a first bonding pad and a second bonding pad.
Yu (947) teaches
forming a first bond pad (fig 24:207;[para 0041]) and a second bond pad (fig 24:207;[para 0041]) on a surface of the wafer (fig 24:201;[para 0026]), wherein the first bond pad (fig 3:207;[para 0041]) and the second bond pad (fig 24:207;[para 0041]) are on an opposite side of the semiconductor substrate (fig 25:201;[para 0026]) than the first carrier (fig 26:601,603,605;[para 0053]); wherein the first bond pad (fig 26:207;[para 0041]) is bonded to a third bond pad (fig 2,26:111;[para 0037]) in one of the first plurality of chips (fig 25:105;[para 0025]); wherein the second bond pad (fig 28:207;[para 0126]) physically contacts one of the gap-filling regions (fig 28:801;[para 0126]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the process taught by Yu (749) by forming bonding pads in order to facilitate the connection between the wafer and the chips stacked thereon, further by providing bond pads in contact with the gap fill material it enables forming through fill vias as is taught by Yu (947).
Regarding claim 2, Yu (749) in view of Yu (947) discloses the method of claim 1.
Yu (749) teaches removing a part (fig 23) of the second carrier (fig 21:206;[para 0076]) from the wafer (fig 22,23:111;[para 0079]), wherein after the part of the second carrier (fig 22,23:206;[para 0079] is removed (fig 23:270;[para 0050]), a portion (fig 23:206a,206b;[para 0079]) of the second carrier (fig 22:206) remains to be bonded to the first plurality of chips (fig 23:253;[para 0079]).
Regarding claim 3, Yu (749) in view of Yu (947) discloses the method of claim 2.
Yu (749) teaches the second carrier (fig 22:206; ;[para 0033,0075]) comprises a silicon substrate and a surface layer (fig 22:211;[para 0075]) on the silicon substrate (fig 23:206;[para 0075]), wherein the part of the second carrier (fig 23:206;[para 0079]) that is removed (fig 23:270) comprises the silicon substrate (fig 22,23), and wherein the surface layer (fig 22,23:211;[para 0079]) remains to be bonded to the first plurality of chips (fig 23:253;[para 0049]).
Regarding claim 4, Yu (749) in view of Yu (947) teaches the method of claim 2.
Yu (749) teaches the portion of the second carrier (fig 23:206a;[para 0079]) that remains to be bonded to the first plurality of chips (fig 23:253;[para 0049]) comprises a […] dielectric (glass) layer (Yu states that carrier 206 comprises similar materials to carrier 205;[para 0033,0075]).
Yu (749) does not teach a silicon containing dielectric.
Yu (947) teaches wherein the carrier (fig 26:601,603,605 ;[para 0053]) comprises a silicon-containing dielectric layer (;[para 0053]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the second carrier of a silicon containing dielectric due to the material’s chemical and physical stability enabling it to integrate into the process.
Regarding claim 5, Yu (749) in view of Yu (947) teaches the method of claim 2.
Yu (749) teaches performing a singulation process (fig 22,23;[para 0079]) to separate the first plurality of chips (fig 23:253;[para 0049]) and additional chips in the wafer (fig 23:111;[para 0077]) into a plurality of packages (fig 24:102a,102b;[para 0079]), wherein each of the plurality of packages (fig 24:102a,102b;[para 0079]) comprises a piece of the portion of the second carrier (fig 24:206a,b;[para 0079]).
Regarding claim 6, Yu (749) in view of Yu (947) teaches the method of claim 5.
Yu (749) teaches at a time after the singulation process (fig 23;[para 0079]) has been performed, the portion of the second carrier (fig 23:206a,206b;[para 0079]) is an outmost layer of the plurality of packages (fig 24:102a,102b;[para 0079]).
Regarding claim 7, Yu (749) in view of Yu (947) teaches the method of claim 1.
Yu (749) teaches a front side of the wafer (fig 1:110;[para 0020]) is bonded to the first carrier (fig 2:205;[para 0034,0035]), and wherein the method further comprises: polishing the semiconductor substrate of the wafer (fig 3:110;[para 0037]) to reveal a plurality of through-vias (fig 3:120;[para 0021]) in the semiconductor substrate (fig 3:115;[para 0037]) […].
Yu (947), wherein the first bond pad (fig 28:207;[para 0126]) and the second bond pad (fig 28:207;[para 0126]) are electrically connected to the [metalization] (;[para 0038])
It would have been obvious to one or ordinary skill in the art before the effective filing date of the claimed invention for the first bond pad and the second bond pad (207) taught by Yu (947) to be electrically connected to the plurality of through-vias taught by Yu (749) in order to facilitate connection of the via to the vertically adjacent chips thereby enabling the package to supply voltage and IO to the packaged die.
Regarding claim 8, Yu (749) in view of Yu (947) teaches the method of claim 1.
Yu (749) teaches the bonding the first plurality of chips (fig 4-9:253;[para 0049]) over the wafer (fig 3:110,111;[para 0037]) comprises dielectric-to-dielectric bonding and metal-to-metal bonding (fig 4-9;[para 0046,0049]).
Regarding claim 9, Yu (749) in view of Yu (947) teaches the method of claim 1.
Yu (749) teaches forming electrical connectors (fig 22:985;[para 0077]) on the wafer (fig 22:111;[para 0077]), wherein the electrical connectors (fig 22:985;[para 0077]) are electrically connected to the first plurality of chips (fig 22:253;[para 0049]) through a plurality of through-vias (120) in the wafer (fig 24:111;[para 0046]).
Regarding claim 10, Yu (749) in view of Yu (947) teaches the method of claim 1.
Yu (749) teaches the gap-filling process (fig 5:216;[para 0044]) comprises depositing silicon oxide (;[para 0044) (fig 5)).
Regarding claim 11, Yu (749) in view of Yu (947) teaches the method of claim 1.
Yu (749) teaches before the second carrier (fig 20:206;[para 0075]) is bonded onto the first plurality of chips (fig 20:253;[para 0075]) and the gap-filling regions (fig 5:216;[para 0044]), depositing an additional dielectric layer (fig 20:211;[para 0075]) on the first plurality of chips (fig 15:253;[para 0049]) and the gap-filling regions (fig 15:257;[para 0049]), wherein the second carrier (fig 20:206;[para 0075]) is bonded to the additional dielectric layer (fig 20:211;[para 0075]).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0158749) as applied to claim 12 and further in view of Yu (2019/0244947)
Regarding claim 14, Yu (749) teaches the elements of claim 12 above.
Yu (749) teaches before the plurality of electrical connectors (fig 22:985;[para 0075]) are formed, bonding the reconstructed wafer (fig 9;[para 0049]) to a carrier (fig 20:206;[para 0075]).
Yu (749) does not teach thinning the carrier.
and after the plurality of electrical connectors (fig 10,32:1017;[para 0082]) are formed (fig 32;[para 0080]), thinning the carrier (fig 11:601,603,605;[para 0086]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to thin the carrier taught by Yu (749) as is taught by Yu (947) in order to reduce the size of the packaged method and facilitate heat removal
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0158749) as applied to claim 12 and further in view of Lee (US 2021/0028146)
Regarding claim 15.
Yu (749) teaches the elements of claim 12 above.
Yu (749) does not teach wafer to wafer bonding
Lee teaches at a time after the gap-filling regions (fig 14:600;[para 0089]) are formed, bonding the reconstructed wafer (fig 15:500,600;[para 0092]) to the device wafer (fig 15:200;[para 0083]) through wafer-on-wafer bonding (fig 15;[para 0092]).
It would have been obvious to one of ordinary skill in the art to one of ordinary skill in the art before the effective filing date of the claimed invention to perform a wafer to wafer bonding process in order to bond many devices simultaneously combing placement into a single step in order to speed up the process.
Claim(s) 16, 17, 18, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0158749) in view of Yu (2019/0244947)
Regarding claim 16.
Yu (749) a method comprising: bonding a front side of a wafer (fig 1:110;[para 0020]) to a carrier (fig 2:205;[para 003]); bonding a plurality of chips (fig 4-9:253;[para 0049]) to the [wafer] (fig 4-9;[para 0040,0048]); de-bonding the carrier (fig 20,22:205;[para 0076]) from the wafer (fig 22:111;[para 0076]) and the plurality of chips (fig 22:253;[para 0076]); and forming electrical connectors (fig 22:120,985;[para 0076]) on the front side of the wafer (fig 22:111;[para 0076]), wherein the electrical connectors (fig 22:120,985;[para 0076]) are electrically connected to the plurality of chips (fig 22:253;[para 0049]) through a plurality of through-vias (fig 22:120;[para 0021]) in the wafer (fig 22:111;[para 0077])
Yu (749) does not teach forming a plurality of bond pads on the backside of the wafer.
Yu (947) a method comprising: a wafer (fig 2:201;[para 0036]), forming a plurality of bond pads (fig 2:207;[para 0038]) on a side of the wafer (fig 2:201;[para 0038]); forming a dielectric layer (fig 2:205;[para 0038]) on the side of the wafer (fig 2:201;[para 0036]), wherein the plurality of bond pads (fig 2:207;[para 0038]) are in the dielectric layer (fig 2:205;[para 0038]); bonding a chip (fig 2:105) to the plurality of bond pads (fig 2:207) and the dielectric layer (fig 2:205) (;[para 0041]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the process taught by Yu (749) by forming bonding pads in order to facilitate the connection between the wafer and the chips stacked thereon as is taught by Yu (947).
Regarding claim 17, discloses Yu (749) in view of Yu (947) teaches the method of claim 16.
Yu (749) teaches wherein in the de-bonding (fig 20,22;[para 0076]), a blank silicon layer (;[para 0033]) in the carrier (fig 20:205;[para 0076]) is removed from the wafer (fig 22:111;[para 0076]), and a surface dielectric layer (fig 1,22:140;[para 0032]) in the carrier (fig 20:205;[para 0076]) is left attached to the wafer (fig 22:111;[para 0076]), and wherein the electrical connectors (fig 22:120,985) penetrate through the surface dielectric layer (fig 1,22:140;[para 0077]).
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Regarding claim 18, Yu (749) in view of Yu (947) teaches the method of claim 16
Yu (947) teaches in a same process for forming the plurality of bond pads (fig 2,3:207;[para 0037]), forming a plurality of conductive features (fig 2,3;[para 0037]), wherein the plurality of conductive features are in the dielectric layer (fig 2,3:205;[para 0037,0038]);
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and forming a plurality of gap-filling regions (fig 28:801;[para 0126]) between the plurality of chips (fig 28:105;[para 0126]), wherein the plurality of gap-filling region (fig 28:810;[para 0126]) physically contact the plurality of conductive features (fig 28:207;[para 0126]).
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Regarding claim 19, Yu (749) in view of Yu (947) teaches the method of claim 16.
Yu (749) teaches the wafer (fig 2:110;[para 0033]) is bonded to the carrier (fig 2:205;[para 0033]) through fusion bonding (fig 2;[;[para 0035], insulator to insulator).
Regarding claim 20
Yu (749) in view of Yu (947) teaches the method of claim 16.
Yu (749) teaches performing a singulation process (fig 23: ;[para 0079], wherein the plurality of chips and device dies in the wafer are sawed (fig 23:270;[para 0079]) into a plurality of packages (fig 24:206a,206b;[para 0079]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 January 16, 2026