DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: claims 1 through 20 rejected
Present action: claims 1,3-13,15-16 and 18-23 rejected
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1, 3, 5, 6, 7, 8, 9, 10, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0158749) in view of Yu (US 2019/0244947)
Regarding claim 1.
Yu (749) teaches:
A method comprising: bonding a wafer (fig 1:110; [para 0020]) to a first carrier (fig 2:205; [para 0033]), wherein the wafer (fig 1:110; [para 0020]) comprises a semiconductor substrate (fig 1:115; [para 0020]);
;
bonding a first plurality of chips (fig 9:253; [para 0038]) over the wafer (fig 1:110; [para 0020]), with gaps (fig 4-9) located between the first plurality of chips (fig 9:253; [para 0038]), ;
performing a gap-filling process to form gap-filling regions (fig 9:257; [para 0049]) in the gaps (fig 4-9), ;
bonding a second carrier (fig 20:211,206; [para 0075]) onto the first plurality of chips (fig 9:253; [para 0038]) and the gap-filling regions (fig 9:257; [para 0049]);
de-bonding the first carrier (fig 20,22:205; [para 0075]) from the wafer (fig 1:110; [para 0020]);
and de-bonding ([para 0079]) a first part (fig 22,23:206a,206b; [para 0079]) of the second carrier from the wafer (fig 20:211,206; [para 0075]),
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Yu (749) does not teach forming first and second bonding pads or debonding part of the second carrier.
Yu (947) teaches:
forming a first bond pad (fig 24:207; [para 0041]) and a second bond pad (fig 24:207; [para 0041]) on a surface of the wafer (fig 24:201; [para 0025]), wherein the first bond pad (fig 24:207; [para 0041]) and the second bond pad (fig 24:207;0041]) are on an opposite side of the semiconductor substrate (fig 25:201; [para 0026]) than the first carrier (fig 26:601,603,605; [para 0053]);
wherein the first bond pad (fig 24:207; [para 0041]) is bonded to a third bond pad (fig 2,26:111; [para 0037]) in one of the first plurality of chips (fig 25,26:105; [para 0025]);
wherein the second bond pad (fig 24,28:207; [para 0041]) physically contacts one of the gap-filling regions (fig 28:801; [para 0126]);
after the first part of the carrier (fig 11:601; [para 0085]) is removed, a second part (fig 11:605; [para 0085]) of the carrier (fig 6,10:601,602,605; [para 0053]) remains to be joined to the first plurality of chips (fig 25,26:105; [para 0025]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the process taught by Yu (749) by forming bonding pads in order to facilitate the connection between the wafer and the chips stacked thereon, further by providing bond pads in contact with the gap fill material it enables the formation of through fill vias as is taught by Yu (749), additionally by debonding a portion of the carrier wafer and leaving a remaining portion a dielectric layer can be used to assist in the adherence of the carrier and to provide protection for the packaged device (Yu paragraph 54, 55)
Regarding claim 3.
Yu (749) in view of Yu (947) teaches the method of claim 1, further
Yu (947) teaches:
the second carrier (fig 6:601,603,605; [para 0054]) comprises a silicon substrate (fig 6:601; [para 0053]) and a surface layer (fig 6:605; [para 0055]) on the silicon substrate (fig 6:601; [para 0053]), wherein the first part (fig 6:601; [para 0053]) of the second carrier (fig 6:601,603,605; [para 0054]) comprises the silicon substrate (fig 6:601; [para 0053]), and wherein the second part of the second carrier comprises the surface layer (fig 6:605; [para 0055]).
Regarding claim 5.
Yu (749) in view of Yu (947) teaches the method of claim 1, further
Yu (749) teaches:
performing a singulation process (fig 22,23; [para 0079]) to separate the first plurality of chips (fig 23:253; [para 0049]) and additional chips in the wafer (fig 23:111; [para 0077]) into a plurality of packages (fig 24:102a,102b; [para 0079]), wherein each of the plurality of packages comprises a piece of the second carrier (fig 23:206a,206b; [para 0079]).
Yu (947) teaches:
a second part (fig 11:605; [para 0085]) of the carrier (fig 6,10:601,602,605; [para 0053])
Regarding claim 6.
Yu (749) in view of Yu (947) teaches the method of claim 5, further
Yu (749) teaches
at a time after the singulation process has been performed (fig 23; [para 0079]),
Yu (947]) teaches
the second part (fig 11:605; [para 0085]) of the second carrier is an outmost layer of the plurality of packages (fig 11; [para 0085]).
Regarding claim 7.
Yu (749) in view of Yu (947) teaches the method of claim 1, further
Yu (749) teaches:
a front side of the wafer (fig 1:110; [para 0020]) is bonded to the first carrier (fig 2:205; [para 0034,0035]), and wherein the method further comprises: polishing the semiconductor substrate of the wafer (fig 1:110; [para 0020]) to reveal a plurality of through-vias (fig 3:120; [para 0021]) in the semiconductor substrate (fig 3:115; [para 0037]), .
Yu (947) teaches:
the first bond pad (fig 28:207; [para 0126]) and the second bond pad (fig 28:207; [para 0126]) are electrically connected to the plurality of ([para 0038]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the first bond pad and the second bond pad taught by Yu (947) to be electrically connected to the plurality of the through vias taught by Yu (749) in order to facilitate connection of the via to the vertically adjacent chips thereby enabling the package to supply voltage and IO to the package die.
Regarding claim 8.
Yu (749) in view of Yu (947) teaches the method of claim 1, further
Yu (749) teaches:
bonding the first plurality of chips (fig 4-9:253; [para 0049]) over the wafer (fig 3:110,111; [para 0037]) comprises dielectric-to-dielectric bonding and metal-to-metal bonding (fig 4-9; [para 0046,0049]).
Regarding claim 9.
Yu (749) in view of Yu (947) teaches the method of claim 1, further
Yu (749) teaches:
forming electrical connectors (fig 22:985; [para 0077])on the wafer (fig 22:111; [para 0077]), wherein the electrical connectors (fig 22:985; [para 0077]) are electrically connected to the first plurality of chips (fig 22:253; [para 0049]) through a plurality of through-vias (fig 4,24:120; [para 0022]) in the wafer (fig 22:111; [para 0077]).
Regarding claim 10.
Yu (749) in view of Yu (947) teaches the method of claim 1, further
Yu (749) teaches:
the gap-filling process (fig 4:126; [para 0026]) comprises depositing silicon oxide (fig 5; [para 0044]).
Regarding claim 11.
Yu (749) in view of Yu (947) teaches the method of claim 1, further
Yu (749) teaches:
before the second carrier (fig 20:206; [para 0075])is bonded onto the first plurality of chips (fig 20:253; [para 0075]) and the gap-filling regions (fig 15,20:257; [para 0049]), depositing an additional dielectric layer (fig 20:211; [para 0075]) on the first plurality of chips (fig 20:253; [para 0075]) and the gap-filling regions (fig 15,20:257; [para 0049]), wherein the second carrier (fig 20:206; [para 0075]) is bonded to the additional dielectric layer (fig 20:211; [para 0075]).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0158749) in view of Yu (US 2019/0244947) as applied to claim 1 and further in view of Hsu (US 2019/0103382).
Regarding claim 4.
Yu (749) in view of Yu (947) teaches the method of claim 1, above.
Yu (749) in view of Yu (947) does not teach that the second part is silicon containing.
Hsu teaches:
A carrier (fig 7a:701,703,1012; [para 0037])
the second part (fig 7a:1012; [para 0037]) of the second carrier (fig 7a:701,703,1012; [para 0037]) that remains to be bonded to the first plurality of chips (fig 7g; [para 0041]) comprises a silicon- containing dielectric layer ([para 0037]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second part comprises a silicon containing material in order control the insulating and protective properties of the layer. Further, substituting spin on glass for spin on polymer will obtain predictable results. Further, the guidance suggested by Hsu is that a silicon containing material is known to work in one field of endeavor and success is predictable to one of ordinary skill in the art. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385. MPEP 2143.I.
Claim(s) 12, 13, 21, and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0158749) in view of Yu (US 2019/0244947)
Regarding claim 12.
Yu (749) teaches:
A method comprising: forming gap-filling regions (fig 9:257; [para 0049]) to fill gaps (fig 4-9; [para 0044]) between a plurality of chips (fig 9:253; [para 0055]) to form a reconstructed wafer (fig 9:261; [para 0055]), wherein the reconstructed wafer (fig 9:261; [para 0055]) is attached to a device wafer (fig 9:111; [para 0055]), and the device wafer (fig 9:111; [para 0055]) comprises a semiconductor substrate (fig 1:115; [para 0020]) extending to all edges of the device wafer (fig 1,2:111; [para 0028]);
thinning (fig 2,3; [para 0037]) the semiconductor substrate (fig 1:115; [para 0020]) to reveal a plurality of through-vias (fig 1,3:120; [para 0021]) in the semiconductor substrate (fig 1:115; [para 0020]);
bonding the reconstructed wafer (fig 9:261; [para 0055]) to a carrier (fig 20:206; [para 0075]), ;
forming a plurality of electrical connectors (fig 22:985; [para 0077]) electrically connecting to the plurality of chips (fig 9,22:253; [para 0049]) through the plurality of through-vias (fig 22:120; [para 0022]);
de-bonding the carrier (fig 22:206; [para 0079]), ; and sawing through the device wafer (fig 23:111; [para 0079]) and the gap-filling regions (fig 9:257; [para 0049]) to form a plurality of packages (fig 24:102a,102b; [para 0079]).
Yu (749) does not teach that the carrier comprises a dielectric layer between a carrier substrate and the package structure.
Yu (947) teaches:
bonding the reconstructed wafer (fig 9:503; [para 0055]) to a carrier (fig 9:601; [para 0054]), wherein a first dielectric layer (fig 9:605; [para 0055]) is bonded between the reconstructed wafer (fig 9:503; [para 0055]) and the carrier (fig 9:601; [para 0054]);
de-bonding the carrier (fig 9,11:601; [para 0085]), wherein after the de-bonding ([para 0085]), the first dielectric layer (fig 9:605; [para 0055]) remains attached (fig 11) to the wafer
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the process taught by Yu (749) by debonding a portion of the carrier wafer and leaving a remaining portion a dielectric layer can be used to assist in the adherence of the carrier and to provide protection for the packaged device (Yu paragraph 54, 55)
Regarding claim 13.
Yu (749) in view of Yu (947) teaches the method of claim 12, further
Yu (749) teaches:
wherein at a time after the sawing, some pieces (fig 23:206a,206b; [para 0079]) remain as parts of the plurality of packages (fig 24:102a,102b; [para 0079]).
Yu (947)
some pieces of the first dielectric layer (fig 9:605; [para 0055]) remain as parts of the plurality of packages (fig 11).
Regarding claim 21.
Yu (749) in view of Yu (947) teaches the method of claim 12, further
Yu (749) teaches:
bonding the reconstructed wafer to the carrier comprises:
Yu (947) teaches:
depositing the first dielectric layer (fig 9:605; [para 0055,0067]) as a first part of the reconstructed wafer (fig 9);
and depositing a second dielectric layer (fig 7,9:701; [para 0062]) as a second part of the carrier (fig 9:601,603,605; [para 0054]), wherein the first dielectric layer (fig 9:605; [para 0055,0067]) is physically bonded to the second dielectric layer (fig 7,9:701; [para 0062,0067]).
Regarding claim 22.
Yu (749) in view of Yu (947) teaches the method of claim 21, further
Yu (749) teaches:
the plurality of packages (fig 24:102a,102b; [para 0079])
Yu (947) teaches:
package comprise first parts of the first dielectric layer (fig 9:605; [para 0055,0067]) and second parts of the second dielectric layer (fig 7,9:701; [para 0062]).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0158749) in view of Yu (US 2019/0244947) as applied to claim 13, and further in view of Lee (US 2021/0028146).
Regarding claim 15.
Yu (749) in view of Yu (947) teaches the method of claim 12 above
Yu (749) in view of Yu (947) does not teach wafer to wafer bonding
Lee teaches:
at a time after the gap-filling regions (fig 14:600; [para 0089]) are formed, bonding the reconstructed wafer (fig 15:500,600; [para 0092]) to the device wafer (fig 15:200; [para 0083]) through wafer-on-wafer bonding (fig 15; [para 0092]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform wafer to wafer bonding in order to bond many devices simultaneously thereby combining placement into a single step in order to speed up the process.
Claim(s) 16, 18, 19, 20, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2018/0158749) in view of Yu (US 2019/0244947)
Regarding claim 16.
Yu (749) teaches:
A method comprising: bonding a front side of a wafer (fig 1:110; [para 0020]) to a carrier (fig 2:205; [para 0033]); forming a plurality of bond [sites] on a backside of the wafer (fig 2:111; [para 0076]);
;
;
de-bonding the carrier (fig 20,22:205; [para 0076]) from the wafer (fig 22:111; [para 0076]) and the plurality of chips (fig 22:253; [para 0076]), wherein in the de-bonding, a blank silicon layer (fig 20,22:205; [para 0033,0076]) of the carrier (fig 2:205; [para 0076]) is de-bonded from the wafer (fig 22:111; [para 0076]), ;
and forming electrical connectors (fig 22:120,985; [para 0076]) on the front side of the wafer (fig 22:111; [para 0076]), wherein the electrical connectors (fig 22:120,985; [para 0076]) are electrically connected to the plurality of chips (fig 22:253; [para 0049]) through a plurality of through-vias (fig 22:120; [para 0021]) in the wafer (fig 22:111; [para 0077]),
Yu (749) does not teach the carrier comprises a surface dielectric layer and bond pads.
Yu (947) teaches
forming a plurality of bond pads (fig 2:207; [para 0038]) on a side of the wafer (fig 2:201; [para 0038]);
forming a dielectric layer (fig 2:207; [para 0038]) on the side of the wafer (fig 2:201; [para 0038]), wherein the plurality of bond pads (fig 2:207; [para 0038]) are in the dielectric layer (fig 2:207; [para 0038]);
bonding a plurality of chips (fig 2:101,103; [para 0035]) to the plurality of bond pads (fig 2:207; [para 0038]) and the dielectric layer (fig 2:207; [para 0038]);
and a surface dielectric layer (fig 9:605; [para 0055]) of the carrier (fig 9:601,603,605; [para 0054]) is left attached to the wafer (fig 2,11:201; [para 0038,0085]);
and wherein the electrical connectors (fig 13:1019,1017; [para 0082]) penetrate through the surface dielectric layer (fig 2:207; [para 0038]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a bonding pad and a dielectric layer on the surface of the substrate in order to facilitate the bonding process, further providing a dielectric layer, which remains with the substrate, provides a means of protection for the packaged structures (paragraph 55).
Regarding claim 18.
Yu (749) in view of Yu (947) teaches the method of claim 16, further
Yu (947) teaches:
in a same process for forming the plurality of bond pads (fig 2,3:207; [para 0037]), forming a plurality of conductive features (fig 2,3:207; [para 0037]), wherein the plurality of conductive features (fig 2,3:207; [para 0037]) are in the dielectric layer (fig 2,3:205; [para 0037,0038]);
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and forming a plurality of gap-filling regions (fig 28:801; [para 0126]) between the plurality of chips (fig 28:105; [para 0126]), wherein the plurality of gap-filling regions (fig 28:810; [para 0126]) physically contact the plurality of conductive features (fig 28:207; [para 0126]).
Regarding claim 19.
Yu (749) in view of Yu (947) teaches the method of claim 16, further
Yu (749) teaches:
the wafer (fig 2:110; [para 0033]) is bonded to the carrier (fig 2:205; [para 0033]) through fusion bonding (fig 2:insulator to insulator; [para 0035]).
Regarding claim 20.
Yu (749) in view of Yu (947) teaches the method of claim 16, further
Yu (749) teaches:
performing a singulation process (fig 23; [para 0079]), wherein the plurality of chips and device dies in the wafer are sawed (fig 3:270; [para 0079]) into a plurality of packages (fig 24:206a,206b; [para 0079]).
Regarding claim 23.
Yu (749) in view of Yu (947) teaches the method of claim 16, further
Yu (749) teaches:
before the carrier (fig 20,22:205; [para 0076]) is de-bonded from the wafer (fig 20,22:111; [para 0077]), bonding an additional carrier (fig 22:211,206; [para 0075]) on an opposite side of the wafer (fig 20,22:111; [para 0077]) than the carrier (fig 20,22:205; [para 0076]), wherein the additional carrier (fig 22:211,206; [para 0075]) comprises a substrate (fig 22:206; [para 0075]) and a first bond layer (fig 22:211; [para 0075]) that is attached to the plurality of chips (fig 2,22:101,103; [para 0035]);
de-bonding the substrate (206a,206b; [para 0079]), ; and sawing the wafer, the plurality of chips, into a plurality of packages (fig 23,24; [para 0050,0079]).
Yu (947) teaches:
A carrier (fig 6:601,603,605; [para 0053]) comprises a substrate (fig 6:601; [para 0053]), and first bond layer (fig 6:603 ; [para 0053]) bonding to a second bond layer (fig 6:605; [para 0053]) that is attached to the plurality of chips (fig 7:503; [para 0053])
De-bonding the substrate (fig 10,11:601; [para 0053]) wherein the second bond layer (fig 10,11:605; [para 0053]) remains attached to the plurality of chips (fig 6,11:605; [para 0053])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the second carrier to comprise a substrate, a first bond layer and a second bond layer in order for the second bond layer to provide protection for the structure during processing (paragraph 55)
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference combination as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The applicant argues that the prior art does not teach that the carrier substrate comprises a portion that remains with chip structure after debonding. However, Yu (US 2018/0158749) in view of Yu (US 2019/0244947) as newly applied (see above) teaches this feature (see Yu 2019/0244947 figures 6 through 11).
The applicant argues that the amendment to claim 18 overcomes the previously applied 112 2nd paragraph rejection.
The previously applied 112 2nd paragraph rejection of claim 18 is withdrawn.
The applicant argues that the amendment to claim 16 overcomes the previously applied double patenting rejection.
The previously applied double patenting rejection is withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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