DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-17, 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujikata(USPGPUB DOCUMENT: 2015/0277207, hereinafter Fujikata) in view of Yu (USPGPUB DOCUMENT: 2023/0161120, hereinafter Yu).
Re claim 1 Fujikata discloses in Fig 1 a semiconductor structure, comprising: a second electrical waveguide(111A/111B) formed of the first dielectric material(13); and a third electrical waveguide(111A/111B) formed of the first dielectric material(13), wherein the second electrical waveguide(111A/111B) and the third electrical waveguide(111A/111B) are configured to form a composite waveguide together with the first electrical waveguide for transmission of the electrical signal(270)[0083,0084].
Fujikata does not disclose a first electrical waveguide formed of a first dielectric material(13) and configured to transmit an electrical signal(270)[0083,0084]; a second electrical waveguide(111A/111B) formed of the first dielectric material(13) and disposed adjacent to a first side of the first electrical waveguide; and a third electrical waveguide(111A/111B) formed of the first dielectric material(13) and disposed adjacent to a second side of the first electrical waveguide opposite the first side,
Yu disclose in Fig 28, 33 a first electrical waveguide(21of Yu) formed of a first dielectric material[0094 of Yu] and configured to transmit an electrical signal[0094 of Yu];
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Yu to the teachings of Fujikata in order to to allows for high-speed optical signaling with power and performance enhancement [0094, Yu]. In doing so, a second electrical waveguide(111A/111B) formed of a first dielectric material[0094 of Yu] and disposed adjacent to a first side of the first electrical waveguide(203 of Yu); and a third electrical waveguide(111A/111B) formed of the formed of a first dielectric material[0094 of Yu] and disposed adjacent to a second side of the first electrical waveguide(203 of Yu) opposite the first side,
Re claim 2 Fujikata and Yu disclose the semiconductor structure of claim 1, wherein the first dielectric material(13) comprises silicon nitride.
Re claim 3 Fujikata and Yu disclose the semiconductor structure of claim 1, wherein the electrical signal(270)[0083,0084] has a frequency between about 70 gigahertz and about 100 terahertz.
Re claim 4 Fujikata and Yu disclose the semiconductor structure of claim 1, wherein a thickness of each the first electrical waveguide, the second electrical waveguide(111A/111B) and the third electrical waveguide(111A/111B) is between about 7 pm and about 10 pm.
Re claim 5 Fujikata and Yu disclose the semiconductor structure of claim 1, wherein a first width of the first electrical waveguide is greater than a second width of the second electrical waveguide(111A/111B) or the third electrical waveguide(111A/111B), and wherein a mode field diameter of the electrical signal(270)[0083,0084] is substantially covered by the first electrical waveguide.
Re claim 6 Fujikata and Yu disclose the semiconductor structure of claim 1, wherein one of the second electrical waveguide(111A/111B) and the third electrical waveguide(111A/111B) comprises a protrusion extending from the respective second or third electrical waveguide(111A/111B) and facing the first electrical waveguide.
Re claim 7 Fujikata and Yu disclose the semiconductor structure of claim 6, wherein the protrusion is connected to the first electrical waveguide.
Re claim 8 Fujikata and Yu disclose the semiconductor structure of claim 1, wherein a thickness of at least one of the first electrical waveguide, the second electrical waveguide(111A/111B) and the third electrical waveguide(111A/111B) increases from two sides to a central location of the at least one of the first electrical waveguide, the second electrical waveguide(111A/111B) and the third electrical waveguide(111A/111B).
Re claim 9 Fujikata and Yu disclose the semiconductor structure of claim 1, further comprising:a fourth electrical waveguide formed of silicon nitride and disposed adjacent to a third side of the first electrical waveguide; and a fifth electrical waveguide formed of silicon nitride and disposed adjacent to a fourth side of the first electrical waveguide opposite the third side, wherein the fourth electrical waveguide and the fifth electrical waveguide are configured to form a composite electrical waveguide together with the first, second and third electrical waveguide(111A/111B)s for the electrical signal(270)[0083,0084].
Re claim 10 Fujikata and Yu disclose the semiconductor structure of claim 1, wherein a mode field diameter of the electrical signal(270)[0083,0084] is formed in gaps between the first, second and third electrical waveguide(111A/111B)s.
Re claim 11 Fujikata and Yu disclose the semiconductor structure of claim 10, wherein a first width of the first electrical waveguide is substantially equal to a second with of the second and third electrical waveguide(111A/111B)s.
Re claim 12 Fujikata and Yu disclose the semiconductor structure of claim 11, further comprising a plurality of fourth electrical waveguides to form an array of electrical waveguides together with the first,second, and third electrical waveguide(111A/111B)s, wherein a mode field diameter is covered substantially by the first electrical waveguide.
Re claim 13 Fujikata discloses in Fig 1 a semiconductor package, comprising: a first semiconductor die(131/132) comprising a first semiconductor device configured to transmit an electrical signal(270)[0083,0084]; a second semiconductor die(131/132) adjacent to the first semiconductor die(131/132) and comprising a second semiconductor device configured to receive the electrical signal(270)[0083,0084]; the first signal path configured to transmit the electrical signal(270)[0083,0084] between the first semiconductor die(131/132) and the second semiconductor die(131/132); and a second signal path adjacent to the first signal path and comprising a plurality of second waveguides(111A/111B) formed of a second dielectric material(13), the second signal path configured to transmit an optical signal[0080] and convert the optical signal[0080] to be part of the electrical signal(270)[0083,0084].
Fujikata does not disclose a third semiconductor die adjacent to the first semiconductor die(131/132) and the second semiconductor die(131/132), the third semiconductor die comprising:a first signal path comprising a plurality of first waveguides formed of a first dielectric material(13),
Yu disclose in Fig 28, 33 the third semiconductor die(311/313/317 of Yu) comprising:a first signal path comprising a plurality of first waveguides(21of Yu) [0094 of Yu] formed of a first dielectric material [0094 of Yu]
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Yu to the teachings of Fujikata in order to to allows for high-speed optical signaling with power and performance enhancement [0094, Yu]. In doing so, a third semiconductor die (311/313/317 of Yu) adjacent to the first semiconductor die(311/313/317 of Yu) and the second semiconductor die(131/132),
Re claim 14 Fujikata and Yu disclose the semiconductor package of claim 13, wherein the first dielectric material(13) comprises silicon nitride, and the second dielectric material(13) comprises elementary silicon.
Re claim 15 Fujikata and Yu disclose the semiconductor package of claim 13, wherein the third semiconductor die further comprises: a vertical transition device electrically coupled to the first signal path and configured to transmit the electrical signal(270)[0083,0084] to the first semiconductor die(131/132) through the first signal path; and an optical device optically coupled to the second signal path and configured to transmit the optical signal[0080] to the second semiconductor die(131/132) through the second signal path.
Re claim 16 Fujikata and Yu disclose the semiconductor package of claim 13, wherein one of the first waveguides overlap the first semiconductor die(131/132) and the second semiconductor die(131/132) from a top-view perspective.
Re claim 17 Fujikata and Yu disclose the semiconductor package of claim 13, wherein the first waveguides are arranged in different layers of the third semiconductor die for transmitting the electrical signal(270)[0083,0084], wherein the second waveguides(111A/111B) are also arranged in the different layers for transmitting the optical signal[0080].
Re claim 21 Fujikata discloses in Fig 1 a semiconductor package, comprising: a first semiconductor die(131/132), comprising a first electronic device configured to transmit an electrical signal(270)[0083,0084]; a second semiconductor die(131/132), comprising a second electronic device configured to receive the electrical signal(270)[0083,0084]; and a second signal path adjacent to the first signal path and comprising a plurality of second waveguides(111A/111B) formed of a second dielectric material(13), the second signal path configured to transmit an optical signal[0080];
Fujikata does not disclose a third semiconductor die, comprising: a first signal path comprising a plurality of first waveguides formed of a first dielectric material(13), the first signal path configured to transmit the electrical signal(270)[0083,0084]; wherein the third semiconductor die is electrically connected to the first semiconductor die(131/132) and the second semiconductor die(131/132) that are disposed on a same side of the third semiconductor die, wherein the first semiconductor die(131/132) is electrically coupled to the second semiconductor die(131/132) through the first signal path and the second signal path.
Yu disclose in Fig 28, 33 a third semiconductor die(311/313/317 of Yu), comprising: a first signal path comprising a plurality of first waveguides(21of Yu) [0094 of Yu] formed of a first dielectric material[0094 of Yu], the first signal path configured to transmit the electrical signal[0094 of Yu]; wherein the first semiconductor die(311/313/317 of Yu) is electrically coupled to the second semiconductor die(311/313/317 of Yu) through the first signal path (electrical/optical)[0094 of Yu] and the second signal path (electrical/optical)[0094 of Yu].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Yu to the teachings of Fujikata in order to to allows for high-speed optical signaling with power and performance enhancement [0094, Yu]. In doing so, wherein the third semiconductor die(311/313/317 of Yu) is electrically connected to the first semiconductor die(311/313/317 of Yu) and the second semiconductor die(131/132) that are disposed on a same side of the third semiconductor die,
Re claim 22 Fujikata and Yu disclose the semiconductor package of claim 21, wherein the first waveguides and the second waveguides(111A/111B) of the third semiconductor die is encapsulating by a third dielectric material that is different from the first and second dielectric material(13)s.
Re claim 23 Fujikata and Yu disclose the semiconductor package of claim 21, wherein the third semiconductor die further comprises a photodetector configured to convert the optical signal[0080] to be part of the electrical signal(270)[0083,0084].
Response to Arguments
Applicant’s arguments with respect to claim 1-17, 21-23 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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