Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 2, 5 – 6, 10 – 11, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Mears (Pub. No. 20050017235 A1), hereinafter Mears, in view of Liu (Pub. No. 20150244151 A1), hereinafter Liu.
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Regarding Independent Claim 1 ( Original ), Mears teaches a semiconductor device comprising:
at least one semiconductor layer including a superlattice ( Mears, FIG. 1, FIG. 2, (25); [0033], superlattice (25) material for a channel region in a CMOS device ) therein, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers ( Mears, FIG. 2, (46); [0037], a plurality of stacked base semiconductor monolayers 46 defining a respective base semiconductor portion 46a-46n ) defining a base semiconductor portion ( Mears, FIG. 2, (46a-46n); [0037], base semiconductor portion (46a-46n) ), and at least one non-semiconductor monolayer ( Mears, FIG. 2, (50); [0038], The energy-band modifying layer (50) illustratively comprises one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions ) constrained within a crystal lattice of adjacent base semiconductor portions ( Mears, FIG. 2, (46a-46n); [0037], base semiconductor portion 46a-46n );
Mears fails to disclose:
a plurality of quantum dots spaced apart in the at least one semiconductor layer above the superlattice and comprising a different semiconductor material than the semiconductor layer.
However, Liu teaches:
a plurality of quantum dots ( Liu, FIG. 4, 5-layer InGa/InGaAs DWELL; [0027], to relax the strain, and also less defects to propagate into the III-V active region, leading to an increase in the RT photoluminescence intensity for Si-based InAs/GaAs QDs. A 5-layer InAs/InGaAs dot-in-a-well (DWELL) laser structure on a Si substrate was fabricated with the use of an AlAs NL; [0029], Next, an InAs/InGaAs dot-in-a-well (DWELL) structure was fabricated on the III-V buffer layers with the use of AlAs or GaAs NLs ) spaced apart in the at least one semiconductor layer above the superlattice ( Liu, [0030], The 5-layer InAs/InGaAs DWELL active region was grown at the center of an undoped 150-nm GaAs/AlGaAs waveguide layer with an n-type lower and a p-type upper cladding layer consisting of 1.5-µm AlGaAs; [0032], Multilayer InGaAs/GaAs dislocation filter layers, consisting of two repeats of a five-period (10-nm In0.15Ga 0.85As/10-nm GaAs) superlattices (SPL) and 350-nm GaAs, were deposited on the GaAs buffer layer. Finally 160-nm SPL layers of alternating 2-nm Ga/As/2-nm Al0.4Ga0.6As layer completed the III-V buffer layers. A five-layer InAs/InGaAs dot-in-a-well (DWELL) structure was then grown at optimised conditions as on GaAs substrates, with each layer consisting of 3.0 MLs of InAs grown on 2 nm of In0.15Ga0.85As and capped by 6 nm of In0.15Ga0.85As at ~ 510°C. 45-nm GaAs barriers separated the five DWELLs ) and comprising a different semiconductor material than the semiconductor layer.
Mears and Liu are both considered to be analogous to the claimed invention because they are superlattices (SPL) and III-V compound semiconductor structures. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mears ( superlattice comprising base semiconductor portion and non-semiconductor monolayer ), to incorporate the teachings of Liu ( 5-layer InAs/InGaAs DWELL active region was grown at the center of an undoped 150-nm GaAs/AlGaAs waveguide layer or above a five-period (10-nm In0.15Ga 0.85As/10-nm GaAs) superlattices (SPL) ), to implement that the quantum dots was grown above the superlattice. Doing so would reduce the defects and provide specific energy band structures, and therefore a higher carrier mobility can be implemented.
Regarding Claim 2 ( Original ), Mears and Liu teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Liu further teaches:
wherein the at least one semiconductor layer comprises a semiconductor substrate and an epitaxial semiconductor layer ( Liu, [0032], Multilayer InGaAs/GaAs dislocation filter layers ) on the substrate; wherein the superlattice ( Liu, [0032], a five-period (10-nm In0.15Ga 0.85As/10-nm GaAs) superlattices (SPL) ) is within the epitaxial semiconductor layer ( Liu, [0032], Multilayer InGaAs/GaAs dislocation filter layers ); and wherein the quantum dots ( Liu, [0032], A five-layer InAs/InGaAs dot-in-a-well (DWELL) structure ) are above the superlattice ( Liu, [0032], a five-period (10-nm In0.15Ga 0.85As/10-nm GaAs) superlattices (SPL) ) within the epitaxial semiconductor layer ( Liu, [0032], Multilayer InGaAs/GaAs dislocation filter layers ).
Regarding Claim 5 ( Original ), Mears and Liu teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Liu further teaches:
wherein the plurality of quantum dots comprise gallium arsenide ( Liu, FIG. 4, 5-layer InGa/InGaAs DWELL; [0027]; [0032], A five-layer InAs/InGaAs dot-in-a-well (DWELL) structure was then grown at optimised conditions as on GaAs substrates ).
Regarding Claim 6 ( Original ), Mears and Liu teach the semiconductor device as claimed in claim 2, on which this claim is dependent, Mears and Liu further teach:
further comprising spaced apart source and drain regions ( Mears, [0034], source/drain regions 22, 23 ) in the epitaxial semiconductor layer ( Liu, [0032], Multilayer InGaAs/GaAs dislocation filter layers ) defining a channel region ( Mears, [0034], a channel region therebetween provided by the superlattice 25 ) therebetween, and a gate (Mears, [0034], A gate 35 illustratively includes a gate insulating layer 37 adjacent the channel provided by the superlattice 25) above the channel region( Mears, [0034] ) on the epitaxial semiconductor layer ( Liu, [0032] ).
Regarding Claim 10 ( Original ), Mears and Liu teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Mears further teaches:
wherein the at least one non-semiconductor comprises oxygen (Mears, [0017], In addition, each energy band-modifying layer may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen).
Regarding Independent Claim 11 ( Original ), Mears teaches a semiconductor device comprising:
a semiconductor substrate ( Mears, FIG. 1, 21; [0034], substrate 21 );
an epitaxial semiconductor layer above the semiconductor substrate ( Mears, FIG. 1, 21; [0034], substrate 21 ) and including a superlattice ( Mears, FIG. 1, FIG. 2, 25; [0033], superlattice 25 material for a channel region in a CMOS device ) therein, the superlattice ( Mears, FIG. 1, FIG. 2, 25; [0033] ) comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers ( Mears, FIG. 2, 46; [0037], a plurality of stacked base semiconductor monolayers 46 defining a respective base semiconductor portion 46a-46n ) defining a base semiconductor portion ( Mears, FIG. 2, 46a-46n; [0037], base semiconductor portion 46a-46n ), and at least one non-semiconductor monolayer ( Mears, FIG. 2, 50; [0038], The energy-band modifying layer 50 illustratively comprises one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions ) constrained within a crystal lattice of adjacent base semiconductor portions ( Mears, FIG. 2, 46a-46n; [0037], base semiconductor portion 46a-46n );
spaced apart source and drain regions ( Mears, [0034], source/drain regions 22, 23 ) in the epitaxial semiconductor layer defining a channel region ( Mears, [0034], a channel region therebetween provided by the superlattice 25 ) therebetween; and
a gate ( Mears, [0034], A gate 35 illustratively includes a gate insulating layer 37 adjacent the channel provided by the superlattice 25 ) above the channel region ( Mears, [0034] ) on the epitaxial semiconductor layer.
Mears fails to disclose:
a plurality of quantum dots spaced apart in the epitaxial semiconductor layer above the superlattice and comprising a different semiconductor material than the epitaxial semiconductor layer;
However, Liu teaches:
a plurality of quantum dots ( Liu, FIG. 4, 5-layer InGa/InGaAs DWELL; [0027], to relax the strain, and also less defects to propagate into the III-V active region, leading to an increase in the RT photoluminescence intensity for Si-based InAs/GaAs QDs. A 5-layer InAs/InGaAs dot-in-a-well (DWELL) laser structure on a Si substrate was fabricated with the use of an AlAs NL; [0029], Next, an InAs/InGaAs dot-in-a-well (DWELL) structure was fabricated on the III-V buffer layers with the use of AlAs or GaAs NLs ) spaced apart in the epitaxial semiconductor layer above the superlattice( Liu, [0030], The 5-layer InAs/InGaAs DWELL active region was grown at the center of an undoped 150-nm GaAs/AlGaAs waveguide layer with an n-type lower and a p-type upper cladding layer consisting of 1.5-µm AlGaAs; [0032], Multilayer InGaAs/GaAs dislocation filter layers, consisting of two repeats of a five-period (10-nm In0.15Ga 0.85As/10-nm GaAs) superlattices (SPL) and 350-nm GaAs, were deposited on the GaAs buffer layer. Finally 160-nm SPL layers of alternating 2-nm Ga/As/2-nm Al0.4Ga0.6As layer completed the III-V buffer layers. A five-layer InAs/InGaAs dot-in-a-well (DWELL) structure was then grown at optimised conditions as on GaAs substrates, with each layer consisting of 3.0 MLs of InAs grown on 2 nm of In0.15Ga0.85As and capped by 6 nm of In0.15Ga0.85As at ~ 510°C. 45-nm GaAs barriers separated the five DWELLs ) and comprising a different semiconductor material than the epitaxial semiconductor layer;
Mears and Liu are both considered to be analogous to the claimed invention because they are superlattices (SPL) and III-V compound semiconductor structures. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mears ( superlattice comprising base semiconductor portion and non-semiconductor monolayer ), to incorporate the teachings of Liu ( 5-layer InAs/InGaAs DWELL active region was grown at the center of an undoped 150-nm GaAs/AlGaAs waveguide layer or above a five-period (10-nm In0.15Ga 0.85As/10-nm GaAs) superlattices (SPL) ), to implement that the quantum dots was grown above the superlattice. Doing so would reduce the defects and provide specific energy band structures, and therefore a higher carrier mobility can be implemented.
Regarding Claim 15 ( Original ), Mears and Liu teach the semiconductor device as claimed in claim 11, on which this claim is dependent, Liu further teaches:
wherein the plurality of quantum dots comprise gallium arsenide ( Liu, FIG. 4, 5-layer InGa/InGaAs DWELL; [0027]; [0032], A five-layer InAs/InGaAs dot-in-a-well (DWELL) structure was then grown at optimised conditions as on GaAs substrates ).
Claim(s) 3 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mears in view of Liu as applied to claims 1 – 2, 5 – 6, 10 – 11, and 15 above, and further in view of Ma (Pat. No. 5144409 A), hereinafter Ma.
Regarding Claim 3 ( Original ), Mears and Liu teach the semiconductor device as claimed in claim 2, on which this claim is dependent, Mears and Liu further teach:
wherein the semiconductor substrate ( Mears, FIG. 1, 21; [0034], substrate 21 ) and the epitaxial semiconductor layer ( Liu, [0032], Multilayer InGaAs/GaAs dislocation filter layers ) comprise silicon ( Mears, [0014], In some preferred embodiments, each base semiconductor portion may comprise silicon );
Mears and Liu fail to teach:
wherein the epitaxial semiconductor layer has a higher percentage of silicon 28 (28Si) than the semiconductor substrate.
However, Ma teaches:
wherein the epitaxial semiconductor layer has a higher percentage of silicon 28 (28Si) ( Ma, column 2, line 29, In the case of silicon, the silicon region has a higher proportion of one of the isotopes of Si than is present in naturally occurring silicon (e.g., it is composed of at least 98% 28Si); column 2, line 40, the invention is a semiconductor structure including an isotopically enriched single-crystal silicon region composed of at least 98% 28Si ) than the semiconductor substrate ( Ma, column 5, line 14, the benefits of using an isotopically enriched layer (i.e. the improved carrier mobilities and the thermal conductivities) ).
Mears and Liu and Ma are all considered to be analogous to the claimed invention because they are epitaxial semiconductor layer with high carrier mobility and thermal conductivity. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mears and Liu ( epitaxial semiconductor layer comprise silicon ), to incorporate the teachings of Ma ( a semiconductor structure including an isotopically enriched single-crystal silicon region composed of at least 98% 28Si ), to implement epitaxial semiconductor layer. Doing so would provide specific silicon composition for epitaxial semiconductor layer, and therefore epitaxial semiconductor layer with high carrier mobility and thermal conductivity can be implemented.
Regarding Claim 12 ( Original ), Mears and Liu teach the semiconductor device as claimed in claim 11, on which this claim is dependent, Mears and Liu further teach:
wherein the semiconductor substrate ( Mears, FIG. 1, 21; [0034], substrate 21 ) and the epitaxial semiconductor layer ( Liu, [0032], Multilayer InGaAs/GaAs dislocation filter layers ) comprise silicon ( Mears, [0014], In some preferred embodiments, each base semiconductor portion may comprise silicon );
Mears and Liu fail to teach:
wherein the epitaxial semiconductor layer has a higher percentage of silicon 28 (28Si) than the semiconductor substrate.
However, Ma teaches:
wherein the epitaxial semiconductor layer has a higher percentage of silicon 28 (28Si) (Ma, column 2, line 29, In the case of silicon, the silicon region has a higher proportion of one of the isotopes of Si than is present in naturally occurring silicon (e.g., it is composed of at least 98% 28Si); column 2, line 40, the invention is a semiconductor structure including an isotopically enriched single-crystal silicon region composed of at least 98% 28Si) than the semiconductor substrate ( Ma, column 5, line 14, the benefits of using an isotopically enriched layer (i.e. the improved carrier mobilities and the thermal conductivities) ).
Mears and Liu and Ma are all considered to be analogous to the claimed invention because they are epitaxial semiconductor layer with high carrier mobility and thermal conductivity. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mears and Liu ( epitaxial semiconductor layer comprise silicon ), to incorporate the teachings of Ma ( a semiconductor structure including an isotopically enriched single-crystal silicon region composed of at least 98% 28Si ), to implement epitaxial semiconductor layer. Doing so would provide specific silicon composition for epitaxial semiconductor layer, and therefore epitaxial semiconductor layer with high carrier mobility and thermal conductivity can be implemented.
Claim(s) 4, 14, 16-17, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mears in view of Liu as applied to claims 1-2,5-6,10-11, and 15 above, and further in view of Maa (2009/0173933), hereinafter Maa.
Regarding Claim 4 ( Original ), Mears and Liu teach the semiconductor device as claimed in claim 1, on which this claim is dependent,
Mears and Liu fail to teach:
wherein the plurality of quantum dots comprise germanium.
However, Maa teaches:
wherein the plurality of quantum dots comprise germanium ( Maa, [0035], In this aspect the SiGe superlattice 114 includes Ge quantum dots … In this aspect however, Ge quantum dots 300 overlie each Si layer 200 ).
Mears and Liu and Maa are all considered to be analogous to the claimed invention because they are superlattices (SPL) and III-V compound semiconductor structures. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mears and Liu ( superlattice comprising base semiconductor portion and non-semiconductor monolayer ), to incorporate the teachings of Maa ( Ge quantum dots ), to implement superlattices. Doing so would provide specific Ge composition for quantum dots, and therefore quantum efficiency can be improved.
Regarding Claim 14 ( Original ), Mears and Liu teach the semiconductor device as claimed in claim 11, on which this claim is dependent,
Mears and Liu fail to teach:
wherein the plurality of quantum dots comprise germanium.
However, Maa teaches:
wherein the plurality of quantum dots comprise germanium ( Maa, [0035], In this aspect the SiGe superlattice 114 includes Ge quantum dots … In this aspect however, Ge quantum dots 300 overlie each Si layer 200 ).
Mears and Liu and Maa are all considered to be analogous to the claimed invention because they are superlattices (SPL) and III-V compound semiconductor structures. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mears and Liu ( superlattice comprising base semiconductor portion and non-semiconductor monolayer ), to incorporate the teachings of Maa ( Ge quantum dots ), to implement superlattices. Doing so would provide specific Ge composition for quantum dots, and therefore quantum efficiency can be improved.
Regarding Independent Claim 16 ( Original ), Mears teaches a semiconductor device comprising:
at least one silicon layer including a superlattice ( Mears, FIG. 1, FIG. 2, 25; [0033], superlattice 25 material for a channel region in a CMOS device ) therein, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers ( Mears, FIG. 2, 46; [0037], a plurality of stacked base semiconductor monolayers 46 defining a respective base semiconductor portion 46a-46n ) defining a base silicon portion ( Mears, FIG. 2, 46a-46n; [0037], base semiconductor portion 46a-46n ), and at least one oxygen monolayer ( Mears, FIG. 2, 50; [0038], The energy-band modifying layer 50 illustratively comprises one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; [0017], In addition, each energy band-modifying layer may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen ) constrained within a crystal lattice of adjacent base semiconductor portions ( Mears, FIG. 2, 46a-46n; [0037], base semiconductor portion 46a-46n ); and
Mears fails to disclose:
a plurality of quantum dots spaced apart in the at least one silicon layer above the superlattice.
However, Liu teaches:
a plurality of quantum dots ( Liu, FIG. 4, 5-layer InGa/InGaAs DWELL; [0027], to relax the strain, and also less defects to propagate into the III-V active region, leading to an increase in the RT photoluminescence intensity for Si-based InAs/GaAs QDs. A 5-layer InAs/InGaAs dot-in-a-well (DWELL) laser structure on a Si substrate was fabricated with the use of an AlAs NL; [0029], Next, an InAs/InGaAs dot-in-a-well (DWELL) structure was fabricated on the III-V buffer layers with the use of AlAs or GaAs NLs ) spaced apart in the at least one silicon layer above the superlattice ( Liu, [0030], The 5-layer InAs/InGaAs DWELL active region was grown at the center of an undoped 150-nm GaAs/AlGaAs waveguide layer with an n-type lower and a p-type upper cladding layer consisting of 1.5-µm AlGaAs; [0032], Multilayer InGaAs/GaAs dislocation filter layers, consisting of two repeats of a five-period (10-nm In0.15Ga 0.85As/10-nm GaAs) superlattices (SPL) and 350-nm GaAs, were deposited on the GaAs buffer layer. Finally 160-nm SPL layers of alternating 2-nm Ga/As/2-nm Al0.4Ga0.6As layer completed the III-V buffer layers. A five-layer InAs/InGaAs dot-in-a-well (DWELL) structure was then grown at optimised conditions as on GaAs substrates, with each layer consisting of 3.0 MLs of InAs grown on 2 nm of In0.15Ga0.85As and capped by 6 nm of In0.15Ga0.85As at ~ 510°C. 45-nm GaAs barriers separated the five DWELLs ).
Mears and Liu are both considered to be analogous to the claimed invention because they are superlattices (SPL) and III-V compound semiconductor structures. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mears ( superlattice comprising base semiconductor portion and non-semiconductor monolayer ), to incorporate the teachings of Liu ( 5-layer InAs/InGaAs DWELL active region was grown at the center of an undoped 150-nm GaAs/AlGaAs waveguide layer or above a five-period (10-nm In0.15Ga 0.85As/10-nm GaAs) superlattices (SPL) ), to implement that the quantum dots was grown above the superlattice. Doing so would reduce the defects and provide specific energy band structures, and therefore a higher carrier mobility can be implemented.
Mears and Liu fail to teach:
wherein the plurality of quantum dots comprise germanium.
However, Maa teaches:
wherein the plurality of quantum dots comprise germanium ( Maa, [0035], In this aspect the SiGe superlattice 114 includes Ge quantum dots … In this aspect however, Ge quantum dots 300 overlie each Si layer 200 ).
Mears and Liu and Maa are all considered to be analogous to the claimed invention because they are superlattices (SPL) and III-V compound semiconductor structures. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mears and Liu ( superlattice comprising base semiconductor portion and non-semiconductor monolayer ), to incorporate the teachings of Maa ( Ge quantum dots ), to implement superlattices. Doing so would provide specific Ge composition for quantum dots, and therefore quantum efficiency can be improved.
Regarding Claim 17 ( Original ), Mears and Liu and Maa teach the semiconductor device as claimed in claim 16, on which this claim is dependent, Liu further teaches:
wherein the at least one silicon layer comprises a silicon substrate and an epitaxial silicon layer ( Liu, [0032], Multilayer InGaAs/GaAs dislocation filter layers ) on the silicon substrate; wherein the superlattice ( Liu, [0032], a five-period (10-nm In0.15Ga 0.85As/10-nm GaAs) superlattices (SPL) ) is within the epitaxial silicon layer ( Liu, [0032], Multilayer InGaAs/GaAs dislocation filter layers ); and wherein the quantum dots ( Liu, [0032], A five-layer InAs/InGaAs dot-in-a-well (DWELL) structure ) are above (Liu, [0032], A five-layer InAs/InGaAs dot-in-a-well (DWELL) structure was then grown at optimised conditions as on GaAs substrates) the superlattice ( Liu, [0032], a five-period (10-nm In0.15Ga 0.85As/10-nm GaAs) superlattices (SPL) ) within the epitaxial silicon layer ( Liu, [0032], Multilayer InGaAs/GaAs dislocation filter layers ).
Regarding Claim 19 ( Original ), Mears and Liu and Maa teach the semiconductor device as claimed in claim 16, on which this claim is dependent, Mears and Liu further teach:
further comprising spaced apart source and drain regions ( Mears, [0034], source/drain regions 22, 23 ) in the epitaxial semiconductor layer ( Liu, [0032], Multilayer InGaAs/GaAs dislocation filter layers ) defining a channel region ( Mears, [0034], a channel region therebetween provided by the superlattice 25 ) therebetween, and a gate (Mears, [0034], A gate 35 illustratively includes a gate insulating layer 37 adjacent the channel provided by the superlattice 25) above the channel region ( Mears, [0034] ) on the epitaxial semiconductor layer( Liu, [0032] ).
Claim(s) 7-9 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mears in view of Liu as applied to claims 1-2,5-6,10-11, and 15 above, and further in view of Pioro-Ladriere ( Pub. No. 20190130298 A1 ), hereinafter Pioro-Ladriere.
Regarding Claim 7 ( Original ), Mears and Liu teach the semiconductor device as claimed in claim 6, on which this claim is dependent,
Mears and Liu fail to teach:
wherein the gate comprises at least one accumulation gate.
However, Pioro-Ladriere teaches:
wherein the gate comprises at least one accumulation gate ( Pioro-Ladriere, Abstract, A gap between a reservoir accumulation gate and a quantum dot accumulation gate provides a tunnel barrier between an electric charge reservoir and a quantum dot well ).
Mears and Liu and Pioro-Ladriere are all considered to be analogous to the claimed invention because they are superlattice, quantum dots and III-V compound semiconductor structures. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mears and Liu ( superlattice, quantum dots ), to incorporate the teachings of Pioro-Ladriere ( accumulation gate ), to implement superlattice with quantum dots and accumulation gate. Doing so would provide specific gate for quantum dots, and therefore to precisely control the number of electrons or holes in the quantum dot.
Regarding Claim 8 ( Original ), Mears and Liu and Pioro-Ladriere teach the semiconductor device as claimed in claim 6, on which this claim is dependent, Pioro-Ladriere further teaches:
wherein the gate comprises at least one plunger gate ( Pioro-Ladriere, [0014], Confinement gates 351 to 354 define the size of quantum dots. Plunger gates 352 and 353 set QD1 and QD2 charge states ).
Regarding Claim 9 ( Original ), Mears and Liu and Pioro-Ladriere teach the semiconductor device as claimed in claim 6, on which this claim is dependent, Pioro-Ladriere further teaches:
wherein the gate comprises at least one barrier gate ( Pioro-Ladriere, [0014], Barrier gates 341, 342 and 343 control the tunnel barriers between the reservoirs and the dots ).
Regarding Claim 13 ( Original ), Mears and Liu teach the semiconductor device as claimed in claim 11, on which this claim is dependent,
Mears and Liu fail to teach:
wherein the gate comprises at least one of an accumulation gate, a plunger gate, and a barrier gate.
However, Pioro-Ladriere teaches:
wherein the gate comprises at least one of an accumulation gate ( Pioro-Ladriere, [0014], Confinement gates 351 to 354 define the size of quantum dots. Plunger gates 352 and 353 set QD1 and QD2 charge states ), a plunger gate ( Pioro-Ladriere, [0014], Confinement gates 351 to 354 define the size of quantum dots. Plunger gates 352 and 353 set QD1 and QD2 charge states ), and a barrier gate ( Pioro-Ladriere, [0014], Barrier gates 341, 342 and 343 control the tunnel barriers between the reservoirs and the dots ).
Mears and Liu and Pioro-Ladriere are all considered to be analogous to the claimed invention because they are superlattice, quantum dots and III-V compound semiconductor structures. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mears and Liu ( superlattice, quantum dots ), to incorporate the teachings of Pioro-Ladriere ( accumulation gate, plunger gate, barrier gate ), to implement superlattice with quantum dots and accumulation gate, plunger gate, barrier gate. Doing so would provide specific gate for quantum dots, and therefore to precisely control the number of electrons or holes in the quantum dot.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mears in view of Liu and Maa as applied to claims 4, 14, 16-17, and 19 above, and further in view of Ma.
Claims 18 is rejected under 35 U.S.C. 103 as being unpatentable over Mears, in view of Liu, in view of Maa (‘933), in view of Ma (‘409).
Regarding Claim 18 ( Original ), Mears and Liu and Maa teach the semiconductor device as claimed in claim 17, on which this claim is dependent, Mears and Liu further teach:
wherein the silicon substrate and the epitaxial silicon layer comprise silicon ( Mears, [0014], each base semiconductor portion may comprise silicon );
Mears and Liu and Maa (‘933) fail to teach:
wherein the epitaxial silicon layer has a higher percentage of silicon 28 (28Si) than the silicon substrate.
However, Ma (‘409) teaches:
wherein the epitaxial silicon layer has a higher percentage of silicon 28 (28Si) Ma (‘409), column 2, line 29, In the case of silicon, the silicon region has a higher proportion of one of the isotopes of Si than is present in naturally occurring silicon (e.g., it is composed of at least 98% 28Si); column 2, line 40, the invention is a semiconductor structure including an isotopically enriched single-crystal silicon region composed of at least 98% 28Si ) than the silicon substrate ( Ma (‘409), column 5, line 14, the benefits of using an isotopically enriched layer (i.e. the improved carrier mobilities and the thermal conductivities) ).
Mears, Liu, Maa (‘933) and Ma (‘409) are all considered to be analogous to the claimed invention because they are epitaxial semiconductor layer with high carrier mobility and thermal conductivity. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mears, Liu, Maa (‘933) ( epitaxial semiconductor layer comprise silicon, quantum dots comprise germanium ), to incorporate the teachings of Ma (‘409) ( a semiconductor structure including an isotopically enriched single-crystal silicon region composed of at least 98% 28Si ), to implement epitaxial semiconductor layer. Doing so would provide specific silicon composition for epitaxial semiconductor layer, and therefore epitaxial semiconductor layer with high carrier mobility and thermal conductivity can be implemented.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mears in view of Liu and Maa as applied to claims 4, 14, 16-17, and 19 above, and further in view of Pioro-Ladriere.
Regarding Claim 20 ( Original ), Mears and Liu and Maa teach the semiconductor device as claimed in claim 16, on which this claim is dependent,
Mears and Liu and Maa fail to teach:
wherein the gate comprises at least one of an accumulation gate, a plunger gate, and a barrier gate.
However, Pioro-Ladriere teaches:
wherein the gate comprises at least one of an accumulation gate ( Pioro-Ladriere, Abstract, A gap between a reservoir accumulation gate and a quantum dot accumulation gate provides a tunnel barrier between an electric charge reservoir and a quantum dot well ), a plunger gate ( Pioro-Ladriere, [0014], Confinement gates 351 to 354 define the size of quantum dots. Plunger gates 352 and 353 set QD1 and QD2 charge states ), and barrier gate ( Pioro-Ladriere, [0014], Barrier gates 341, 342 and 343 control the tunnel barriers between the reservoirs and the dots ).
Mears, Liu, Maa and Pioro-Ladriere are all considered to be analogous to the claimed invention because they are superlattice, quantum dots and III-V compound semiconductor structures. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mears, Liu, Maa ( superlattice, quantum dots, quantum dots comprise germanium ), to incorporate the teachings of Pioro-Ladriere ( accumulation gate, plunger gate, barrier gate ), to implement superlattice with quantum dots and accumulation gate, plunger gate, barrier gate. Doing so would provide specific gate for quantum dots, and therefore to precisely control the number of electrons or holes in the quantum dot.
Response to Arguments
Applicant's remarks filed 03/09/2026 have been fully considered but they are not persuasive.
Applicant’s remarks regarding ( Original ) Independent Claims 1, 11, 16: on page 10, line 6 from bottom, cited “ Applicant respectfully submits that the Examiner is using improper hindsight to selectively combine the disjoint teachings of Mears et al. and Liu et al. Mears et al. uses the superlattice to achieve the key benefits - lower conductivity effective mass and higher carrier mobility - for lateral transport parallel to the planes (e.g., as a MOSFET channel), with all layer thicknesses and compositions chosen to maintain a common band structure along that direction. The quantum dots in Liu et al., by contrast, are used for vertical optical confinement and recombination in a laser cavity; the critical physics is carrier capture into localized QD states and radiative recombination, not lateral channel mobility. Accordingly, one of skill in the art would recognize that inserting a lateral-mobility-optimized Si/O superlattice in series with a vertical QD laser stack has no clear benefit to lasing characteristics and would complicate both carrier injection and optical mode design. ”.
Examiner’s response: First, “ In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. ”, see In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971). Second, please refer to claims 1, 11, 16 in Claim Rejections - 35 USC § 103 of this office action, for instance, claim 1, cited “ Mears and Liu are both considered to be analogous to the claimed invention because they are forming superlattices (SPL) and III-V compound semiconductor structures. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mears ( superlattice comprising base semiconductor portion and non-semiconductor monolayer ), to incorporate the teachings of Liu ( 5-layer InAs/InGaAs DWELL active region was grown at the center of an undoped 150-nm GaAs/AlGaAs waveguide layer or above a five-period (10-nm In0.15Ga 0.85As/10-nm GaAs) superlattices (SPL) ), to implement that the quantum dots was grown above the superlattice. Doing so would reduce the defects and provide specific energy band structures, and therefore a higher carrier mobility can be implemented. ”. The combination of Mears and Liu are based on above two reasons.
Applicant’s remarks regarding Liu: on page 11, line 12, cited “ In addition, Liu et al. already teaches a complete solution for Si-based QD lasers using an AlAs (or Al1-xXxAs) nucleation layer and III-V buffer/superlattice design. The performance improvements (reduced threading dislocations, enhanced PL, lower threshold current) are achieved without any Si/O superlattice. ”.
Examiner’s response: First, “ In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. ”, see In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Second, Liu, [0029], cited “ Next, an InAs/InGaAs dot-in-a-well (DWELL) structure was fabricated on the III-V buffer layers with the use of AlAs or GaAs NLs. III-V buffer layers consist of the following layer sequence: AlAs NL, GaAs buffer layer, InGaAs/GaAs dislocation filter layer, and GaAs/AlGaAs superlattice layers … ” and [0032], cited “ Multilayer InGaAs/GaAs dislocation filter layers, consisting of two repeats of a five-period (10-nm In0.15Ga0.85As/10-nm GaAs) superlattices (SPL) and 350-nm GaAs, were deposited on the GaAs buffer layer … ”. Therefore, based on above two reasons, applicant’s remarks regarding Liu are not persuasive.
Terminal Disclaimer
The terminal disclaimer filed on 03/09/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of Application Number 18/338,415 ( reference application ) has been reviewed and is accepted. The terminal disclaimer has been recorded.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached Monday thru Friday E.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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