DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-13, and 21-24 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. (US 2020/0176457 A1) (“Sharma”), in view of Muller et al. (US 2014/0355328 A1) (“Muller”).
Note: In order to make the combination clearing in light of the claims Examiner will be applying both references at the same time. The primary reference is Sharma. The modification is the replacement of Sharma’s ferroelectric layer with Muller’s ferroelectric layer. The motivation to combine will be provided at the end of the analysis.
Regarding claim 1, Sharma teaches at least in figure 1, and Muller teaches at least in figure 2:
a ferroelectric structure (Sharma 120; Muller 14) including
a ferroelectric layer (Muller upper 6; hereinafter “A”) and an anti-ferroelectric layer (Muller lower 6; hereinafter “B”) (Where in ¶¶ 0030-33, the upper and lower 6 can be the same or different, such that one can be FE, and the other can be AFE. Therefore, it would have been obvious based upon Muller the A could be FE, and the B could be AFE);
a gate structure (Sharma 110) disposed along a first face of the anti-ferroelectric layer (Muller A),
such that the anti-ferroelectric layer (Muller 6 B) separates the gate structure (Sharma 110) from the ferroelectric layer (Muller A);
an oxide semiconductor (Sharma 130; ¶¶ 0028-30) disposed along a first face of the ferroelectric layer (Muller A),
such that the ferroelectric layer (Muller A) separates the oxide semiconductor (Sharma 130) from the anti-ferroelectric layer (Muller B);
wherein a width of the oxide semiconductor (Sharma 130) is less than the width of the gate structure (Sharma 110) (Examiner is rejected this limitation for two reasons. Reason one, the claim only requires the oxide semiconductor to have less width than the gate structure. The claim does not state how much less. Therefore, under the broadest reasonable interpretation this can be that the oxide semiconductor is one atom less in width than the gate structure. This would be obvious in light of standard process variables in semiconductor. Where one atom difference in width, thickness, etc. is well within the standard process variables when measured in nanometers. The second interpretation is the prior art performs the same function as the claimed feature. It is well-known that the channel is generally delineated as the spacing between the source and drain. This is acknowledged in the L element in Applicant’s figures. The excess semiconductor material is not a functional aspect of the device. Rather, it is there for process reasons such as overlay, or is there to allow one to construct the rest of the device above it as shown in Sharma. Therefore, whether the channel has less width than the gate may be a structural difference it has no patentable functional effect in the final device. Thus, this limitation could also be considered a change in size or proportion where a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04(III)(A), and/or can be considered a change in shape as there is no persuasive evidence of record that the particular shape of the claimed oxide semiconductor layer relative to the gate structure was significant or would perform differently. MPEP 2144.04(III)(B).
a source region (Sharma 140) and a drain region (Sharma 150) disposed on the oxide semiconductor (Sharma 130),
wherein the gate structure (Sharma 110) extends laterally over (Examiner understands “over” to mean that the gate structure extends the length of the anti-ferroelectric layer as shown in Applicant’s figure 4, where the gate structure 102 is under the anti-ferroelectric layer 112 and extends the length of the anti-ferroelectric layer 112) the anti-ferroelectric layer (Muller B) between the source region (Sharma 140) and the drain region (Sharma 150); and
an interlayer (Muller 8) separating the ferroelectric layer (Muller A) from the anti-ferroelectric layer (Muller B).
It would have been obvious to one of ordinary skill in the art to replace the ferroelectric layer of Sharma with the ferroelectric layer of Muller as Muller teaches this is an improvement over the ferroelectric layer of Sharma as Muller’s ferroelectric layer minimizes the charge trapping of Sharma’s ferroelectric layer, and improves the sensing (reading of the ferroelectric layers) and improves the memory window the ferroelectric layers. ¶¶ 0005.
Regarding claim 2, Muller teaches at least in figure 2:
wherein the ferroelectric layer comprises Hf1-xZrxO, and the anti-ferroelectric layer comprises Hf1-yZryO, where x and y are different (Muller ¶¶ 0023, and 30-33, where Muller A and Muller B can be different compositions of Hf and Zr, along with different doping concentrations).
Regarding claim 3, Muller teaches at least in figure 2:
wherein x is between 0 and 0.5, and y is between 0.5 and 1 (Muller ¶ 0023).
Regarding claim 4, Muller teaches at least in figure 2:
wherein the interlayer comprises (Muller 8) a metal oxide or a metal (¶ 0029).
Regarding claim 5, Muller teaches at least in figure 2:
wherein the interlayer (Muller 8) comprises the metal oxide and the metal oxide comprises titanium oxide, aluminum oxide, magnesium oxide, hafnium oxide, or indium oxide; or wherein the interlayer comprises the metal and the metal comprises titanium, platinum, gold, or nickel (¶ 0029).
Regarding claim 6, Muller teaches at least in figure 2:
wherein the ferroelectric layer has a first percentage of tetragonal crystalline lattice per unit volume and the anti-ferroelectric layer has a second percentage of tetragonal crystalline lattice per unit volume, the second percentage being greater than the first percentage (¶¶ 0032, and 38-39, where one of ordinary skill in the art can adjust the crystallization of Muller A and Muller B to obtain the desired crystallinity of each layer. It would have been obvious to one of ordinary skill in the art to use routine skill in the art and optimize the crystallinity of each layer in order to minimize the charge trapping and maximize the sensing and memory window of the ferroelectric layers).
Regarding claim 7, Muller teaches at least in figure 2:
wherein a ratio of a first percentage of orthorhombic crystal per unit volume in the ferroelectric layer to a second percentage of tetragonal crystal per unit volume in the anti-ferroelectric layer is in a range of 15:1 to 25:1 (This is considered an optimization of the prior art. As such, the optimization of the claim would be obvious to one of ordinary skill in the art. As taught be Muller the crystallinity of Muller A-B changes the ferro/anti-ferro electric properties of the Muller A-B. This is because the general conditions are disclosed in the prior art, and is it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).).
Regarding claim 8, Muller teaches at least in figure 2:
Claim 8 is obvious for the same reasons as claim 7 above.
Regarding claim 9, Muller teaches at least in figure 2:
wherein the interlayer has a coefficient of thermal expansion of 1 x 10-4 m/Kelvin (K) to 1 x 10-6 m/K (Muller 8 can comprise the same material as disclosed by Applicant. Therefore, it is obvious that it would have the same characteristic as Applicant. MPEP 2112.).
Regarding claim 10, Muller teaches at least in figure 2:
wherein the interlayer (Muller 8) has a thickness of less than 1 nanometer (¶ 0029, where Muller 8 can be from 1 angstrom (0.1 nm) to 100 angstrom (10 nm).
Regarding claim 11, Sharma teaches at least in figure 1
wherein the oxide semiconductor comprises one or more of indium gallium zinc oxide, indium gallium zinc tin oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc oxide, or zinc oxide (¶ 0028).
Regarding claim 12, Sharma teaches at least in figure 1
wherein the source region is coupled to a source-line, the drain region is coupled to a bit-line, and the gate structure is coupled to a word-line (figure 5 shows that the source, gate, and drain are all connected to different metal lines).
Regarding claim 13, Sharma teaches at least in figure 1
a substrate (while not shown in figure 1 of Sharma it would have been obvious based upon at least ¶ 0023 that the device of figure 1 of Sharma would be formed on a substrate (“Z”). This is because it is routine in the art, and in semiconductor patent publications to omit that which is known and routine. Such as forming a device, such as the device of Sharma figure 1, on a substrate.);
wherein the gate structure (Sharma 110) is disposed along a first side of the substrate (Sharma 110 would be on a top side of the substrate); and
wherein the gate structure (Sharma 110) is vertically disposed between the first side of the substrate (top of substrate) and the ferroelectric structure (Sharma 120).
Regarding claim 21
Claim 21, is rejected for the same reasons as claim 1, 6, and 13 above.
The difference between claim 21 and claims 1, 6, and 13 is the inclusion of the capping layer.
In the prior art Sharma 165 can be considered a capping layer as it is on top (caps) the active region 130.
In regards to the gate dielectric layer. According to Sharma in ¶ 0027, the ferroelectric dielectric 120 can be one or more of a plurality of materials. This mean the one can be considered a gate dielectric and the more can be ferroelectric dielectric. Since the plurality of materials are both ferroelectric and dielectrics and separate the gate from the active layer it does not matter which is which. However, Examiner would note that HZO and doped HfO2 are very common high-k dielectrics and ferroelectric materials. Therefore, Sharma teaches this limitation.
Regarding claim 22,
Claim 22 is rejected for the same reasons as claim 11 above.
Regarding claim 23,
Claim 23 is rejected for the same reasons as claims 2-3 above.
Regarding claim 24,
Claim 24 can be considered a duplication of parts. This is because one of ordinary skill in the art could make two ferroelectric transistors of the prior art. Having two of the same ferroelectric transistors next to each other on a substrate would be necessary in the formation of a memory device. The first ferroelectric transistor would be the transistor of claim 21. The second ferroelectric transistor would be the transistor of claim 24. Since they are built the same their gate electrode/conductive gate structure would be at the same height.
Claim(s) 14-16, and 25 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. (US 2020/0176457 A1) (“Sharma”), in view of Muller et al. (US 2014/0355328 A1) (“Muller”), in view of Muller et al. (US 2019/0130956 A1) (“Muller II”).
Regarding claim 14,
Claim 14 is rejected for the same reasons as claims 1 and 13 above.
Claim 14 contains additional limitations below. The previous prior art does not teach these limitations.
a capping layer disposed on the oxide semiconductor,
wherein a height of the capping layer is less than a height of the source region and less than a height of the drain region, and
wherein the capping layer includes a single dielectric material that laterally surrounds the source region and the drain region from a cross-sectional view.
Muller II teaches at least in figure 2J:
a capping layer (260a) disposed on the semiconductor (112c),
wherein a height of the capping layer (260b) is less than a height of the source region (242s/262s) and less than a height of the drain region (242d/262d), and
wherein the capping layer (260a) includes a single dielectric material (¶ 0086, where the term “may” allows for a single material) that laterally surrounds the source region and the drain region from a cross-sectional view (this is shown in figure 2L).
It would have been obvious to one of ordinary skill in the art to include the capping layer of Muller II in the previous prior art as this will not only provide insulation for each of the elements in the transistor, but it will also allow one a flat surface from which to continue to build up the device.
Regarding claim 15,
Claim 15 is rejected for the same reasons as claim 6 above.
Regarding claim 16,
Claim 16 is rejected for the same reasons as claim 2 above.
Regarding claim 25,
Claim 25 is dependent upon claim 21. Claim 21 is broader than claim 25 in what the capping layer can be. The more narrower claim 25 would be rejected under the same rational as claim 14 above.
Response to Arguments
Regarding claim 1,
The amendments to claim 1 are not persuasive for the reasons given in the analysis of claim 1 above.
Regarding claim 14,
The amendments to claim 14 have overcome the art of record. However, the claims are rejected under the previous prior art, in view of Mueller II.
Regarding claim 21,
The amendments to claim 11 are not persuasive for the reasons given in the analysis of claim 11 above.
Regarding new claim 25,
New claim 25 is being rejected under the art and analysis used in claim 14, and shown above.
For all the reasons above, Applicant’s arguments concerning their amendments are not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VINCENT WALL/Primary Examiner, Art Unit 2898
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