DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Newly submitted claims 21-28 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: claims 21-28 have isolation structure which was not present in the previously elected claims.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21-28 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-12,15,17-18,20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US Pub No. 20210020643), in view of Shen et al (US Pub No. 20100084715).
With respect to claim 9, Yang discloses :a substrate including a first region (right side of 4A) and a second region (left side,Fig.4A), wherein the first region and the second region are separated from each other (Fig.4A); a first transistor formed in the first region (220); and a second transistor (222) formed in the second region and coupled to the first transistor in series through an interconnecting structure (Fig.2), wherein the first transistor includes a first gate structure (340,Fig.4B) straddling a structure (412 right in the middle for C) protruding from the substrate (in the vertical direction), and the second transistor includes a second gate structure (340 for 222) wrapping around each of a plurality of first structures (para 40,402, Fig.4B) that are vertically spaced apart from one another (for example 402,404). However, Yang does not explicitly disclose a substrate; having an isolation structure; and the second transistor having nanostructure channel region. However, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Yang such that devices are formed on the substrate, in order for the transistors to be mechanically secured, and it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Yang such that isolation structure is between the two transistors, in order to prevent crosstalk thereby improving the device performance, and it would have been obvious to one of ordinary skill in the art at the at the time of the filing of the invention to have nano structure as nano channel, in order to save cost by using less material to make channel region. However, Yang does not explicitly disclose the first gate structure extending in a first direction and the second gate structure spaced apart from the first gate structure. On the other hand, Shen et al discloses the first gate (114 right,Fig.1A) structure extending in a first direction ( in the y direction) and the second gate structure (114 left) spaced apart from the first gate structure (Fig.1A). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Yang according to the teachings of the Shen such that the first and the second gate are spaced from each other, in order to build a 3T-gain cell, which works better than standard SRAM.
With respect to claim 10, Yang does not explicitly disclose wherein the first transistor and the second transistor collectively serve as a one-time-programmable (OTP) memory cell. However, the first transistor and the second transistor can be used in an antifuse memory cell (which is a OTP memory), in order to have an inexpensive nonvolatile memory.
With respect to claim 11, Yang discloses wherein the protruding structure is configured as a channel of the first transistor (FIg.4b), and the plurality of nanostructures are collectively configured as a channel of the second transistor (Fg.4b).
With respect to claim 12, Yang discloses wherein the first transistor includes a first source/drain (S/D) structure coupled to a first end of the protruded structure (this is an inherent feature for all the finfet), and the second transistor (the GAA transistor) includes a second S/D structure (All GAA have this,Fig.4B)) and a third S/Dcoupled to a first end and a second end of the plurality of first nanostructures (Fig.4b), respectively .
With respect to claim 15, Yang discloses wherein the connecting structure connects the first S/D structure (Fig.2) to one of the second S/D structure or the third S/D structure (Fig.2).
With respect to claim 17, the arts cited above do not explicitly disclose further comprising at least one dummy gate structure disposed between the first region and the second region. However, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Yang such that at least one dummy gate structure disposed between the first region and the second region as alignment mark in order to decrease the chance of error in fabrication of device, thereby cutting cost.
With respect to claim 18, Yang discloses a first region (right side of Fig.4A) and a second region (left side,Fig.4A),; a first transistor formed in the first region (220) and comprising: a first gate structure (340,Fig.4B) straddling a structure protruding from the substrate (the middle vertical structure);; and a second transistor formed in the second region (222), coupled to the first transistor in series (Fig.2,Fig.4A) through an interconnecting structure (Fig.4A,Fig.2), and comprising: a second gate structure (340 for the 222) wrapping around each of a plurality of first structures (402-406) that are vertically spaced apart from one another (Fig.4B). However, Yang does not explicitly disclose a substrate including; wherein the first region and the second region are separated from each other with an isolation structure; a first source/drain (S/D) structure coupled to a first end of the protruded structure; a second S/D structure coupled to a first end of the plurality of first nanostructures; and a third S/D structure coupled to a second end of the plurality of first nanostructures. However, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Yang such that devices are formed on the substrate, in order for the transistors to be mechanically secured, and it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Yang such that isolation structure is between the two transistors, in order to prevent crosstalk thereby improving the device performance, and it would have been obvious to one of ordinary skill in the art at the at the time of the filing of the invention to have nano structure as nano channel, in order to save cost by using less material to make channel region. Furthermore, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Yang such that a first source/drain (S/D) structure coupled to a first end of the protruded structure; a second S/D structure coupled to a first end of the plurality of first nanostructures; and a third S/D structure coupled to a second end of the plurality of first nanostructures; in order to have devices turned and on and off.
However, Yang does not explicitly disclose the first gate structure extending along a first direction; the second gate structure extending along the first direction and spaced apart from the gate structure. On the other hand, Shen et al discloses the first gate structure (114 left,Fig.1A) extending along a first direction (y direction); the second gate structure (114 right) extending along the first direction ( y direction) and spaced apart from the gate structure (Fig.1A). It would have been obvious to one of ordinary skill in the art at the time of the filing of invention to modify Yang according to the teachings of the Shen et al such that the first and the second gate are spaced from each other, in order to build a 3T-gain cell, which works better than standard SRAM.
With respect to claim 20, Yang discloses wherein the connecting structure (going through N1Fig.2) connects the first S/D structure to one of the second S/D structure (Fig.2) or the third S/D structure.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US Pub No. 20210020643), in view of Xie et al (US Pub No. 20180342507), in view of Shen et al (US Pub No. 20100084715).
With respect to claim 13, Yang discloses wherein the first S/D structure and the second S/D structure are immediately adjacent (Fig.2,Fig.4A); however, it does not explicitly disclose to but separated from each other by the isolation structure. On the other hand, Xie et al discloses source and drain regions of two transistors are separated from each other by a shallow isolation layer (16,Fig.7). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Yang according to the teaching of Xie et al such that an isolating region is formed between two immediate adjacent transistors to prevent crosstalk to occur between them, thereby improve the performance of the memory device.
Claim(s) 14,19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US Pub No. 20210020643), in view of Trivedi et al (US Patent No. 12369358), in view of Shen et al (US Pub No. 20100084715).
With respect to claim 14, Yang discloses wherein the first S/D structure has a first vertical height (it is formed on the top surface of the middle structure), however, Yang does not explicitly disclose and the second S/D structure and the third S/D structure have a second vertical height, the second vertical height being greater than the first vertical height. On the other hand, Trivedi et al discloses that second (120 for 172A) and third source drain regions (120 for 172A) are tall as the device itself (172A). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Yang according to the teachings of the Trivedi et al such that third and the second source/drain regions are as tall the device itself, and source and drain region for the finfet are merely on the surface of fin, in order to cut the cost by not using too much material to manufacture source and drain region. Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
With respect to claim 19, Yang discloses wherein the first S/D structure has a first vertical height (it is formed on the top surface of the middle structure), however, Yang does not explicitly disclose and the second S/D structure and the third S/D structure have a second vertical height, the second vertical height being greater than the first vertical height. On the other hand, Trivedi et al discloses that second (120 for 172A) and third source drain regions (120 for 172A) are tall as the device itself (172A). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Yang according to the teachings of the Trivedi et al such that third and the second source/drain regions are as tall the device itself, and source and drain region for the finfet are merely on the surface of fin, in order to cut the cost by not using too much material to manufacture source and drain region. Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US Pub No. 20210020643), in view of Lee et al (US Patent No. 8927997), in view of Shen et al (US Pub No. 20100084715).
With respect to claim 16, Yang does not explicitly disclose further comprising a third transistor electrically coupled to the second transistor in series and formed in the second region of the substrate, wherein the third transistor includes a third gate structure wrapping around each of a plurality of second nanostructures that are vertically spaced apart from one another. On the other hand, Lee et al a third transistor (MN13,Fig.1) electrically coupled to the second transistor (MN12) in series and formed in the second region of the substrate (on the right hand of the circuit). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the Yang such that a third transistor is formed which is in series with other transistor, in order to make an OPT device, as a nonvolatile memory device, as a design choice. However, the arts cited above do not explicitly disclose wherein the third transistor includes a third gate structure wrapping around each of a plurality of second nanostructures that are vertically spaced apart from one another. However, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to have a gate all around structure for the third transistor, in order to increase the density of the device while saving space.
Response to Arguments
Applicant’s arguments with respect to claim(s) 9-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALI N NARAGHI whose telephone number is (571)270-5720. The examiner can normally be reached 10am-6pm.
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/ALI NARAGHI/Primary Examiner, Art Unit 2817
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