DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
Applicant’s election, with traverse, of Invention I, drawn to the device of claims 1-15, in the Response to Restriction Requirements filed on 01/20/26 is acknowledged. Together with the Response to Restriction Requirements, Applicant amended Claims 5, 12, drawn to the elected invention, as well as Claims 17-20 (with Claims 16-20 drawn to the method of non-elected Invention II.
Traversal of the restriction requirement was based on Applicant’s comment stating examining both device and method claims would not be a serious burden.
The Examiner respectfully disagrees with Applicant’s comment and reminds Applicant the Restriction Requirement mailed 11/25/25 clearly explained three existing and commonly accepted grounds for showing the burden of examining both device and method claims. The Examiner notes, Applicant did not provide a single argument against any of the presented burden grounds.
Regarding non-chosen for initial examination method claims, the Examiner reminds Applicant (as it was stated in the Restriction Requirements) if the device claims are allowed, method claims will be considered for rejoinder, and method claims are commonly rejoined with allowed device claims if an independent method claim contains all limitations of an allowable independent device claim.
Applicant also has an option of filing a divisional application (as stated in the Applicant’ Response to Restriction Requirements), at least in the situation when the Applicant does not wish to repeat the limitations of the device claims in the method claims.
Status of Claims
Claims 16-20 are withdrawn from consideration as belonging to the invention not chosen for the examination.
Claims 1-15 are examined on merits herein.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “a plurality of memory films wrapped around the plurality of nanowires”, as Claim 1 recites, must be shown or the feature(s) canceled from the claim(s) – currently, in Figs. 3v-2 (where v is a letter in a range from D to K and number 2 is directed to a cross-sections in plane XY) – only a middle nanowire 108N is surrounded by memory films 116, while upper and lower nanowires 108N are not surrounded by memory films. Moreover, such presentation contradicts to Figs. 3v-3 (in cross-section ZX, in which all nanowires 108N are surrounded by memory films.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
Specification is objected to since it contains conflicting statements:
Paragraph 0031 of the published application (US 2024/0431099) recites that conductive vias 154 lands on a group of conductive lines 142E1 (or 142E2) and “may” penetrate through the lines of the group, while paragraphs 0055-0060, describing creation of conductive vias 154 (with references to Figs. 3L-3O), teach that each via penetrates all related conductive lines of a line group (such as a group comprising lines 142E1-1 and 142E1-2) and connects these lines together. Examiner suggests modifying paragraph 0031 at least by substituting a word “may” with a word: “and”, to avoid an uncertainty created by different statements.
Paragraph 0041, referring to Figs. 3D, states: “a memory film 116 and a gate electrode layer 124 are sequentially formed over the memory device” and further states that “The memory film 116 wraps around the nanowires”, while paragraph 0042 states that “The gate electrode layer 124 surrounds the memory film 116”. Please, be reminded that “wrapping around” and “forming over” are related to different dispositions of elements.
Please, note that the above-cited objections to the specification are mainly made because their inconsistencies are repeated by claims of the application.
Appropriate corrections/clarifications are required.
Claim Objections
Claims 9, 11, and 12 are objected to because of the following informalities:
Lines 7-8 of Claim 9 recites: “at least two drain lines that are electrically coupled to the at least two memory nanowires of the corresponding memory transistor”. Since the claim recites earlier that each memory transistor comprises at least two nanowires, but does not recite “a corresponding memory transistor”, Examiner suggests changing the above recitation to the following: “at least two drain lines that are electrically coupled to the at least two memory nanowires of a corresponding memory transistor”.
Lines 3-4 of Claim 11 have a recitation similar to the above recitation of Claim 9, but directed to source lines. Examiner suggests making a correction similar to that cited for Claim 9.
Lines 7-8 of Claim 12 recites: “between the gate electrode layer and the corresponding nanowire”. Examiner suggests changing the recitation to: “between the gate electrode layer and a corresponding nanowire”, in order to avoid a rejection for a lack of antecedent basis.
Appropriate corrections are required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In re Claim 1: Claim 1 recites (lines 3-4): “a plurality of memory films wrapping around the plurality of nanowires, respectively, wherein each of the memory films includes at least two dielectric layers”. The recitation is unclear, since it leads to questions: Is the cited plurality of memory films wrapped around the entire cited plurality of nanowires separated from (or connected to) each other with some means? Is the cited plurality of memory films wrapped around each nanowire of the cited plurality? Is one memory film wrapped around a corresponding one nanowire, and there is plurality of memory films corresponding to the plurality of nanowires? Claims 2-8, dependent on Claim 1, also do not clarify the wrapping arrangement.
Appropriate correction is required to clarify the cited limitation.
For this Office Action, based on paragraph 0027 of the specification of the published application (US 2024/0431099), the cited limitation was interpreted as: “a plurality of identical memory films corresponding to the plurality of nanowires, one of the identical memory films, comprised at least two dielectric layers, is wrapped around a respective nanowire”.
In re Claims 3, 4, and 5: Claim 3 recites: “a plurality of first conductive lines vertically stacked over the substrate and electrically coupled to first ends of the plurality of nanowires” (with a similar recitation for a plurality of second conductive lines), while Claim 4, dependent on Claim 3, recites: “the plurality of first conductive lines is divided into groups of source lines, and each of the groups comprises at least two source lines that are electrically connected to each other through a conductive via”. Claim 5 has a limitation similar to Claim 4, but for second conductive lines.
Combinations of the cited limitations of Claims 3 and 4 (and Claims 3 and 5) are unclear, since Claim 3 depends on Claim 1, which recites one gate electrode, e.g., Claim 1 is directed to one memory transistor, while Claims 4 and 5, citing groups of source and drain lines are directed to a plurality of memory transistors (see at least paragraph 0018 of the published application on a definition of a group of source lines and a group of drain lines), and as such, Claims 4 and 5 are directed to structures comprised a plurality of memory transistors, and, according, comprised a plurality of gate electrodes, which are not cited by Claims 1 and 3, on which Claims 4 and 5 depend.
Appropriate correction is required to clarify the claims language.
For this Office Action, the cited limitation of Claim 4 was interpreted as: “the plurality of first conductive lines defines a first group of source lines connected to one memory transistor of the memory device, where the memory device comprises a plurality of memory transistors, a plurality of gate electrodes, and a plurality of first groups of source lines”.
For this Office Action, the cited limitation of Claim 5 was interpreted as: “the plurality of second conductive lines defines a second group of drain lines connected to one memory transistor of the memory device, where the memory device comprises a plurality of memory transistors, a plurality of gate electrodes, and a plurality of second groups of drain lines”.
In re Claims 2-3 and 6-8: Claims 2-3 and 6-8 are rejected under 35 U.S.C. 112(b) due to dependency on Claim 1.
In re Claim 9: Lines 9-11 of Claim 9 recites: “a plurality of conductive vias landing on the groups of drain lines, respectively, wherein the at least two drain lines in each group are electrically connected to each other through the corresponding conductive via”. The recitation is not quite clear since leads to a question: Are all conductive vias landing on each group of drain lines or a one specified via is landed on a corresponding group of drain lines? How landing on a group of drain lines can lead to electrical connection of drain lines of the group, where drain lines of the same group (in the current application) are disposed on vertically different levels (see Figs. 1 and 2 and corresponding paragraphs of the specification).
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited limitation was interpreted as: “”.
In re Claim 12: Lines 3-5 of Claim 12 recite: “the first column of memory transistors comprises a plurality of memory films respectively surrounding the nanowires and a gate electrode layer over the plurality of memory films”. The recitation is unclear, since “the nanowires” are cited by Claim 9 (on which Claim 12 depends) as belonging to a plurality of memory transistors disposed in one column, while each memory transistor of the current application has an all-around gate electrode that surrounds nanowires of only one memory transistor (Abstract, paragraphs 0005, 0027, 0042).
Appropriate corrections are required to clarify the claim language.
For this Office Action, in view of the limitation of Claim 9: “each of the memory transistors in the first column comprises at last two nanowires”, the cited recitation of Claim 12 was interpreted as: “each of the at least two nanowires is surrounded by a corresponding memory film, and a gate electrode surrounds all memory films of one memory transistor”.
In re Claim 15: Claim 15 recites: “one of the conductive vias penetrates through the at least two drain lines in the corresponding group”. Since Claim 9, on which Claim 15 depends, is interpreted to have a similar recitation, Examiner suggests to amend Claim 15, to avoid in a future a rejection under 112(d) for absence of a limitation that further limits Claim 15 with respect to Claim 9.
In re Claims 10-11 and 13-14: Claims 10-11 and 13-14 are rejected under35 U.S.C. 112(b) due to dependency on Claim 9.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As far as the claims are understood, Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Fan et al. (EP 4,261,889) in view of Ryu et al. (US 2022/0122975).
In re Claim 1, Fan teaches a semiconductor memory device, comprising (Fig. 6; see also Figs. 14A-14H and paragraphs 0080-0125 directed to a method of the device manufacturing for a better understanding its structure)
a plurality of nanowires 63 (paragraph 0063) vertically stacked over a substrate 61 (paragraph 0063);
a plurality of memory films (one memory film being a gate dielectric 65, not shown in the figures, but described in paragraphs 0065, 0077) wrapping around the plurality of nanowires 63, respectively, wherein each of the memory films 65 (paragraph 0077 – on a memory function of 65) includes one dielectric layer 65;
a gate electrode layer 64 (paragraph 0063) surrounding the plurality of memory films 65; and
an isolation structure 68 and 24 (paragraphs 0078, 0106) encapsulating the gate electrode layer 64, wherein
the isolation structure 68, 24 is in direct contact with the gate electrode layer (at least because there is no space between the gate electrode 64 and insulation 68, while layer 24 may be deposited on the gate electrode 64) and the memory films (which abut dielectric 68, as in Figs. 14C-14G).
Fan does not teach that each memory film includes at least two dielectric layers – he teaches one dielectric layer capable to storage a charge (paragraph 0077).
Ryu teaches (Figs. 1-2) that a memory film, as a gate dielectric layer GD, may be created either from one dielectric film or from a combination of dielectric films, such as comprising at least two dielectric layers – silicon oxide and silicon nitride (paragraph 0026).
Fan and Ryu teach analogous arts directed to memory devices comprised memory transistors with channels being lateral nanowires, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Fan memory device in view of the Ryu’ memory device, since they are from the same field of endeavor, and Ryu created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Fan device by substituting its single-layer gate dielectric-memory film with a memory film comprising at least two dielectric layers (per Ryu), if such memory film is preferred for the manufacturer: See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 2, Fan/Ryu teaches the semiconductor memory device of Claim 1 as cited above, wherein, as it is shown for Claim 1, the at least two dielectric layers are a silicon oxide layer and a silicon nitride layer.
As far as the claims are understood, Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Fan/Ryu in view of Pang et al. (US 2018/0102375).
In re Claim 8, Fan/Ryu teaches the semiconductor memory device of Claim 1 as cited above, including the memory films, but does not teach, at least, explicitly, that each of the memory films further includes a metal layer, wherein the metal layer is sandwiched between the at least two dielectric layers of the memory film and in direct contact with the isolation structure.
Pang teaches a memory transistor (Fig. 5C, paragraphs 0075-0076 and 0079) comprising a metal layer as a floating gate 518 that is sandwiched between two dielectric layers 516 and 477.
Fan/Ryu and Pang teach analogous arts directed to memory devices with memory films comprised at least two dielectric layers, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Fan/Ryu device in view of the Pang device, since they are from the same field of endeavor, and Pang created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Fan/Ryu device by substituting its memory films comprised two dielectric layers with memory films each comprised a metal layer surrounded by the at least two dielectric layers (per Pang), when such memory films are desired for the manufacturer: See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
It would have been further obvious for one of ordinary skill in the art before filing the application to create the memory layer in direct contact with insulating layer 68 of Fan, similar to other layers of the memory film of Fan/Ryu, when identical lengths of all layers in the memory film simplifies the manufacturing procedure.
Allowable Subject Matter
Claims 3 and 9 (as interpreted) contain allowable subject matter, while Claims 4-7 depend on Claim 3 and Claims 10-15 depend on Claim 9.
Reason for Indicating Allowable Subject Matter
Re Claim 3: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitations of Claim 3 as: “a plurality of first conductive lines vertically stacked over the substrate and electrically coupled to first ends of the plurality of nanowires, respectively; and a plurality of second conductive lines vertically stacked over the substrate and electrically coupled to second ends of the plurality of nanowires, respectively”: Fan teaches a single source and a single drain coupled to a set of all nanowires of a single memory transistor – in spite of the fact that Fan’ nanowires are disposed at different levels, they are not contacted different conductive lines on one-to-one bases.
Ryu teaches “a plurality of first conductive lines vertically stacked over the substrate and electrically coupled to first ends of nanowires”, but he does not teach a plurality of second conductive lines vertically stacked and electrically coupled to second ends of nanowires. Moreover, and more importantly, each of the Ryu’ conductive lines is connected to different memory transistors stacked on different levels, while vertically each of stacked first and second conductive lines of Claim 3 of the current application are connected to one nanowire of a same memory transistor.
Barraud (US 2022/0415967), also teaching a memory device comprised nanowire memory transistors, where the memory transistors are disposed in a 3D structure, and teaching a plurality of first and second conductive lines connected to source and drain regions of memory transistors, do not compensate the above-cited deficiency of Fan/Ryu, since his first and second conductive lines are not disposed as vertical stacks – each plurality oof first and second conductive lines are disposed laterally with respect to each other.
Wu et al. (US 2020/0066741), teaching a memory device with GAA (gate-all-around) structure for a memory transistor, also does not compensate the above-cited deficiency, as well as Liaw (US 2024/0008241), Ye et al. (US 2024/0405089), Barraud (NPL), or Sim (NPL).
Re Claim 9: The prior arts of record cited above, fail(s) to anticipate or render obvious such limitation of Claim 9 (as interpreted) as: “a second column of drain lines stacked in the respective levels in the vertical direction”, where “the nanowires of the memory transistors are stacked in respective levels”, and: “a plurality of conductive vias, each conductive via landing on and passing through a corresponding group of drain lines, wherein the at least two drain lines in the corresponding drain line group are electrically connected to each other through this conductive via” (e.g., in accordance with the claim interpretation), in combination with other limitations of Claim 9.
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 02/11/26