DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-15 are cancelled. Claims 21-35 are new, no new matter is present. Claims 16-35 are present for examination.
Information Disclosure Statement
The information disclosure statement (IDS) filed on June 21, 2023 has been considered by the examiner.
Election/Restrictions
Claims 1-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected device, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on October 16, 2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-17 and 20-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The following terms; “first semiconductor strips”, “second semiconductor strips” in claims 16-17 and 20 is a relative term which renders the claim indefinite. The term “strips” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
For purposes of examination, (I) “first semiconductor strips” is being interpreted as “first semiconductor stack strips” and (II) “second semiconductor strips” is being interpreted as “second semiconductor stack strips”
The following terms; “ a plurality of first strips”, “ a plurality of second strips” in claim 21 is a relative term which renders the claim indefinite. The term “strips” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
For purposes of examination, (I) “ a plurality of first strips” is being interpreted as “a plurality of first semiconductor stack strips” and (II) “a plurality of second strips” is being interpreted as “a plurality of second semiconductor stack strips”
Allowable Subject Matter
Claims 26-35 are allowed.
The following is an examiner’s statement of reasons for allowance:
The closest prior art of record, Cheng (US 2021/0193828 A1), Wu (US 2016/0005617 A1), fails to disclose the following limitations in combination with the rest of the claim.
Claim 26 (from which claims 27-35 depend), forming a first gate structure wrapping around the first semiconductor layer, wherein the first gate structure has a cross pattern when viewed from a top view; and forming a second gate structure wrapping around the second semiconductor layer, wherein the second gate structure has a cross pattern when viewed from a top view, the insulator layer is vertically between the first gate structure and the second gate structure.
Wu discloses a method of forming an integrated circuit device (method 100 is used to form a device, [0013], Figs. 1 and 18a-18b), comprising:
forming a first semiconductor layer (material layer 216 is a first semiconductor layer, [0016], Fig. 1), an insulator layer (second spacer layer 222 is an insulator layer, [0023], Fig. 1) and a second semiconductor layer (material layer 226 is a second semiconductor layer, [0026], Figs. 1) over a substrate in sequence (substrate 202 includes 216, 222, and 226 formed over 214 in sequence, Fig. 18b).
Wu does not explicitly disclose the following limitations; forming a first gate structure wrapping around the first semiconductor layer, wherein the first gate structure has a cross pattern when viewed from a top view; and forming a second gate structure wrapping around the second semiconductor layer, wherein the second gate structure has a cross pattern when viewed from a top view, the insulator layer is vertically between the first gate structure and the second gate structure.
Claims 18-20 and 22-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 16 (from which claims 17-20 depend), patterning the stack by a lithography process using a first grid-shaped mask such that the stack comprises a plurality of first semiconductor stack strips along a first direction and a plurality of second semiconductor stack strips along a second direction crossing the first direction; recessing the plurality of first semiconductor stack strips; and growing first epitaxial source/drain regions from the recessed plurality of first semiconductor strips.
Cheng discloses a method of forming an integrated circuit device (semiconductor device 100 is an integrated circuit device, Figs. 1A-1E, wherein 100 is formed via method 200, [0065], Fig. 2), comprising:
forming a stack on a substrate (fin structures 108 are composed of fin base portions 108A and stacked fin portions 108B wherein 108 is a stack formed on a substrate 106, [0066], Fig. 3B); and
patterning the stack 108 by a lithography process (108 is patterned via a photolithography process, [0036], Fig. 1A).
Regarding claim 21 (from which claims 22-25 depend), a plurality of first strips extending along a first direction; and a plurality of second strips along a second direction, and wherein the second direction crosses the first direction.
Cheng discloses a method of forming an integrated circuit device (semiconductor device 100 is an integrated circuit device, Figs. 1A-1E, wherein 100 is formed via method 200, [0065], Fig. 2), comprising:
forming a semiconductor nanostructure over a substrate (fin structures 108 are composed of fin base portions 108A and stacked fin portions 108B wherein 108 is a semiconductor nanostructure formed over a substrate 106, [0066], Fig. 3B), wherein the semiconductor nanostructure 108 includes:
forming a gate dielectric layer (gate dielectric layer 112B, [0049], Figs. 1B and 1C) wrapping around the semiconductor nanostructure 108 (112B is formed wrapping around 108, [0049], Figs. 1A-1C); and
forming a gate electrode over the gate dielectric layer (gate electrode 112C is formed over 112B, [0049], Figs. 1A-1C).
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812