Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Applicant Election filled on 12/11/2025. Currently, claims 1-20 are pending in the application. Claims 3, 6-7 and 16 have been withdrawn from consideration.
Election/Restrictions
Applicant's election without traverse of Species IV (Figures 5A, 8A-8B and 13A-13H), claims 1-2, 4-5, 8-15 and 17-20 with traverse, in the reply filed on 12/11/2025 is acknowledged, there being no allowable generic or linking claim.
The first traversal is on the ground(s) that the examination of all of claims 1-20 would not present an undue burden on the Examiner since the listed species is sufficiently related such that a search for the subject matter of any one of these species would encompass a search for the subject matter of the remaining species.
This is not found persuasive and the Examiner has already established burden (as defined in M.P.E.P. 808.02) in the restriction requirement dated 10/23/2025. There is a search and/or examination burden for the patentably distinct species or device/method claims, wherein they require a different field of search (e.g., searching different classes/subclasses or electronic resources or non-patent language, or deploying different search queries); and/or the prior art applicable to one invention would not likely be applicable to another; and/or the inventions are likely to raise different non-prior art issues under 35 U.S.C 101 and/or 35 U.S.C 112, first paragraph. Therefore, the requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 11-14 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al (US 20210098473 A1).
Regarding claim 1, Figure 1 of Lin discloses a memory device, comprising:
a static random-access memory (SRAM, [0024]) cell over a substrate (201, [0029]), wherein the SRAM cell comprises:
a first inverter having a first pull-down transistor (PD-1, n-type transistor) and a first pull-up transistor (PU-1, p-type transistor, [0024]); and
a second inverter having a second pull-down transistor (PD-2) and a second pull-up transistor (PU-2, [0024]), wherein the first inverter and the second inverter are cross-coupled to each other (the first inverter and the second inverter are cross-coupled to each other in a SRAM based on Figure 1), wherein each of the first pull-down transistor, the first pull-up transistor, the second pull-down transistor, and the second pull-up transistor comprises:
active channel layers (108, [0025]) vertically stacked, wherein a number of the active channel layers of the first pull-up transistor is less than a number of the active channel layers of the first pull-down transistor or the second pull-down transistor (pull-up transistors are in region 204 ,and pull-down transistors are in region 202 and number of channels 108 is less in region 204 than the number of channels in region 202).
Regarding claim 11, Figure 1 of Lin discloses a memory device, comprising:
a static random-access memory (SRAM, [0024]) cell over a substrate, wherein the SRAM cell comprises:
a first pull-down transistor (PD-1, [0024]) and a first pull-up transistor (PU-1) sharing a first gate structure (120A) extending in an X-direction; and
a second pull-down transistor (PD-2, [0024]) and a second pull-up transistor (PU-2) sharing a second gate structure (120B) extending in the X-direction, wherein each of the first pull-down transistor, the first pull-up transistor, the second pull-down transistor, and the second pull-up transistor comprises: nanostructures (108, [0025]) vertically stacked in a Z-direction; and
source/drain features (not shown in Figure 1; please see Figure 10 for 226, [0049]) attached to the nanostructures in a Y-direction (source/drain features are formed at an end of the nanostructure 108 in Figure 1, [0027]), wherein a distance from a topmost surface to a bottommost surface of the nanostructures of the first pull-up transistor (PU-1) is less than a distance from a topmost surface to a bottommost surface of the nanostructures of the first pull-down transistor (PD-1) or the second pull-down transistor (pull up transistors are in region 204 and pull-down transistors are in region 202).
Regarding claim 12, Figure 1 of Lin discloses that the memory device of claim 11, wherein bottom surfaces of the source/drain features (not shown in Figure 1, please see Figure 10 for 226) of the first pull-down transistor and the second pull-down transistor are lower than bottommost surfaces of the first gate structure and the second gate structure (not shown in Figure 1, please see Figure 10).
Regarding claim 13, Figure 1 of Lin discloses that the memory device of claim 11, further comprising: isolation layers (224, [0044]) on opposite sides of the first gate structure (120A, [0024]) and the second gate structure (120B), wherein the source/drain features (not shown in Figure 1, please see Figure 10 for 226) are separated from the substrate (201) by the isolation layers (224) in the Z-direction.
Regarding claim 14, Figure 1 of Lin discloses that the memory device of claim 13, wherein the source/drain features (not shown in Figure 1, please see Figure 10 for 226) are separated from the isolation layers (224) in the Z-direction.
Regarding claim 17, Figure 1 of Lin discloses a memory device, comprising:
a static random-access memory (SRAM) cell ([0024]) comprising a first pass-gate transistor (PG-1, [0024]), a second pass-gate transistor (PG-2), a first pull-down transistor (PD-1, [0024]), a second pull-down transistor (PD-2), a first pull-up transistor (PU-1), and a second pull-up transistor (PU-2), wherein each of the first pass-gate transistor, the second pass-gate transistor, the first pull-down transistor, the second pull-down transistor, the first pull-up transistor, and the second pull-up transistor comprises:
active channel layers (108, [0025]) vertically stacked in a Z-direction;
source/drain features (not shown in Figure 1; please see Figure 10 for 226, [0049]) on opposite sides of the active channel layers (108) in a Y-direction; and
isolation layers (224, [0044]) under the source/drain features in the Z-direction, wherein a number of the active channel layers (108) of the first pull-up transistor is less than a number of the active channel layers of the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor, or the second pass-gate transistor (pull-up transistors are in region 204, and pull-down and the pass gate transistors are in region 202, and number of channel 108 is less in region 204 than the number of channels in region 202).
Regarding claim 18, Figure 1 of Lin discloses that the memory device of claim 17, wherein each of the first pass-gate transistor (PG-1, [0024]), the second pass-gate transistor (PG-2), the first pull-down transistor (PD-1), the second pull-down transistor (PD-2), the first pull-up transistor (PU-1), and the second pull-up transistor (PU-2, [0024]) further comprises: isolation layers (224, [0044]) over a substrate (201, [0029]), wherein the source/drain features (not shown in Figure 1, please see Figure 10 for 226) are separated from the substrate (201) by the isolation layers in the Z-direction.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 4-5 and 8 are rejected under 35 U.S.C. 103 as being obvious over Lin et al (US 20210098473 A1) in view of Chang et al (US 20210098304 A1).
Regarding claim 2, Figure 1 of Lin discloses that the memory device of claim 1, wherein each of the first pull-down transistor (PD-1), the first pull-up transistor (PU-1), the second pull-down transistor (PD-2), and the second pull-up transistor (PU-2) further comprises: source/drain features (not shown in Figure 1; please see Figure 10 for 226, [0049]) on opposite sides of the active channel layers (108).
Lin does not teach wherein bottom surfaces of the source/drain features of the first pull-down transistor (PD-1, n-type transistors, [0024]) and the second pull-down transistor (PD-2, [0024]) are lower than bottom surfaces of the source/drain features of the first pull-up transistor (PU-1) and the second pull-up transistor (PU-2, p-type transistors, [0024]).
However, Chang is a pertinent art which teaches p-type and n-type transistors used in SRAM, wherein Figure 12 of Chang teaches a n-type transistor having source/drain feature (240A) with lower bottom surface than a source/drain feature (240B) of a p-type transistor ([0035]) for improved performance ([0049]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lin such that bottom surfaces of the source/drain features of the first pull-down transistor (PD-1, n-type transistors, [0024]) and the second pull-down transistor (PD-2, [0024]) are lower than bottom surfaces of the source/drain features of the first pull-up transistor (PU-1) and the second pull-up transistor (PU-2, p-type transistors, [0024]) according to the teaching of Chang for improved performance with lower cost ([0002] and [0049]).
Regarding claim 4, Figure 1 of Lin discloses that the memory device of claim 2, wherein each of the first pull-down transistor (PD-1, [0024]), the first pull-up transistor (PD-1), the second pull-down transistor (PD-2), and the second pull-up transistor (PU-2) further comprises: isolation layers (224, [0044]) vertically sandwiched between the source/drain features (not shown in Figure 1, please see Figure 10 for 226) and the substrate (201).
Regarding claim 5, Figure 1 of Lin discloses that the memory device of claim 4, wherein a thickness of the isolation layers (224) of the first pull-up transistor (PU-1 in region 204) and the second pull-up transistor (PU-2) is greater than a thickness of the isolation layers of the first pull-down transistor (in region 202) and the second pull-down transistor (PD-2, [0024]).
Regarding claim 8, Figure 1 of Lin does not teach that the memory device of claim 4, wherein each of the first pull-down transistor, the first pull-up transistor, the second pull-down transistor, and the second pull-up transistor further comprises: air gaps separating the source/drain features (226, please see Figure 10) from the isolation layers (224).
However, Chang is a pertinent art which teaches p-type and n-type transistors used in SRAM, wherein Figure 12 of Chang teaches transistor having air gaps (AG1 and AG2, [0037]) between the source/drain feature (240) and isolation layer (222, [0024]) for improved performance ([0049]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lin such that each of the first pull-down transistor, the first pull-up transistor, the second pull-down transistor, and the second pull-up transistor further comprises: air gaps separating the source/drain features (226, please see Figure 10 of Lin) from the isolation layers (224) according to the teaching of Chang for improved performance with lower cost ([0002] and [0049]).
Claims 9-10 are rejected under 35 U.S.C. 103 as being obvious over Lin et al (US 20210098473 A1) in view of Chang et al (US 20210098304 A1) as applied to claim 4 above, and further in view of ZHENG et al (US 20210296323 A1).
Regarding claim 9, Figure 1 of Lin in view of Chang do not teach that the memory device of claim 4, wherein each of the first pull-up transistor (PU-1) and the second pull-down transistor (PD-2) further comprises: an inactive channel layer under the active channel layers (108).
However, ZHENG is a pertinent art which teaches a SRAM device with six transistors, wherein Figure 7 of ZHENG teaches of having inactive channels (714) under active channels (715) ([0085]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the memory device of Lin in view of Chang such that each of the first pull-up transistor (PU-1) and the second pull-down transistor (PD-2) further comprises: an inactive channel layer under the active channel layers according to the teaching of ZHENG in order to optimize performance with improved device with smallest dimension ([0002-[0004] of ZHENG).
Regarding claim 10, Figure 1 of Lin in view of Chang and ZHENG teaches that the memory device of claim 9, wherein top surfaces of the isolation layers of the first pull-up transistor and the second pull-up transistor are higher than top surfaces of the inactive channel layers (please see Figure 12C of Chang that the top surfaces of the isolation layers 222 are higher in the right region than top surfaces in the left region).
Claims 15 and 19 are rejected under 35 U.S.C. 103 as being obvious over Lin et al (US 20210098473 A1) in view of ZHENG et al (US 20210296323 A1).
Regarding claims 15 and 19, Figure 1 of Lin does not teach that the memory device of claim 13, wherein each of the first pull-up transistor and the second pull-up transistor further comprises: a non-functional nanostructure between a bottommost surface of the nanostructures and the substrate in the Z-direction. Or
The memory device of claim 18, wherein each of the first pass-gate transistor, the second pass-gate transistor, the first pull-down transistor, the second pull-down transistor, the first pull-up transistor, and the second pull-up transistor further comprises: an inactive channel between the isolation layers in the Y-direction.
However, ZHENG is a pertinent art which teaches a SRAM device with six transistors, wherein Figure 7 of ZHENG teaches of having inactive channels (714) under active channels (715) ([0085]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the memory device of Lin that wherein each of the first pull-up transistor and the second pull-up transistor further comprises: a non-functional nanostructure between a bottommost surface of the nanostructures and the substrate in the Z-direction or wherein each of the first pass-gate transistor, the second pass-gate transistor, the first pull-down transistor, the second pull-down transistor, the first pull-up transistor, and the second pull-up transistor further comprises: an inactive channel between the isolation layers in the Y-direction according to the teaching of ZHENG in order to optimize performance with improved device with smallest dimension ([0002-[0004] of ZHENG).
Claim 20 is rejected under 35 U.S.C. 103 as being obvious over Lin et al (US 20210098473 A1) in view of ZHENG et al (US 20210296323 A1) as applied to claim 19 above, and further in view of Chang et al (US 20210098304 A1).
Regarding claim 20, Figure 1 of Lin in view of ZHENG do not teach that the memory device of claim 19, wherein each of the first pass-gate transistor (PG-1, [0024]), the second pass-gate transistor (PG-2), the first pull-down transistor (PD-1), the second pull-down transistor (PD-2), the first pull-up transistor (PU-1), and the second pull-up transistor (PU-2) further comprises: air gaps between the source/drain features (226) and the isolation layers (224) in the Z-direction.
However, Chang is a pertinent art which teaches p-type and n-type transistors used in SRAM, wherein Figure 12 of Chang teaches transistor having air gaps (AG1 and AG2, [0037]) between the source/drain feature (240) and isolation layer (222, [0024]) for improved performance ([0049]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lin in view of ZHENG such that each of the first pass-gate transistor (PG-1, [0024]), the second pass-gate transistor (PG-2), the first pull-down transistor (PD-1), the second pull-down transistor (PD-2), the first pull-up transistor (PU-1), and the second pull-up transistor (PU-2) further comprises: air gaps between the source/drain features and the isolation layers in the Z-direction according to the teaching of Chang for improved performance with lower cost ([0002] and [0049] of Chang).
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
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/KHAJA AHMAD/Primary Examiner, Art Unit 2813