Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the filing of the Applicant Arguments/Remarks Made in an Amendment on 05/15/2026. Currently, claims 1-8 and 10-21 are pending in the application. Claims 3, 6-7 and 16 have been withdrawn from consideration. Claim 9 has been cancelled.
Claim Objections
Claim 10 is objected to because of the following informalities: Where it recites “The memory device of claim 9” in line 1 should be “The memory device of claim 4” since claim 9 has been cancelled. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4 and 10 are rejected under 35 U.S.C. 103 as being obvious over Liaw (US 20210159232 A1) in view of ZHENG et al (US 20210296323 A1).
Regarding claim 1, Figures 1-2 of Liaw disclose a memory device, comprising:
a static random-access memory (SRAM) cell over a substrate (201, [0027]), wherein the SRAM cell comprises:
a first inverter having a first pull-down transistor (PD-1, [0021]) and a first pull-up transistor (PU-1, [0021]); and
a second inverter having a second pull-down transistor (PD-2, 0021]) and a second pull-up transistor (PU-2, [0021]), wherein the first inverter and the second inverter are cross-coupled to each other (please see Figure 1), wherein each of the first pull-down transistor, the first pull-up transistor, the second pull- down transistor, and the second pull-up transistor comprises: active channel layers (255, 253, 255, [0027]) vertically stacked.
Liaw does no teach that wherein a number of the active channel layers of the first pull-up transistor is less than a number of the active channel layers of the first pull-down transistor or the second pull-down transistor, wherein the first pull-up transistor and the second pull-up transistor comprise: inactive channel layers under the active channel layers of the first pull-up transistor and the second pull-up transistor, wherein the inactive channel layers and the active channel layers have the same semiconductor material.
However, ZHENG is a pertinent art which teaches a SRAM cell, where Figure 9-10 of ZHENG teaches that the pull up transistor having less active channel layers than a pull down transistor, wherein the pull up transistors comprising active channel and inactive channels (depopulated channels) under the active channel (Figure 10B) for appropriate driving current for different devices ([0030]-[0033]). ZHENG, further , teaches of making an inactive channel (depopulated channels) by using depopulation dopant ([0046]) or using an insulator under the source/drain regions to make inactive channel (Figure 5A, 515 in 502 is inactive, [0072]-[0074]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the memory device wherein a number of the active channel layers of the first pull-up transistor is less than a number of the active channel layers of the first pull-down transistor or the second pull-down transistor, wherein the first pull-up transistor and the second pull-up transistor comprise: inactive channel layers under the active channel layers of the first pull-up transistor and the second pull-up transistor, wherein the inactive channel layers and the active channel layers have the same semiconductor material according to the teaching of ZHENG for modulation of drive currents in different devices, which may be needed for different circuits ([0033] of ZHENG).
Regarding claim 2, Figures 1-2 of Liaw in view of ZHENG teach that the memory device of claim 1, wherein each of the first pull-down transistor, the first pull-up transistor, the second pull-down transistor, and the second pull-up transistor further comprises: source/drain features on opposite sides of the active channel layers, wherein bottom surfaces of the source/drain features of the first pull-down transistor and the second pull-down transistor are lower than bottom surfaces of the source/drain features of the first pull-up transistor and the second pull-up transistor (Figure 5A of ZHENG teaches that the pull up transistor has lower channel inactive due to the presence of isolation layer 502 and hence the bottom surface of the source/drain features of the first pull-down transistor and the second pull-down transistor are lower than bottom surfaces of the source/drain features of the first pull-up transistor and the second pull-up transistor).
Regarding claim 4, Figures 1-2 of Liaw in view of ZHENG teach that the memory device of claim 2, wherein each of the first pull-down transistor, the first pull-up transistor, the second pull-down transistor, and the second pull-up transistor further comprises: isolation layers vertically sandwiched between the source/drain features and the substrate (Figure 5A of ZHENG teaches isolation layer 502 vertically sandwiched between the source/drain features 505 and the substrate 501).
Regarding claim 10, Figures 1-2 of Liaw in view of ZHENG teach that the memory device of claim 4, wherein top surfaces of the isolation layers of the first pull-up transistor and the second pull-up transistor are higher than top surfaces of the inactive channel layers (Figure 5A of ZHENG teaches isolation layer 502 vertically sandwiched between the source/drain features 505 and the substrate 501, wherein top surface of 502 is higher than the top surface of the inactive channel 515 in the 502 layer).
Claims 5 and 8 are rejected under 35 U.S.C. 103 as being obvious over Liaw (US 20210159232 A1) in view of ZHENG et al (US 20210296323 A1) as applied to claim 4 above, and further in view of Chang et al (US 20210098304 A1).
Regarding claims 5 and 8, Figures 1-2 of Liaw in view of ZHENG do not teach that the memory device of claim 4, wherein a thickness of the isolation layers of the first pull-up transistor and the second pull-up transistor is greater than a thickness of the isolation layers of the first pull-down transistor and the second pull-down transistor. Or
The memory device of claim 4, wherein each of the first pull-down transistor, the first pull-up transistor, the second pull-down transistor, and the second pull-up transistor further comprises: air gaps separating the source/drain features from the isolation layers.
However, Chang is a pertinent art which teaches transistors used for devices such as SRAM, wherein Figures 12-14 of Chang teach of forming isolation layers (222A and air gaps) between bottommost surfaces of the source/drain features (240) and the substrate (202) in a cross-section view for improved performance with ease of fabrication ([0002], [0049] and [0052]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the memory device of Liaw in view of ZHENG as claimed above according to the teaching of Chang in order to form a memory device with improved performance and ease of fabrication and lower the cost ([0002], [0049] and [0052] of Chang).
Claims 11-15 and 17-21 are rejected under 35 U.S.C. 103 as being obvious over Liaw (US 20210159232 A1) in view of Chang et al (US 20210098304 A1) and ZHENG et al (US 20210296323 A1).
Regarding claim 11, Figures 1-2 of Liaw teach a memory device, comprising:
a static random-access memory (SRAM) cell over a substrate (201, [0027]), wherein the SRAM cell comprises:
a first pull-down transistor (PD-1) and a first pull-up transistor (PU-1) sharing a first gate structure (230, [0027])) extending a first direction (X, left to right); and
a second pull-down transistor (PD-2) and a second pull-up (PU-2) transistor sharing a second gate structure (235) extending in the first direction (X), wherein each of the first pull-down transistor, the first pull-up transistor, the second pull- down transistor, and the second pull-up transistor comprises: nanostructures (255, 253, 255, [0027]) vertically stacked in a second direction different from the first direction (Y, front to back); and
source/drain features (250) attached to the nanostructures in a third direction (Z, upwards) different from the first direction and the second direction.
Liaw does not teach isolation layers between bottommost surfaces of the source/drain features and the substrate in a cross-section view.
However, Chang is a pertinent art which teaches transistors used for devices such as SRAM, wherein Figures 12-14 of Chang teach of forming isolation layers (222A and air gaps) between bottommost surfaces of the source/drain features (240) and the substrate (202) in a cross-section view for improved performance with ease of fabrication ([0002], [0049] and [0052]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the memory device of Liaw by having isolation layers between bottommost surfaces of the source/drain features and the substrate in a cross-section view in order to form a memory device with improved performance and ease of fabrication and lower the cost ([0002], [0049] and [0052] of Chang).
Liaw, further does not teach wherein a distance from a topmost surface to a bottommost surface of the nanostructures of the first pull-up transistor is less than a distance from a topmost surface to a bottommost surface of the nanostructures of the first pull-down transistor or the second pull-down transistor.
However, ZHENG is a pertinent art which teaches a SRAM cell, where Figure 9-10 of ZHENG teaches that the pull up transistor having less active channel layers than a pull down transistor, wherein the pull up transistors comprising active channel and inactive channels (depopulated channels) under the active channel (Figure 10B) for appropriate driving current for different devices ([0030]-[0033]). ZHENG, further , teaches of making an inactive channel (depopulated channels) by using depopulation dopant ([0046]) or using an insulator under the source/drain regions to make inactive channel (Figure 5A, 515 in 502 is inactive, [0072]-[0074]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the memory device with pull-up transistor with less channel, wherein a distance from a topmost surface to a bottommost surface of the nanostructures of the first pull-up transistor is less than a distance from a topmost surface to a bottommost surface of the nanostructures of the first pull-down transistor or the second pull-down transistor according to the teaching of ZHENG for modulation of drive currents in different devices, which may be needed for different circuits ([0033] of ZHENG).
Regarding claim 12, Figures 1-2 of Liaw in view of Chang and ZHENG teach that the memory device of claim 11, wherein bottom surfaces of the source/drain features of the first pull-down transistor and the second pull-down transistor are lower than bottommost surfaces of the first gate structure and the second gate structure (Figure 5 and 10 of ZHENG teach pull down transistor having this feature).
Regarding claim 13, Figures 1-2 of Liaw in view of Chang and ZHENG teach that the memory device of claim 11, wherein the isolation layers are on opposite sides of the first gate structure and the second gate structure (Figure 5 of ZHENG teaches isolation layer at the bottom of source/drain feature and, further Figures 12-14 of Chang teach of forming isolation layers on opposite sides of the gate structure).
Regarding claim 14, Figures 1-2 of Liaw in view of Chang and ZHENG teach that the memory device of claim 13, wherein the source/drain features are separated from the isolation layers in the second direction (Figures 12-14 of Chang teach source/drain features are separated from the isolation layers).
Regarding claim 15, Figures 1-2 of Liaw in view of Chang and ZHENG teach that the memory device of claim 13, wherein each of the first pull-up transistor and the second pull-up transistor further comprises: a non-functional nanostructure between a bottommost surface of the nanostructures and the substrate in the second direction (Figures 5 and 10 of ZHENG teach a non-functional nanostructure (deactivated channel) between a bottommost surface of the nanostructures).
Regarding claim 17, Figures 1-2 of Liaw teach a memory device, comprising:
a static random-access memory (SRAM) cell comprising a first pass-gate transistor (PG-1), a second pass-gate transistor (PG-2), a first pull-down transistor (PD-1), a second pull-down transistor (PD-2), a first pull- up transistor (PU-1), and a second pull-up transistor (PU-2), wherein each of the first pass-gate transistor, the second pass-gate transistor, the first pull-down transistor, the second pull-down transistor, the first pull-up transistor, and the second pull-up transistor comprises:
active channel layers (255, 253, 255, [0027]) vertically stacked;
source/drain features (250) on opposite sides of the active channel layers in a first direction (Z direction, UP direction); and
a source/drain contact (nodes, Figure 2) extending in a second direction (X direction) different from the first direction, wherein the source/drain contact are over and electrically connected to the source/drain features of the second pull-up transistor and the second pull-down transistor; and a contact over and electrically connected to the source/drain contact and a gate structure shared by the first pull-up transistor and the first pull-down transistor ([0023], Figures 1-2).
Liaw does not teach an isolation layers under the source/drain features.
However, Chang is a pertinent art which teaches transistors used for devices such as SRAM, wherein Figures 12-14 of Chang teach of forming isolation layers (222A and air gaps) between bottommost surfaces of the source/drain features (240) and the substrate (202) in a cross-section view for improved performance with ease of fabrication ([0002], [0049] and [0052]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the memory device of Liaw by having isolation layers between bottommost surfaces of the source/drain features and the substrate in a cross-section view in order to form a memory device with improved performance and ease of fabrication and lower the cost ([0002], [0049] and [0052] of Chang).
Liaw does not teach wherein a number of the active channel layers of the first pull-up transistor is less than a number of the active channel layers of the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor, or the second pass-gate transistor.
However, ZHENG is a pertinent art which teaches a SRAM cell, where Figure 9-10 of ZHENG teach that the pull up transistor having less active channel layers than a pull down transistor, wherein the pull up transistors comprising active channel and inactive channels (depopulated channels) under the active channel (Figure 10B) for appropriate driving current for different devices ([0030]-[0033]). ZHENG, further , teaches of making an inactive channel (depopulated channels) by using depopulation dopant ([0046]) or using an insulator under the source/drain regions to make inactive channel (Figure 5A, 515 in 502 is inactive, [0072]-[0074]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the memory device wherein a number of the active channel layers of the first pull-up transistor is less than a number of the active channel layers of the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor, or the second pass-gate transistor according to the teaching of ZHENG for modulation of drive currents in different devices, which may be needed for different circuits ([0033] of ZHENG).
Regarding claim 18, Figures 1-2 of Liaw in view of Chang and ZHENG teach that the memory device of claim 17, wherein each of the first pass-gate transistor (PG-1), the second pass-gate transistor (PG-2), the first pull-down transistor (PD-1), the second pull- down transistor (PD-2), the first pull-up transistor (PU-1), and the second pull-up transistor (PU-2) further comprises: isolation layers over a substrate, wherein the source/drain features are vertically separated from the substrate by the isolation layers (Figure 5 of ZHENG teaches isolation layer at the bottom of source/drain feature and, further Figures 12-14 of Chang teach of forming isolation layers on opposite sides of the gate structure).
Regarding claim 19, Figures 1-2 of Liaw in view of Chang and ZHENG teach that the memory device of claim 18, wherein each of the first pass-gate transistor, the second pass-gate transistor, the first pull-down transistor, the second pull- down transistor, the first pull-up transistor, and the second pull-up transistor further comprises: an inactive channel between the isolation layers in the second direction (Figure 5/10 of ZHENG teaches isolation layer at the bottom of source/drain feature with inactive channel, and further Figures 12-14 of Chang teach of forming isolation layers on opposite sides of the gate structure).
Regarding claim 20, Figures 1-2 of Liaw in view of Chang and ZHENG teach that the memory device of claim 19, wherein each of the first pass-gate transistor, the second pass-gate transistor, the first pull-down transistor, the second pull- down transistor, the first pull-up transistor, and the second pull-up transistor further comprises: air gaps between the source/drain features and the isolation layers (Figures 12-14 of Chang teach of forming isolation layers and air gaps on opposite sides of the gate structure).
Regarding claim 21, Figures 1-2 of Liaw in view of Chang and ZHENG teach that the memory device of claim 11, wherein the cross-section view is along the second direction (Y direction, Figures 1-2 of Liaw).
Response to Arguments
Applicant’s arguments/amendments regarding the rejection of claims 1, 11 and 17, filed on 05/15/2026, have been fully considered but arguments are moot because newly added limitation to the claim (s) requires a new ground of rejection necessitated by amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday to Friday from 8:00 AM to 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/
Primary Examiner, Art Unit 2813
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