DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The present amendment, filed on or after 3/4/2026, has been entered. The Applicant has amended claims 1, 11, 17, and 21. Claims 18-20 were withdrawn due to restriction requirement by the Applicant. Accordingly, claims 1-17 and 21-23 remain pending in the application.
Applicant’s amendment to the title has overcome the title objection previously set forth in the Non-Final Office Action mailed on 12/1/ 2025.
Information Disclosure Statement
The information disclosure statement submitted on 3/23/2026 is considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 6-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang Embodiment 1 (US 2021/0134794 A1, Embodiment 1, where the first gate electrode 214 and second gate electrode are formed from the material; [0063] and [0071]: p-type titanium nitride).
Regarding claim 1, Huang Embodiment 1 teaches a method of manufacturing (Figs. 4-26, [0006]) a semiconductor device (NFET device, Fig. 1, [0014]), comprising:
forming a first stack of nanostructures (third nanosheet channel structures 206, Fig. 15, [0057]) spaced vertically one from another in a first region (above third fin structure 116, Fig. 15, [0057]) of the semiconductor device (NFET device, Fig. 15), a second stack of nanostructures (second nanosheet channel structures 204, Fig. 15, [0057]) spaced vertically one from another in a second region (above second fin structure 114, Fig. 15, [0057]) of the semiconductor device (NFET device, Fig. 15), and a third stack of nanostructures (first nanosheet channel structures 202, Fig. 15, [0057]) spaced vertically one from another in a third region (above first fin structure 112, Fig. 15, [0057]) of the semiconductor device (NFET device, Fig. 15);
depositing (Fig. 20, [0063]: “deposition process”) a first work function layer (first gate electrode 214 after etching the first conductive layer 2002, Fig. 20, [0063]: “the first conductive layer 2002 comprises a conductive material … that is a p-type work function metal (e.g., titanium nitride, tungsten carbon nitride, tungsten, tantalum nitride, etc.), …”) wrapping around each of the nanostructures (first nanosheet channel structures 202, second first nanosheet channel structures 204, third nanosheet channel structures 206, Fig. 20) in the first (above third fin structure 116, Fig. 20), second (above second fin structure 114, Fig. 20), and third regions (above first fin structure 112, Fig. 20);
removing the first work function layer (first gate electrode 214, Fig. 21) from the first (above third fin structure 116, Fig. 21) and second regions (above second fin structure 114, Fig. 21);
depositing (Fig. 23, [0071]: “deposition process”) a second work function layer (second gate electrode 216 after etching the second conductive layer 2302, Fig. 23, [0071]: “the second conductive layer 2302 comprises a conductive material … that is a p-type work function metal (e.g., titanium nitride, tungsten carbon nitride, tungsten, tantalum nitride, etc.), …”) wrapping around (from sides and top) each of the nanostructures (third nanosheet channel structures 206, second first nanosheet channel structures 204, first nanosheet channel structures 202, Fig. 23) in the first (above third fin structure 116, Fig. 23) and second regions (above second fin structure 114, Fig. 23) and over the first work function layer (first gate electrode 214, Fig. 23) in the third region (above first fin structure 112, Fig. 23), wherein an interface between the second work function layer (second gate electrode 216, Fig. 23) and the first work function layer (first gate electrode 214, Fig. 23) in the third region (above first fin structure 112, Fig. 23) is free of oxide (second gate electrode 216 is deposited directly on first gate electrode 214, and therefore the interface is free of oxide);
removing (Fig. 24, [0073]) the second work function layer (second gate electrode 216, Fig. 24, [0073]) from the first region (above third fin structure 116, Fig. 24);
depositing (Fig. 25, [0078]: “deposition process”) a third work function layer (third gate electrode layer 218, Fig. 25, [0078]) wrapping around each of the nanostructures in the first region (above third fin structure 116, Fig. 25) and over the second work function layer (second gate electrode 216, Fig. 25) in the second (above second fin structure 114, Fig. 25) and third regions (above first fin structure 112, Fig. 25); and
forming a capping layer (filler layer 138, Fig. 26, [0080]) over the third work function layer (third gate electrode layer 218, Fig. 26) in the first (above third fin structure 116, Fig. 26), second (above second fin structure 114, Fig. 26), and third (above first fin structure 112, Fig. 26) regions.
Regarding claim 2, Huang Embodiment 1 teaches the method of claim 1, wherein the first work function layer (first gate electrode 214, Fig. 26) and the second work function layer (second gate electrode 216, Fig. 26) are of a first conductivity type (p-type, see claim 1 rejection above), and the third work function layer (third gate electrode layer 218, Fig. 26) is of a second conductivity type (n-type, [0078]: “the third gate electrode layer 218 comprises a conductive material that is an n-type work function metal (e.g., titanium aluminum, titanium aluminum carbide, tantalum aluminum carbide, titanium silicon aluminum carbide, etc.)”) that is opposite to the first conductivity type (p-type).
Regarding claim 3, Huang Embodiment 1 teaches the method of claim 2, wherein the first conductivity type is p-type (see claim 2 rejection above) and the second conductivity type is n-type (see claim 2 rejection above).
Regarding claim 6, Huang Embodiment 1 teaches the method of claim 1, wherein the first work function layer (first gate electrode 214, Fig. 26, [0063]) and the second work function layer (second gate electrode 216, Fig. 26, [0071]) include a same work function material with a same grain size (both layers are deposited with the same deposition process ([0063 and [0072]) and from the same material (titanium nitride), therefore the first and second metal work function layers are identical and have the same grain size).
Regarding claim 7, Huang Embodiment 1 teaches the method of claim 1, further comprising:
after the depositing of the second work function layer (second gate electrode 216, Fig. 23), forming a barrier layer (eighth masking structure 2402, Figs. 23-24, [0071]) over the second work function layer (second gate electrode 216, Figs. 23-24”) in the first (above third fin structure 116, Figs. 23-24), second (above second fin structure 114, Figs. 23-24), and third (above first fin structure 112, Figs. 23-24) regions ( “In some embodiments, the eighth masking structure 2402 may be formed using deposition (e.g., spin-coating), photolithography and removal (e.g., etching) processes.“ ([0072] and “After the formation of the eighth masking structure 2402, in some embodiments, a ninth removal process is performed to remove portions of the second conductive layer (2302 of FIG. 23) that are uncovered by the eighth masking structure 2402 thereby forming a second gate electrode layer 216 over the second fin structure 114.” ([0073]); therefore, even though not illustrated in any figures, the barrier layer is formed in all regions and then removed from the first region later); and
after the removing of the second work function layer (second gate electrode 216, Fig. 24) from the first region (above third fin structure 116, Fig. 24), removing ([0077]) the barrier layer (eighth masking structure 2402, Fig. 25, [0077]) from the second (above second fin structure 114, Fig. 25) and third (above first fin structure 112, Fig. 25) regions, wherein the removing of the second work function layer (second gate electrode 216, Fig. 24) from the first region (above third fin structure 112, Fig. 24) includes removing the barrier layer (eighth masking structure 2402, Figs. 24, “In some embodiments, the eighth masking structure 2402 may be formed using deposition (e.g., spin-coating), photolithography and removal (e.g., etching) processes.“ ([0072] and “After the formation of the eighth masking structure 2402, in some embodiments, a ninth removal process is performed to remove portions of the second conductive layer (2302 of FIG. 23) that are uncovered by the eighth masking structure 2402 thereby forming a second gate electrode layer 216 over the second fin structure 114.” ([0073])) from the first region (above third fin structure 112, Fig. 24).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Huang Embodiment 1 (US 2021/0134794 A1, Embodiment 1, where the first gate electrode 214 and second gate electrode are formed from the material; [0063] and [0071]: p-type titanium nitride) as applied to claims 1-3 and 6-7 above, and further in view of Huang Embodiment 2 (US 2021/0134794 A1, Embodiment 2, where the first gate electrode 214 and second gate electrode 216 are formed from different materials, [0097]).
Regarding claim 4, while Huang Embodiment 1 teaches the method of claim 1,
Huang Embodiment 1 does not teach that the first work function layer and the second work function layer include different work function materials
Huang Embodiment 2, on the other hand, teaches a method for manufacturing a semiconductor device wherein the first work function layer (first gate electrode 214, Fig. 26, [0063]) and the second work function layer (second gate electrode 216, Fig. 26, WFM 23, Fig. 22, [0071]) include different work function materials ([0097]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the threshold voltage of a FET comprising nanostructure stacks would depend on the work function material, as evidenced by Yu (US 2021/0098455 A1, [0034]). Yu further discloses that multi-threshold voltage IC devices may require transistors with different voltage thresholds ([0003]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to manufacture a multi-threshold device would be motivated to modify the method of Huang Embodiment 1 according to the teachings of Huang Embodiment 2 and form the first work function layer and the second work function layer from different work function materials.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Huang Embodiment 1 (US 2021/0134794 A1, Embodiment 1, where the first gate electrode 214 and second gate electrode are formed from the material; [0063] and [0071]: p-type titanium nitride) as applied to claims 1-3 and 6-7 above, and further in view of Hsiao (US 2021/0159326 A1).
Regarding claim 5, Huang Embodiment 1 teaches the method of claim 1, wherein the first work function layer (first gate electrode 214, Fig. 26, [0063]) and the second work function layer (second gate electrode 216, Fig. 26, [0071]) include a same work function material ([0063] and [0071]: both the first gate electrode 214 and the second gate electrode 216 can be p-type titanium nitride).
Huang Embodiment 1, however, does not teach that the first work function layer and the second work function layer have different grain sizes.
Hsiao, on the other hand, teaches a method for forming a gate stack for a radio-frequency (RF) p-type finFET device (FinFET 90, Fig. 14A, Abstact and [0048]) wherein the metal gate includes a work function layer (work function layer 66, Fig. 14A, [0031] comprising a first work function layer (lower layer 66A, Fig. 14A, [0031]) and a second work function layer (upper layer 66B, Fig. 14A, [0031) that include a same work function material but different grain sizes ([0031]: “Lower layer 66Ahas grain sizes smaller than the grain sizes of upper layer 66B.”).
Hsiao further discloses that by forming work-function layer 66 with two layers with the same material (having the same composition or different compositions), the lower layer 66A, with the smaller grain size, is suitable for acting as a seed layer for the formation of the upper layer 66B. The lower layer 66A, with the smaller grain size, however, has a relative high sheet resistance, which adversely affects the speed of the resulting transistor. Accordingly, the upper layer 66B is formed with larger grain and hence a lower sheet resistance to improve the performance. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to use the transistor in the second region as a RF transistor would be motivated to modify the method of Huang Embodiment 1 to form the first work function layer and the second work function layer with different grain sizes to improve the RF performance of the semiconductor device.
Claim 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Huang Embodiment 1 (US 2021/0134794 A1, Embodiment 1, where the first gate electrode 214 and second gate electrode are formed from the material; [0063] and [0071]: p-type titanium nitride) as applied to claims 1-3 and 6-7 above, and further in view of Chen (US 2022/0102147 A1).
Regarding claim 8, while Huang Embodiment 1 teaches the method of claim 7,
Huang Embodiment 1 does not teach that the removing of the barrier layer from the second and third regions results in an intermixing layer over the second work function layer in the second and third regions.
Chen, on the other hand, method of forming multiple layers of work function metals (Figs. 4A-4I, [0008] and [0015]) for field effect transistors (device 400, Fig. 4I, [0018] and [0041]). Chen’s method includes depositing a barrier layer (work function adjusting layer 442, Fig. 4C, [0033]: the work function adjusting layer 442 contains materials that are introduced into the first work function layer by an annealing process, and “The impurity is selected based on a predetermined work function, and there is no limitation of a species of the impurity in the present disclosure.”) over the first work function layer (first work function metal layer 430, Fig. 4C, [0032]), performing an anneal process (anneal operation 444, Fig. 4C, [0033]) to diffuse of material (impurities, [0033]) in the barrier layer (work function adjusting layer 442, Fig. 4C) into the first work function layer (first work function metal layer 430, Fig. 4C), thereby forming an intermixing layer (W-containing residue 440', Fig. 4E, [0033]: “annealing the work function adjusting layer 442 to diffuse the impurity into at least one of the dummy layer 440 and the first work function metal layer 430”) at an interface between the barrier layer (work function adjusting layer 442, Fig. 4C) and the first work function layer (first work function metal layer 430, Fig. 4C).
Chen further discloses that forming and removing a barrier layer (work function adjusting layer 442) in between stacked work function layers in the method of Chen improves the quality of work function layers ([0017] and improves the performance of the semiconductor device by adjusting the work function of different work function layers ([0003]). Therefore, a person of ordinary skill in the art before the effective fling date of the claimed invention would be motivated to modify the method of Huang Embodiment 1 by forming a dummy layer and a barrier layer after forming the second work function layer, performing an annealing step to diffuse the impurities into the dummy layer and second work function layer to form an intermixing layer, and then removing the barrier layer and portions of the dummy layer to reveal an intermixing layer (W-containing residue 440' of Chen) , as taught by Chen, before forming the third work function layer to obtain a device with improved performance and better layer quality. Thus, the combination of Huang Embodiment 1 and Chen meets the following limitations of claim 8 that the removing of the barrier layer from the second and third regions results in an intermixing layer over the second work function layer in the second and third regions.
Regarding claim 10, Huang Embodiment 1 in view of Chen teaches the method of claim 8, wherein
the combination of Huang Embodiment 1 and Chen further teaches that the third work function layer (third gate electrode layer 218, Fig. 25, [0078]) is in physical contact with the intermixing layer (W-containing residue 440' of Chen over the second work function layer (second gate electrode 216) of Huang Embodiment 1 introduced into the method of Huang Embodiment 1 via modification by Chen, see claim 8 above) in the second (above second fin structure 114, Fig. 25) and third (above first fin structure 112, Fig. 25) regions.
Claims 11-13 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Bao (US 2023/0187495 A1) in view of Wang (US 2019/0237336 A1).
Regarding claim 11, Bao teaches a method (method of forming various semiconductor structures for the FET devices, Figs. 1-22, [0032]), comprising:
providing a structure (semiconductor structure, Fig. 1, [0045]) having a first region (region of the substrate 1 where the NS 102 is located, which will be referred as region 102, Fig. 1; [0045]: each nanosheet stack NS 101, 102, 103, and 104 are on a different portion of the substrate 1) and a second region (region of the substrate 1 where the NS 104 is located, which will be referred as region 104, Fig. 1), a first stack of nanostructures (nanosheet stack (NS) 102 comprising channels 4, Fig. 1, [0045]) spaced vertically one from another (each channel 4 in the NS 102 is vertically separated from others, Fig. 1, [0045]) in the first region (region 102, Fig. 1), and a second stack of nanostructures (nanosheet stack (NS) 104 comprising channels 4, Fig. 1, [0045]) spaced vertically one from another (each channel 4 in the NS 104 is vertically separated from others, Fig. 1, [0045]) in the second region (region 104, Fig. 1);
forming a dielectric layer (dielectric 6, Fig. 1, [0045]) wrapping around each of the nanostructures (channels 4, Fig. 1) in the first (region 102, Fig. 1) and second (region 104, Fig. 1) regions;
forming a p-type work function layer (work function metal 22, Fig. 9, [0063]: WFM 22 is TiN, which is a common p-type work function material). Furthermore, Bao teaches that the each of the NS 101, 102, 103, and 104 may be a pFET ([0049]) over the dielectric layer (dielectric 6, Fig. 9) in the first (region 1402/1502, Figs. 14-15) and second (region 1404/1504, Fig. 9) regions;
depositing a barrier layer (sacrificial oxide 43, Fig. 10, [0064]) over the p-type work function layer (work function metal 22, Fig. 10) in the first (region 1002, Fig. 16) and second regions (region 1004, Fig. 10);
removing the barrier layer (sacrificial oxide 43, Figs. 11-12) and the p-type work function layer (work function metal 23, Figs. 11-12) from the first region (region 1102/1202, Fig. 18), thereby exposing the dielectric layer (dielectric 6, Figs. 11-12) in the first region (region 1102/1202, Figs. 11-12);
removing the barrier layer (sacrificial oxide 43, Figs. 13-14) from the second region (region 1304/1404, Figs. 13-14), resulting in a thin film (very thin layer of sacrificial oxide 43, Figs. 13-14, [0068]) over the p-type work function layer (work function metal 22, Figs. 13-14) in the second region (region 1304/1404, Figs. 13-14); and
forming a work function layer (WFM 23, Fig. 15, [0072]) over the dielectric layer (dielectric 6, Fig. 15) in the first region (region 1502, Fig. 15) and over the thin film (very thin layer of sacrificial oxide 43, Fig. 15) in the second region (region 1504, Fig. 15), wherein after the forming of the n-type work function layer (WFM 23, Fig. 15), the n-type work function layer (WFM 23, Fig. 15) fully fills up gaps between adjacent ones of the nanostructures (nanosheet stack (NS) 103 comprising channels 4, Fig. 15) in the second region (region 1504, Fig. 15, [0072]: “As depicted in FIG. 15, the deposition of WFM 23 pinches off the gaps between sacrificial oxide 43 on adjacent channels 4 in NS 1504”).
Boa, however, does not explicitly disclose that
the work function layer formed over the dielectric layer in the first region and over the thin film in the second region is an n-type work function layer.
Wang, on the other hand, teaches a method for forming gate structures for semiconductor devices (CMOS device, Fig. 11, [0004]), which comprises an nFET transistor (second stack 11b (analogous to the region 101 of Bao), [0063]) and a pFET transistor (first stack 11a (analogous to the region 102 of Bao), [0063]) located at different regions of the semiconductor device (Fig. 11), wherein the nFET comprises an n-type work function layer (second gate metal layer 30, Fig. 11, [0081]), and the pFET device comprises a p-type work function layer (first gate metal layer 20, Fig. 11, [0085]).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the method of Bao to choose the FET device in the first region of the semiconductor device of to be an nFET (accordingly the work function layer will be an n-type work function metal), as taught by Wang, to be able to manufacture CMOS-bases devices which improve device miniaturization ([0002]).
Thus, thus the combination of Bao and Wang meets all the limitations of claim 11.
Regarding claim 12, Bao in view of Wang teaches the method of claim 11, wherein
Bao further teaches that the thin film (very thin layer of sacrificial oxide 43, Figs. 13-14, [0068]) includes a first metal element (Ti, [0063]: WFM 22 is TiN) from the p-type work function layer (work function metal 22, Figs. 13-14) and a second metal element ([0064]: La or Y) from the barrier layer (sacrificial oxide 43, Figs. 13-14, [0068]: “compound or mix of La and Ti”).
Regarding claim 13, Bao in view of Wang teaches the method of claim 12, wherein
Bao further teaches that the first metal element (TiN, see claim 12 rejection above) is titanium (Ti, see claim 12 rejection above).
Bao, however, does not teach that the second metal element is tungsten.
Wang, on the other hand, teaches a barrier layer (etch stop layer 25, Fig. 8, [0066]) that is tungsten nitride (WN) ([0066]).
Therefore, tungsten nitride is an alternative material for lanthanum oxide (LaOx) as the barrier layer (see Wang [0066]). Selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301 (see MPEP 2144.06). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention who choses WN over LaOx for the barrier layer would obtain tungsten as the second metal element in the thin film.
Regarding claim 16, Bao in view of Wang teaches the method of claim 11, wherein
Bao further teaches that after the depositing of the barrier layer (sacrificial oxide 43, Fig. 10, [0064]), the barrier layer (sacrificial oxide 43, Fig. 10) fills up gaps (see Fig. 10) between adjacent ones of the nanostructures (channels 4, Fig. 10, [0045]) in the first (region 1002, Fig. 10) and second (region 1004, Fig. 10) regions.
Regarding claim 17, Bao in view of Wang teaches the method of claim 11, wherein
Bao further teaches that after the forming of the n-type work function layer (WFM 23, Fig. 15, [0072]), gaps (space between channels 4 in region 1002, Fig. 10) between adjacent ones of the nanostructures (channels 4 in region 1002, Fig. 10) in the first region (region 1002, Fig. 10) remain.
Claim 21-23 are rejected under 35 U.S.C. 103 as being unpatentable Lin (US 2021/0057544 A1) in views of Chen (US 2022/0102147 A1) and Lima (Lima et al, J. Appl. Phys. 115, 074504 (2014), https://doi.org/10.1063/1.4866323).
Regarding claim 21, Lin teaches a method (Figs. 3-16, [0004]-[0006]), comprising:
forming a plurality of first nanostructures (stacked semiconductor layers 204A on the n-type region 202B, Fig. 11B, [0016]-[0017]) vertically stacked over a first region (n-type region 202B, Fig. 11B, [0016]) of a substrate (substrate 202, Figs. 11B, [0015]);
forming a plurality of second nanostructures (stacked semiconductor layers 204A on the p-type region 202A, Fig. 11B, [0016]-[0017]) vertically stacked over a second region (p-type region 202A, Fig. 11B, [0016]) of the substrate (substrate 202, Fig. 11B);
depositing a gate dielectric layer (gate dielectric layer 282, Fig. 12B, [0034]) wrapping around each of the first (stacked semiconductor layers 204A on the n-type region 202B, Fig. 112B) and second (stacked semiconductor layers 204A on the p-type region 202A, Fig. 12B) nanostructures;
depositing (Fig. 12B, [0036]) a first work function layer (first WFM layer 286, Fig. 12B, [0036]) of a first conductivity type ([0036]: ”p-type work function”) over the gate dielectric layer (gate dielectric layer 282, Fig. 12B) in the first (n-type region 202B, Fig. 12B) and second (p-type region 202A, Fig. 12B) regions; and
depositing (Fig. 14B, [0040]) a second work function layer (second WFM layers 288, Fig. 14B, [0040]) of a second conductivity type ([0040]: “n-type”) opposite to the first conductivity type (p-type) over the gate dielectric layer (gate dielectric layer 282, Fig. 14B) in the first region (n-type region 202B, Fig. 14B) and over the first work function layer (first WFM layer 286, Fig. 14B) in the second region (p-type region 202A, Fig. 14B).
Lin, however, does not teach
depositing a metal-containing barrier layer over the first work function layer in the first and second regions;
removing the metal-containing barrier layer and the first work function layer from the first region, thereby exposing the gate dielectric layer in the first region;
performing an anneal process to promote a diffusion of a metal element in the metal-containing barrier layer into the first work function layer, thereby forming an alloy thin film at an interface between the metal-containing barrier layer and the first work function layer in the second region;
removing the metal-containing barrier layer from the second region, resulting in exposing the alloy thin film over the first work function layer in the second region; and
depositing the second work function layer over the alloy thin film in the second region.
Chen, on the other hand, method of forming multiple layers of work function metals (Figs. 4A-4I, [0008] and [0015]) for field effect transistors (device 400, Fig. 4I, [0018] and [0041]). Chen’s method includes
depositing a barrier layer (work function adjusting layer 442, Fig. 4C, [0033]: the work function adjusting layer 442 contains materials that are introduced into the first work function layer by an annealing process, and “The impurity is selected based on a predetermined work function, and there is no limitation of a species of the impurity in the present disclosure.”) over the first work function layer (first work function metal layer 430, Fig. 4C, [0032]);
performing an anneal process (anneal operation 444, Fig. 4C, [0033]) to promote a diffusion of an element (impurities, [0033]) in the barrier layer (work function adjusting layer 442, Fig. 4C) into the first work function layer (first work function metal layer 430, Fig. 4C), thereby forming an alloy thin film (W-containing residue 440', Fig. 4E, [0036]: the alloy film is formed by diffusion of impurities into a dummy layer 440, which was located between the work function adjusting layer 442 and first work function metal layer 430, see [0033]: “annealing the work function adjusting layer 442 to diffuse the impurity into at least one of the dummy layer 440 and the first work function metal layer 430”) at an interface between the barrier layer (work function adjusting layer 442, Fig. 4C) and the first work function layer (first work function metal layer 430, Fig. 4C);
depositing the second work function layer (second work function metal layer 450, Fig. 4F, [0038]) over the alloy thin film (W-containing residue 440', Fig. 4E, [0038]).
Chen further discloses that forming and removing a barrier layer (work function adjusting layer 442) in between stacked work function layers in the method of Chen improves the quality of work function layers ([0017] and improves the performance of the semiconductor device by adjusting the work function of different work function layers ([0003]). Therefore, a person of ordinary skill in the art before the effective fling date of the claimed invention would be motivated to modify the method of Lin by forming a dummy layer and a barrier layer after forming the first work function layer, performing an annealing step to adjust the work function of the first work function layer, and then removing the barrier layer and portions of the dummy layer before forming the second work function layer as taught by Chen, to obtain a device with improved performance and better layer quality. Thus, the combination of Lin and Chen meets the following limitations of claim 21 regarding the method further comprises
depositing a barrier layer over the first work function layer in the first and second regions;
removing the barrier layer and the first work function layer from the first region, thereby exposing the gate dielectric layer in the first region;
performing an anneal process to promote a diffusion of an element in the barrier layer into the first work function layer, thereby forming an alloy thin film at an interface between the metal-containing barrier layer and the first work function layer in the second region;
removing the barrier layer from the second region, resulting in exposing the alloy thin film over the first work function layer in the second region; and
depositing the second work function layer over the alloy thin film in the second region.
The combination of Lin and Chen, however, are silent on the composition of the barrier layer (Chen, [0033]: ”introducing the impurity is performed by depositing a work function adjusting layer 442 over the dummy layer 440 …. The impurity is selected based on a predetermined work function, and there is no limitation of a species of the impurity in the present disclosure.”, and therefore does not teach that
the barrier layer is a metal-containing barrier layer; and
the diffusing element is a metal element.
Lima, on the other hand, teaches a method for tuning (reducing) the work function of a TiN layer (Abstract; the first work function layer of Lin in view of Chen is TiN (see above)) by annealing a AlN layer deposited on the TiN layer by diffusing the Al into the TiN layer (page 3, col. 2, para. 2). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to reduce the work function of the first work function in the method of Lin in view of Chen would be motivated to use AlN, as taught by Lime, for the barrier layer in the method of Lin in view of Chen. Accordingly, the combination of Lin, Chen, and Lima meets all the limitations of claim 21.
Regarding claim 22, Lin in views of Chen and Lima teaches the method of claim 21, wherein
the combination of Lin in views of Chen and Lima further teaches that the alloy thin film (Chen’s W-containing residue 440' introduced into the method of Lin (see claim 1 rejection above) includes titanium and tungsten ([0037]: “W-containing residue 440' may further include a compound of W and TiN, …”).
Regarding claim 23, Lin in views of Chen and Lima teaches the method of claim 21, wherein
The combination Lin, Chen and Lima further teaches that after the depositing of the metal-containing barrier layer (in the method of Lin modified by Chen and Lima the metal-containing barrier layer would be deposited after forming the first work function layer (first WFM layer 286, Fig. 12B) conformally over the first work function layer in both the first region (p-type region 202A, Fig. 12B) and second region (n-type region 202B, Fig. 12B)), the metal-containing barrier layer fills up gaps between adjacent ones of the first and second nanostructures (because the barrier layer is conformally deposited over the first and second nanostructures, the barrier layer fills up the gaps between adjacent nanostructures).
Allowable Subject Matter
Claims 9 and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 9, disclosing the limitation that “the intermixing layer includes a first metal element from the second work function layer and a second metal element from the barrier layer”, would be allowable if incorporated in a claim combining claims 1 and 7-8.
Regarding the relevant prior art for the invention disclosed in claim 9, Bao (Us 2023/0287495 A1) is identified as the closest prior art. As detailed in the non-final office action Bao teaches all the limitations of claim 1, 7, and 8, except the new limitation added to claim 1, that “an interface between the second work function layer and the first work function layer in the third region is free of oxide”, where the interface includes the intermixing layer which includes an oxide in Bao. Regarding Huang Embodiment 1 in view of Chen as applied to claims 1 and 7-8 above, the intermixing layer is formed by diffusion of impurities from the barrier layer to a dummy layer over the second work function layer. Therefore, the intermixing layer includes diffused impurity elements from the barrier layer, but nor from the second work function layer. There has been no prior art identified that can modify the method of Huang Embodiment 1 to include an intermixing layer that includes a first metal element from the second work function layer and a second metal element from the barrier layer. Therefore, claim 9 includes allowable subject matter, but is objected because claim 9 depends on a rejected claim.
Claim 14, disclosing the limitations “removing the sacrificial work function layer and the metal-containing layer from the first and second regions, thereby exposing the dielectric layer in the first and second regions”, would be allowable if written in an independent form or is incorporated with claim 11.
Regarding the relevant prior art for the invention disclosed in claim 9, the combination of Bao (Us 2023/0287495 A1) and Wang (US 2019/0237336 A1) is identified as the closest prior art. Bao teaches in regions 201-601, 202-602 and 203-603 (Figs. 2-6) a sacrificial work function layer (WFM 21) and a metal containing layer (sacrificial oxide 33) to be deposited and removed. Therefore, for the limitations of claim 11, if any pair of these regions could be selected, then the invention of claim 14 would be obvious. However, such a selection cannot be made, because of the new limitation of claim 11 ”the n-type work function layer fully fills up gaps between adjacent ones of the nanostructures in the second region” conflicts with the coverage of nanostructures in region 204-604. Alternatively, including a fifth region in Bao also does not recover this issue. There has been no motivation (steps disclosed in claim 14 leaves the device structure unchanged) or prior art that has been identified to modify Bao in view of Wang to make the invention of claim 14 obvious. Therefore, claim 14 includes allowable subject matter, but is objected because claim 14 depends on a rejected claim.
Claim 15, which inherits allowable subject matter from claim 14, is objected, too, because claim 15 also depends on a rejected claim.
Response to Arguments
It has been acknowledged that the applicant amended claims 1, 11, 17, and 21 per response dated on 3/4/2026. Applicant's arguments with respect to claims have been fully considered.
Applicant argues in substance:
Amended claim 1 recites, in part, "depositing a second work function layer wrapping around each of the nanostructures in the first and second regions and over the first work function layer in the third region, wherein an interface between the second work function layer and the first work function layer in the third region is free of oxide." ….
Therefore, Bao at least does not disclose or suggest "depositing a second work function layer wrapping around each of the nanostructures in the first and second regions and over the first work function layer in the third region, wherein an interface between the second work function layer and the first work function layer in the third region is free of oxide," as recited by amended claim 1. Accordingly, Applicant respectfully requests the Office withdraw the rejection to amended claim 1.
The examiner agrees with the Applicant on that amended claim 1 with the new limitation stated above overcame the 35. U.S.C. 102 rejection made by prior art Bao-1 (US 2023/0187495 A1, Embodiment 1, where the work function metal WFM 22 and the work function metal WFM 23 are same metal nitride, [0072]).
Claim 1, however. is now rejected under 35. U.S.C 102 based on a new prior art Huang Embodiment 1 (US 2021/0134794 A1, Embodiment 1, where the first gate electrode 214 and second gate electrode are formed from the material; [0063] and [0071]: p-type titanium nitride) as detailed in the office action above. Claims 2-8 and 10 which are directly or indirectly dependent on claim 1 are also rejected by Huang Embodiment 1 or its combination with other references. Regarding claim 9, no grounds for rejection has been identified. Therefore, claim 9 is now objected, because claim 9 depends on a rejected claim.
Amended claim 11 recites, in part, "forming an n-type work function layer over the dielectric layer in the first region and over the thin film in the second region, wherein after the forming of the n-type work function layer, the n-type work function layer fully fills up gaps between adjacent ones of the nanostructures in the second region."
However, in Bao's teaching, WFM 24 does not fully fill up gaps between channels 4 in region 2102. As shown in Bao's FIG. 4, gaps still exist after the deposition of WFM 24. Therefore, Bao at least does not disclose or suggest "forming an n-type work function layer over the dielectric layer in the first region and over the thin film in the second region, wherein after the forming of the n-type work function layer, the n-type work function layer fully fills up gaps between adjacent ones of the nanostructures in the second region," as recited by amended claim. The Wang reference does not remedy the deficiency. In that regard, the Wang reference is cited for allegedly teaching choosing n-type work function layer in a CMOS device. Accordingly, Applicant respectfully requests the Office withdraw the rejection to amended claim 11.
The examiner agrees with the Applicant on that the amended claim 11 overcame the 35 U.S.C. 103 rejection based on prior-art Bao-1 (US 2023/0187495 A1, Embodiment 1, where the work function metal WFM 22 and the work function metal WFM 23 are same metal nitride, [0072]) and Wang (US 2019/0237336 A1).
However, claim 11 is now rejected under new grounds again based on Bao-1 and Wang as detailed in the office action above. Claims 12-13 and 16-17 which are directly or indirectly dependent on claim 11 are also rejected by Bao-1 and Wang, or their combination with other references. Regarding claims 14-15, no grounds for rejection has been identified. Therefore, claim 14-15 are now objected, because they depend on a rejected claim.
Amended claim 21 recites, in part, "performing an anneal process to promote a diffusion of a metal element in the metal-containing barrier layer into the first work function layer, thereby forming an alloy thin film at an interface between the metal-containing barrier layer and the first work function layer in the second region; removing the metal-containing barrier layer from the second region, resulting in exposing the alloy thin film over the first work function layer in the second region." ….
Therefore, Bao at least does not disclose or suggest "performing an anneal process to promote a diffusion of a metal element in the metal-containing barrier layer into the first work function layer, thereby forming an alloy thin film at an interface between the metal-containing barrier layer and the first work function layer in the second region; removing the metal-containing barrier layer from the second region, resulting in exposing the alloy thin film over the first work function layer in the second region," as recited by amended claim 21. The Wang reference does not remedy the deficiency. In that regard, the Wang reference is cited for allegedly teaching choosing n-type work function layer in a CMOS device. Accordingly, Applicant respectfully requests the Office withdraw the rejection to amended claim 21.
The Examiner agrees with the Applicant on that the amended claim 21 overcame the 35 U.S.C. 103 rejection based on Bao-1 (US 2023/0187495 A1, Embodiment 1, where the work function metal WFM 22 and the work function metal WFM 23 are same metal nitride, [0072]) and Wang (US 2019/0237336 A1).
However, claim 21 is now rejected under new grounds again based Lin (US 2021/0057544 A1) in views of Chen (US 2022/0102147 A1) and Lima (Lima et al, J. Appl. Phys. 115, 074504 (2014), https://doi.org/10.1063/1.4866323) as detailed in the office action above. Claims 22-23 which are dependent on claim 21 are also rejected based on these new references.
Applicant respectfully notes that Claim 11 is additionally rejected under 35 U.S.C. § 103 over Yang in view of Lee. See Office Action at page 11. However, the Office Action does not provide any accompanying explanation, claim mapping, or articulated reasoning in support of this rejection. Moreover, Yang and Lee are not otherwise discussed in the Office Action in connection with Claim 11.
In view of the absence of any stated findings or rationale, Applicant is unable to meaningfully respond to this rejection. Applicant respectfully submits that the above-referenced rejection may have been included in error (e.g., as a typographical or clerical oversight).
Accordingly, Applicant has not substantively addressed this rejection at this time.
The Examiner apologizes for this error. As the Applicant correctly guessed, the stated rejection was due to a typographical or clerical oversight, and no response was required.
For the purpose of compact prosecution, the Examiner notes that incorporating limitations that clarify the intermixing layer further may make independent claim 1, 11, and 21 inventive and non-obvious.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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