DETAILED ACTION
This office action is in response to amendment filed 12/09/2025.
Claims 1-4, 7-13, 15, 17-19 and 21-23 are pending. Claims 5-6, 14, 16, 20, and 24-35 have been canceled. Claims 1-4, 7-13, 15, 17-19 and 21-23 have been amended. Claims 21-23 have been withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 7-13, 15, and 17-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 reciting “the thin active layer underlying the thick active layer is doped so as to lower the resistance RB of the thick active layer” renders the claim indefinite. Amended claim 1 reciting “a thick active layer formed on a selected region of the thin active layer such that the selected region of the thin active layer underlies the thick active layer”, which defines the thin active layer as a separate layer over which the thick active layer is formed. It is unclear how would the dopant level in the lower thin active layer affect the resistance of the upper thick active layer. Applicant’s specification describes the resistance of the “P-well body region” to be lowered by doping the lower thin active layer (see ¶ 46). However, the “P-well body region”, as best understood, does not correspond to the upper thick active layer. Rather, the “P-well body region” appear to correspond to only the lower doped portion of the entire active layer. Furthermore, Applicant’s original describes the “thick active layer” as including the lower “thin active layer” (see FIG. 1A). As such, the “thick active layer” ALthick has a total thickness that is “thick” relative to the “thin active layer” ALthin alone. However, the claimed “thick active layer” is now only referring to the upper portion of ALthick above the “thin active layer”. The “thin active layer” ALthin and the “thick active layer” above ALthin seemingly having comparable thickness. Therefore, it is unclear what constitutes “thin active layer” vs. “thick active layer”. It is unclear what is meant by the relative terms “thin” and “thick”.
Claim 10 reciting “a second field-effect transistor” renders the claim indefinite. No “first field-effect transistor” has been claimed previously. It is unclear if the recitation to “a second field-effect transistor” implies the prerequisite of a first field-effect transistor.
Claim 13 reciting “a lower portion of the body region is doped to have a lower resistance RB” renders the claim indefinite. It unclear if the doped region having a lower resistance RB is referring the doped thin active layer having the resistance RB as recited in claim 1. Applicant’s disclosure does not appear to describe two separate doped regions having “a lower resistance RB”.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 9-13, 15 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsujiuchi et al. US 2007/0176235 A1 (Tsujiuchi).
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In re claim 1, as best understood, Tsujiuchi discloses (e.g. FIG. 94-96) an integrated circuit having dual-thickness active areas, including:
(a) a substrate 1;
(b) a buried oxide layer 2 formed on the substrate 1;
(c) a “thin active layer” (lower portion of layer 3, labeled in FIG. 81; the lower portion of layer 3 is considered “thin” relative a greater thickness) formed on the buried oxide layer 2;
(d) a “thick active layer” (upper portion of layer 3 in thick film SOI region 101; the upper portion of layer 3 is considered “thick” relative to a smaller thickness) formed on a selected region (e.g. in region 101) of the “thin active layer” such that the selected region of the “thin active layer” (lower portion of layer 3 in region 101) underlies the “thick active layer” (upper portion of layer 3 in region 101, wherein the “thin active layer” (lower portion of layer 3 in region 101) underlying the “thick active layer” is doped (doped regions 34 extend into the lower “thin active layer”, ¶ 216) so as to lower the resistance RB of the “thick active layer” (as best understood, the upper “thick active layer” also including doped regions 34 which effectively lowers the resistance in the doped regions of the upper “thick active layer” compared to an undoped region).
Tsujiuchi further teaches additionally doping lower portion of silicon layer 3 (FIG. 67, ¶ 146-147) to form doped regions 27 in the silicon layer. The doped regions 27 also has a lowered electrical resistance compared to an undoped region.
In re claim 2, Tsujiuchi discloses (e.g. FIG. 94) the silicon layer 3 has a thickness of 100 nm to 200 nm (¶ 221). The “thin active layer” is considered to correspond to a lower portion of layer 3. More particularly, the “thin active layer” may correspond to a lower portion of layer 3 that is 550 Å or less thick. As such, the “thin active layer” (corresponding only to the lower 550 Å or less thick portion) has a thickness at or below about 550 Å.
In re claim 3, Tsujiuchi discloses (e.g. FIG. 94) wherein the thin and thick active layers (i.e. entire layer 3 in thick film SOI region 101) have a combined thickness at or above about 1000 Å (100 nm to 200 nm, ¶ 221).
In re claim 4, Tsujiuchi discloses (e.g. FIG. 81) the thick active layer (upper portion of layer 3 in thick film SOI region 101) is formed from a layer of semiconductor material (e.g. silicon layer, ¶ 206). The recitation “wherein the thick active layer is formed by epitaxial growth of one or more semiconductor materials on the selected region of the thin active layer” pertains to product by process limitation. In regard to the product by process language, since a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao and Sato et al., 190 USPQ 15 at 17 (CCPA 1976) (footnote 3). “[T]he lack of physical description in a product-by-process claim makes determination of the patentability of the claim more difficult, since in spite of the fact that the claim may recite only process limitations, it is the patentability of the product claimed and not of the recited process steps which must be established. We are therefore of the opinion that when the prior art discloses a product which reasonably appears to be either identical with or only slightly different than a product claimed in a product-by-process claim, a rejection based alternatively on either section 102 or section 103 of the statute is eminently fair and acceptable. As a practical matter, the Patent Office is not equipped to manufacture products by the myriad of processes put before it and then obtain prior art products and make physical comparisons therewith.” In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972). See also In re Luck and Gainer, 177 USPQ 523 (CCPA 1973); In re Fessmann, 180 USPQ 324 (CCPA 1974); and In re Marosi et al., 218 USPQ 289 (CAFC 1983). It is the final product per se which must be determined for patentability in a "product by, all of" claim, and not the patentability of the process, and that an old or obvious product, whether claimed in "product by process" claims or not, is not patentable. Note that Applicant has the burden of proof in such cases, as the above case law makes clear. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based upon the product itself. The patentability of a product does not depend on its method of production. If the product in product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product is made by a different process. In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985).
In re claim 9, Tsujiuchi discloses (e.g. FIG. 94) wherein the substrate 1 is silicon (¶ 62). No specific magnitude has been claimed to define “high-resistivity” or particular porosity that would render the claimed substrate structurally distinguishable from Tsujiuchi’s silicon substrate 1. More specifically, Tsujiuchi’s silicon substrate 1 is considered to be a “high-resistivity silicon” relative to a silicon substrate having lower resistivity, and is considered to be a “porous silicon” relative to a silicon substrate having higher density.
In re claim 10, as best understood, Tsujiuchi discloses (e.g. FIGs. 93-96) further including a “second field-effect transistor” (FET) Q2, the second FET Q2 including:
(a) a semiconductor well 54 formed within the thin active layer (silicon layer 3 in thin film SOI region 102);
(b) a gate structure 13 formed on the semiconductor well;
(c) a source region 34 formed within the semiconductor well adjacent a first side of the gate structure 13; and
(d) a drain region 34 formed within the semiconductor well adjacent a second side of the gate structure 13.
In re claim 11, Tsujiuchi discloses (e.g. FIGs. 93-96) further including at least one field-effect transistor (FET) Q1, the at least one FET Q1 including:
(a) a semiconductor well 54 formed within the thick active layer (upper portion of silicon layer 3 in thick film SOI region 101);
(b) a gate structure 13 formed on the semiconductor well;
(c) a source region 34 formed within the semiconductor well adjacent a first side of the gate structure 13; and
(d) a drain region 34 formed within the semiconductor well adjacent a second side of the gate structure 13.
In re claim 12, Tsujiuchi discloses (e.g. FIGs. 95-96) wherein the FET Q1 further includes a body contact region 55 formed within the semiconductor well 54 and extending to the buried oxide layer 2.
In re claim 13, as best understood, Tsujiuchi discloses (e.g. FIGs. 95-96) wherein the FET Q1 further includes a body region 54 within the semiconductor well 54 underneath the gate structure, and wherein “a lower portion of the body region 54 (e.g. body contact region 55 doped in lower portion of body region 54) is doped to have a lower resistance RB”. No specific “lower resistance” is claimed that would distinguish over Tsujiuchi’s body contact region 55 that is P+ doped which has a “lower resistance” compared to a region with higher electrical resistance. P+ doped region 55 has lower resistance than the P doped region 54.
In re claim 15, Tsujiuchi discloses (e.g. FIG. 67 & FIG. 94) wherein the FET Q1 further includes a body region 54 within the semiconductor well underneath the gate structure 13, and wherein the FET Q1 is configured to fully deplete the body region in an OFF state (¶ 157). The body region is opposite in conductivity type from the source/drain region (¶ 147). Therefore, the body region during the OFF state of the FET would be free of charge carriers and is therefore considered to be fully depleted of charge carriers. Furthermore, a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “[A]pparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990).
In re claim 17, Tsujiuchi discloses (e.g. FIG. 67 & FIG. 94) wherein the FET Q1 further includes a body region 54 within the semiconductor well underneath the gate structure 13, and wherein the FET Q1 is configured to partially deplete the body region in an OFF state (¶ 157). The body region is opposite in conductivity type from the source/drain region (¶ 147). Therefore, the body region during the OFF state of the FET would be free of charge carriers and is therefore considered to be depleted of charge carriers. Partial depletion is compassed by full depletion. Furthermore, a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “[A]pparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Tsujiuchi as applied to claim 1 above, and further in view of Koga JP 2020038917 A.
In re claim 7, Tsujiuchi discloses the claimed IC SOI structure including a silicon active layer 3 having the lower thin active layer on a buried oxide layer 2 on a silicon support 1.
Tsujiuchi does not explicitly teach the SOI structure further including a heat dissipation layer formed between the buried oxide layer and the thin active layer.
However, Koga discloses a SOI wafer (e.g. FIGs. 2B-2C) comprising silicon active layer 21 on a buried oxide layer 35 on a silicon support 10, and further including a heat dissipation layer 31 formed between the buried oxide layer 35 and the active layer 21. Koga teaches the SiC heat dissipation layer 31 having high thermal conductivity is disposed between the buried oxide 35 and the silicon active layer 21 to improve heat dissipation of the SOI structure (Para 24).
A person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the SOI structure can be modified to further include a SiC heat dissipation layer for the purpose of improving heat dissipation. Furthermore, a person of ordinary skill in the art would have been able to carry out the modification. Finally, the modification achieves the predictable result of enhanced heat dissipation of the SOI substrate which results in improved device performance. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the SOI structure of Tsujiuchi to additionally include a SiC heat dissipation layer between the oxide layer and the active layer to improve heat dissipation of the SOI structure according to known methods to yield the predictable result of improved heat dissipation as taught by Koga.
In re claim 8, Tsujiuchi discloses the claimed IC SOI structure including a silicon active layer 3 having the lower thin active layer on a buried oxide layer 2 on a silicon support 1.
Tsujiuchi does not explicitly teach the SOI structure further including a silicon carbide layer formed between the buried oxide layer and the thin active layer.
However, Koga discloses a SOI wafer (e.g. FIGs. 2B-2C) comprising silicon active layer 21 on a buried oxide layer 35 on a silicon support 10, and further including a heat dissipation layer 31 formed between the buried oxide layer 35 and the active layer 21. Koga teaches the SiC heat dissipation layer 31 having high thermal conductivity is disposed between the buried oxide 35 and the silicon active layer 21 to improve heat dissipation of the SOI structure (Para 24).
A person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the SOI structure can be modified to further include a SiC heat dissipation layer for the purpose of improving heat dissipation. Furthermore, a person of ordinary skill in the art would have been able to carry out the modification. Finally, the modification achieves the predictable result of enhanced heat dissipation of the SOI substrate which results in improved device performance. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the SOI structure of Tsujiuchi to additionally include a SiC heat dissipation layer between the oxide layer and the active layer to improve heat dissipation of the SOI structure according to known methods to yield the predictable result of improved heat dissipation as taught by Koga.
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Tsujiuchi as applied to claim 11 above, and further in view of Yeo et al. US 2004/0175872 A1 (Yeo).
In re claim 18, Tsujiuchi teaches (e.g. FIGs. 94-96) the claimed SOI IC structure having dual-thickness including a silicon active layer 3 on a buried oxide layer 2 on a silicon support 1, and MOSFET formed in the thick active layer having a semiconductor well 54. Tsujiuchi does explicitly teach the semiconductor well includes at least two layers, at least one of the two layers comprising a silicon germanium alloy.
However, Yeo teaches (FIG. 6) a MOSFET IC on a SOI substrate, wherein the active layer including semiconductor well is composed of a first silicon layer 5, a silicon germanium layer 6, and a second silicon layer 7a,7b (¶ 14-16).
Yeo such multilayered structure introduces compressive strain in the channel of a PMOS and tensile strain in the silicon channel of a NMOS to improve carrier mobility (¶ 20).
A person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the silicon layer 3 of Tsujiuchi can be modified with the Si/SiGe/Si multilayered structure for the purpose of enhancing carrier mobility. Furthermore, a person of ordinary skill in the art would have been able to carry out the modification. Finally, the modification achieves the predictable result of enhanced carrier mobility. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tsujiuchi’s silicon layer 3 for the Si/SiGe/Si multilayered structure of Yeo according to known methods to yield the predictable result of enhanced carrier mobility as taught by Yeo.
In re claim 19, Yeo discloses (e.g. FIG. 6) wherein the semiconductor well includes:
(a) a first layer 5 of silicon (¶ 13);
(b) a second layer 6 of a silicon germanium alloy (¶ 14); and
(c) a third layer 7b (in NMOS region 2) of tensile-strained silicon (¶ 8,11,15,20, Abstract).
Response to Arguments
Applicant's arguments filed 12/09/2025 have been fully considered but they are not persuasive.
Regarding claimed rejected over Tsujiuchi, Applicant argues source/drain regions 32,34,36 formed by implanting impurity ions does not teach the “thin active layer” underlying a thick active layer is doped so as to lower the resistance of the “thick active layer” (Remark, page 7-8).
This is not persuasive. Firstly, it is unclear how would doping the thin active layer lower the resistance of the thick active layer as detailed in the §112b rejection above. The thin active layer and the thick active layer are claimed as physically separate layers. Applicant’s disclosure does not provide clarifying description on how doping of the thin active layer would lower the resistance of the overlying thick active layer.
Tsujiuchi teaches a silicon layer 3 that is doped by injecting impurity ions to form source/drain regions (¶ 216). The doped source/drain regions 34 extends into the lower “thin active layer” in region 103. The doped regions has a lowered resistance compared to an undoped region. Furthermore, the upper “thick active layer” of layer 3 in region 103 is also doped to form source/drain regions 34 which effectively lowers the resistance in the doped regions of the upper “thick active layer” compared to an undoped region.
Additionally, Tsujiuchi teaches doping lower portion of silicon layer 3 (FIG. 67, ¶ 146-147) to form doped regions 27 in the silicon layer. The doped regions 27 also has a lowered electrical resistance compared to an undoped region.
As such, the claimed invention, as best understood, is taught by prior art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896