DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-18 in the reply filed on 10/21/25 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shank(USPGPUB DOCUMENT: 2020/0161218, hereinafter Shank) in view of Sabuncuoglu Tezcan (USPGPUB DOCUMENT: 2012/0013022, hereinafter Sabuncuoglu Tezcan).
Re claim 1 Shank discloses a structure, comprising: a through semiconductor via (TSV(750)) in a semiconductor substrate(100); and a cavity including: a first cavity portion(middle/bottom portion of 450/420) in the semiconductor substrate(100) and surrounding a middle section of the TSV(750), and a plurality of second cavity portions(upper portion of 450/420) in the semiconductor substrate(100) and surrounding an upper section of the TSV(750), the semiconductor substrate(100) between adjacent second cavity portions(upper portion of 450/420).
Shank discloses the first cavity portion(middle/bottom portion of 450/420) in direct contact with the TSV(750),
Sabuncuoglu Tezcan discloses in Fig 3a the first cavity portion(20) in direct contact with the TSV(5),
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Sabuncuoglu Tezcan to the teachings of Shank in order to reduce the capacitance [0002, Sabuncuoglu Tezcan].
Re claim 2 Shank and Sabuncuoglu Tezcan disclose the structure of claim 1, wherein the TSV(750) includes a dielectric liner(470) surrounding a conductor core and wherein the first cavity portion(middle/bottom portion of 450/420) is in direct contact with the dielectric liner(470).
Re claim 3 Shank and Sabuncuoglu Tezcan disclose the structure of claim 1, wherein each of the plurality of second cavity portions(upper portion of 450/420) have an elongated, curved cross-sectional shape(see Fig 5/6 of Sabuncuoglu Tezcan).
Re claim 4 Shank and Sabuncuoglu Tezcan disclose the structure of claim 1, wherein each of the plurality of second cavity portions(upper portion of 450/420) have a circular cross-sectional shape(see Fig 5/6 of Sabuncuoglu Tezcan).
Re claim 5 Shank and Sabuncuoglu Tezcan disclose the structure of claim 1, wherein the first cavity portion(middle/bottom portion of 450/420) surrounds approximately 80% of a height of the TSV(750).
Re claim 6 Shank and Sabuncuoglu Tezcan disclose the structure of claim 1, wherein each of the plurality of second cavity portions(upper portion of 450/420) have a width of less 200 nanometers (nm).
Re claim 7 Shank and Sabuncuoglu Tezcan disclose the structure of claim 1, wherein each of the plurality of second cavity portions(upper portion of 450/420) have a passivation layer(820) on a sidewall of the semiconductor substrate(100).
Re claim 8 Shank and Sabuncuoglu Tezcan disclose the structure of claim 1, wherein each of the plurality of second cavity portions(upper portion of 450/420) are separated from the TSV(750) by a portion of the semiconductor substrate(100).
Re claim 9 Shank and Sabuncuoglu Tezcan disclose the structure of claim 1, wherein the plurality of second cavity portions(upper portion of 450/420) are equidistantly spaced around the TSV(750).
Re claim 10 Shank and Sabuncuoglu Tezcan disclose the structure of claim 1, wherein a distance between the first cavity portion(middle/bottom portion of 450/420) and a lower surface of the semiconductor substrate(100) is in a range of 4000 to 6000 nm.
Re claim 11 Shank and Sabuncuoglu Tezcan disclose the structure of claim 1, wherein a distance between the first cavity portion(middle/bottom portion of 450/420) and an upper surface of the semiconductor substrate(100) is in a range of 4000 to 6000 nm.
Re claim 12 Shank discloses a structure, comprising: a through semiconductor via (TSV(750)) in a semiconductor substrate(100); and a cavity including: a first cavity portion(middle/bottom portion of 450/420) in the semiconductor substrate(100) and surrounding a middle section of the TSV(750), and a plurality of second cavity portions(upper portion of 450/420) in the semiconductor substrate(100) and in fluid communication with the first cavity portion(middle/bottom portion of 450/420), wherein the plurality of second cavity portions(upper portion of 450/420) surrounds an upper section of the TSV(750), and wherein a portion of the semiconductor substrate(100) is between adjacent second cavity portions(upper portion of 450/420) and between each of the plurality of second cavity portions(upper portion of 450/420) and the TSV(750).
Shank discloses the first cavity portion(middle/bottom portion of 450/420) in direct contact with the TSV(750),
Sabuncuoglu Tezcan discloses in Fig 3a the first cavity portion(20) in direct contact with the TSV(5),
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Sabuncuoglu Tezcan to the teachings of Shank in order to reduce the capacitance [0002, Sabuncuoglu Tezcan].
Re claim 13 Shank and Sabuncuoglu Tezcan disclose the structure of claim 12, wherein the TSV(750) includes a dielectric liner(470) surrounding a conductor core and wherein the first cavity portion(middle/bottom portion of 450/420) is in direct contact with the dielectric liner(470).
Re claim 14 Shank and Sabuncuoglu Tezcan disclose the structure of claim 12, wherein each of the plurality of second cavity portions(upper portion of 450/420) have one of: an elongated, curved cross-sectional shape(see Fig 5/6 of Sabuncuoglu Tezcan) and a circular cross-sectional shape(see Fig 5/6 of Sabuncuoglu Tezcan).
Re claim 15 Shank and Sabuncuoglu Tezcan disclose the structure of claim 12, wherein the first cavity portion(middle/bottom portion of 450/420) surrounds approximately 80% of a height of the TSV(750).
Re claim 16 Shank and Sabuncuoglu Tezcan disclose the structure of claim 12, wherein each of the plurality of second cavity portions(upper portion of 450/420) have a passivation layer(820) on a sidewall of the semiconductor substrate(100).
Re claim 17 Shank and Sabuncuoglu Tezcan disclose the structure of claim 12, wherein the plurality of second cavity portions(upper portion of 450/420) are equidistantly spaced around the TSV(750).
Re claim 18 Shank and Sabuncuoglu Tezcan disclose the structure of claim 12, wherein a first distance between the first cavity portion(middle/bottom portion of 450/420) and a lower surface of the semiconductor substrate(100) is in a range of 4000 to 6000 nm, and a second distance between the first cavity portion(middle/bottom portion of 450/420) and an upper surface of the semiconductor substrate(100) is in a range of 4000 to 6000 nm.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812