Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 12/04/2025 have been fully considered but they are not persuasive.
The Applicant argues the rejection of previous claim 14 which has currently been amended into claim 1 of the Application. The Applicant states that the rejection of the limitation “a peak dopant concentration being located "within about 250 Angstroms or less of a substrate," is not taught by Kato, nor does Kato disclose a peak dopant concentration at all. These arguments are not persuasive.
Regarding the argument that Kato does not disclose a peak dopant concentration at all, a person having ordinary skills in the art will understand that the doped isolation region 408 of Kato (Para 16) inherently has a peak dopant concentration because the level of concentration in the doped isolation region 408 is the peak dopant concentration required for the doped isolation region 408 of the device to achieve the desired impact.
Regarding the argument that Kato fails to teach “a peak dopant concentration being located "within about 250 Angstroms or less of a substrate,” it can be seen that Kato’s doped isolation region 408 is within about 250 Angstroms or less of a substrate –i.e., portions of doped isolation region 408 are present at locations within about 250 Angstroms or less of a substrate.
The Applicant also stated that Fujisawa fails to disclose the argues limitation, however, the argument is moot because Fujisawa was not relied upon in making the rejection of the limitation.
Applicant’s arguments with respect to claims 19 and 40 have been considered but are moot since the scope of the claims are new and wherein the claims will be rejected in view of new ground of rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 19 and 40 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ramply et al. [US PGPUB 20220392856] (hereinafter Ramply).
Regarding claim 19, Ramply teaches a transistor device, comprising:
a substrate (201, Para 26);
a Group III-nitride semiconductor structure (214/216/218, Para 26-28) on the substrate (Fig. 3), the Group III-nitride semiconductor structure comprising a first channel structure (216 of device 251a, Para 24/27, Fig. 3) and a second channel structure (216 of device 251b, Para 24/27, Fig. 3) that is electrically isolated from the first channel structure (Fig. 3, i.e., electrically isolated by high resistivity regions 254, Para 37);
a source contact (260, Para 46) on the Group III-nitride semiconductor structure (Fig. 3);
a drain contact (264, Para 46) on the Group III-nitride semiconductor structure (Fig. 3);
wherein the first channel structure and the second channel structure each have a length extending in a first direction (horizontal direction, Fig. 3) that is generally perpendicular to a second direction (into the paper direction, Fig. 3) corresponding to a long dimension of the source contact and a long dimension of the drain contact (Fig. 3); and
wherein the Group III-nitride semiconductor structure has a recess (opening in which back metal layer 244 is formed, Fig. 3) between the first channel structure and the second channel structure, the recess having one or more sloped sidewalls (Fig. 3).
Regarding claim 40, Ramply teaches a method of forming a semiconductor device, comprising:
forming a Group III-nitride semiconductor structure (214/216/218, Para 26-28) on a substrate (201, Para 26, Fig. 4A);
implanting dopants (Para 33; i.e., isolation regions 252a and 252b may be formed via an implantation procedure) into the Group III-nitride semiconductor structure to form an isolation implant region (254, Para 33, Fig. 4B) in the Group III-nitride semiconductor structure (Fig. 4B), the isolation implant region separating the Group III-nitride semiconductor structure into a plurality of channel structures (Fig. 4B), the plurality of channel structures electrically isolated from one another (Fig. 4B; i.e., in view of the formation of region 254),
forming a first contact (260, Para 46) on the Group III-nitride semiconductor structure (Fig. 4C);
forming a second contact (264, Para 46) on the Group III-nitride semiconductor structure (Fig. 4C), the second contact spaced apart from the first contact (Fig. 4C);
wherein each of the plurality of channel structures has a length extending between the first contact and the second contact (Fig. 4C; at least when view in plan view);
wherein the isolation implant region extends along a length of one of the plurality of channel structures (Fig. 4C); and
wherein the implanted dopants have a peak dopant concentration at a depth in the isolation implant region within about 250 Angstroms or less of an interface between a barrier layer (218, Para 26) and a channel layer (216, Para 27, Fig. 4C; i.e., in view of the isolation implant region at least being in contact with edge of the barrier and channel layer).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7-8, 11-14, 17, 19, and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Ohno et al. [US Patent 6373082] in view of Ramply et al. [US PGPUB 20220392856] and in view of Kato et al. [US PGPUB 20070295991] (hereinafter Ohno, Ramply and Kato).
Regarding claim 1, Ohno teaches a semiconductor device, comprising:
a semiconductor structure (device of Fig. 1 excluding contacts 1 and 4, Col. 3, lines 57-58);
a first contact (1, Col. 3, line 57) on the semiconductor structure (Fig. 1);
a second contact (4, Col. 3, line 57) on the semiconductor structure, the second contact spaced apart from the first contact (Fig. 1);
wherein the semiconductor structure comprises a plurality of channel structures (3, Col. 3, lines 1-2/58) extending in a length direction between the first contact and the second contact (Fig. 1); and
wherein the semiconductor device comprises an isolation implant region (7, (1, Col. 2, line 62-64/ Col. 3, line 62) extending along at least a portion of a length of at least one of the plurality of channel structures (Fig. 1), wherein the isolation implant region comprises implanted dopants (Col. 3, lines 17-20).
Ohno does not specifically disclose that the semiconductor structure is a Group III-nitride semiconductor structure; and
wherein the implanted dopants have a peak dopant concentration at a depth in the isolation implant region within about 250 Angstroms or less of a substrate.
Referring to the invention of Ramply, Ramply teaches an exemplary structure of a field effect transistor, wherein the transistor comprises a Group III-nitride semiconductor structure (Para 26-29).
In view of such teaching by Ramply, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the device of Ohno comprise the teachings of Ramply at least based on the rationale of using known technique/material to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
Referring to the invention of Kato, Kato teaches forming isolation implant region (408, Para 16) extending at least partially into a substrate (substrate 41, Fig. 1 –wherein “or less of a substrate” as claimed suggests that the depth can reach the substrate).
In view of such teaching by Kato, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the modified invention comprise the teachings of Kato in order to have different types of FETs formed on a common substrate effectively isolated from one another.
Regarding claim 7, the modified invention of Ohno teaches the limitation of claim 1 upon which it depends.
The modified invention does not specifically disclose wherein each channel structure comprises a channel layer and a barrier layer, the barrier layer having a different bandgap relative to the channel layer.
However, referring to the invention of Ramply teaches a semiconductor device wherein a channel structure comprising a channel layer (216, Para 27) and a barrier layer (218, Para 28), the barrier layer having a different bandgap relative to the channel layer (Para 28).
In view of such further teaching by Ramply, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the device of Ohno comprise the teachings of Ramply (such that, each channel structure comprises a channel layer and a barrier layer, as claimed), at least based on the rationale of using known technique/material to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
Regarding claim 8, Ohno teaches a semiconductor device wherein the first contact comprises a source contact (Col. 3, line 57) and the second contact comprises a drain contact (Col. 3, line 58), wherein the semiconductor device further comprises a gate contact (2, Col. 3, lines 57/58), the gate contact having a long dimension extending generally perpendicular to the length of the plurality of channel structures (Fig. 1).
Regarding claim 11, the modified invention of Ohno teaches the limitation of claim 1 upon which it depends.
The modified invention does not specifically disclose wherein the isolation implant region extends through the channel structure to an interface between the channel structure and a substrate.
Referring to the invention of Kato, Kato teaches forming isolation implant region (408, Para 16) extending through channel structure 403 (Para 11) to an interface between the channel structure and a substrate (Fig. 1 –wherein layer 402 is a substrate for the channel structure 403, wherein layer 402 and 403 form an interface).
In view of such teaching by Kato, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the modified invention comprise the teachings of Kato in order to have different types of FETs formed on a common substrate effectively isolated from one another.
Regarding claim 12, the modified invention of Ohno teaches the limitation of claim 1 upon which it depends.
The modified invention does not specifically disclose wherein the isolation implant region extends at least partially into a substrate.
Referring to the invention of Kato, Kato teaches forming isolation implant region (408, Para 16) extending at least partially into a substrate (substrate 41, Fig. 1).
In view of such teaching by Kato, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the modified invention comprise the teachings of Kato in order to have different types of FETs formed on a common substrate effectively isolated from one another.
Regarding claim 13, the modified invention of Ohno teaches the limitation of claim 1 upon which it depends.
The modified invention does not specifically disclose wherein the implanted dopants comprise one or more of nitrogen, hydrogen, helium, zirconium, or oxygen.
Referring to the invention of Ramply, Ramply teaches that isolation region 254 can be formed by other material than boron (as taught by Ohno), to include one of nitrogen (N), boron (B), helium (He), hydrogen (H), oxygen (O), or a combination of these or one or a combination of other suitable ion species (Para 43).
In view of such teaching by Ramply, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the modified invention comprise the teachings of Ramply at least based on the rationale of simple substitution of one known element/structure with a suitable another to obtain predictable results (MPEP 2143.I.B).
Regarding claim 17, the modified invention of Ohno specifically in view of Ramply teaches a semiconductor device wherein the Group III-nitride semiconductor structure is on a substrate, the substrate comprising silicon carbide (Para 26).
In view of such teaching by Ramply, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the modified invention comprise the teachings of Ramply at least based on the rationale of simple substitution of one known element/structure with a suitable another to obtain predictable results (MPEP 2143.I.B).
Regarding claim 19, Ohno teaches a transistor device, comprising:
a substrate (not, shown, however, it is inherent for the transistor of Fig. 1 to have a substrate on which all the layer depicted are formed);
a semiconductor structure (device of Fig. 1 excluding contacts 1 and 4, Col. 3, lines 57-58) on the substrate (Fig. 1), the semiconductor structure comprising a first channel structure and a second channel structure that is electrically isolated from the first channel structure (Fig. 1; i.e., in view of channel portions 3 isolated from one another by isolation region 7 to form sub-channel -Col. 3, lines 1-2/58 and Col. 2, line 62-64/ Col. 3, line 62);
a source contact (1, Col. 3, line 57) on the semiconductor structure (Fig. 1);
a drain contact (4, Col. 3, line 57) on the semiconductor structure (Fig. 1); and
wherein the first channel structure and the second channel structure each have a length extending in a first direction that is generally perpendicular to a second direction corresponding to a long dimension of the source contact and a long dimension of the drain contact (Fig. 1).
Referring to the invention of Ramply, Ramply teaches an exemplary structure of a field effect transistor, wherein the transistor comprises a Group III-nitride semiconductor structure (Para 26-29).
In view of such teaching by Ramply, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the device of Ohno comprise the teachings of Ramply at least based on the rationale of using known technique/material to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
Regarding claim 40, Ohno teaches a method of forming a semiconductor device, comprising:
forming a semiconductor structure (device of Fig. 1 excluding contacts 1 and 4, Col. 3, lines 57-58) on a substrate (not, shown, however, it is inherent for the transistor of Fig. 1 to have a substrate on which all the layer depicted are formed);
implanting dopants into the semiconductor structure to form an isolation implant region in the semiconductor structure (isolation implant region 7, (1, Col. 2, line 62-64/ Col. 3, line 62 and Col. 3, lines 17-20), the isolation implant region separating semiconductor structure into a plurality of channel structures (Fig. 1), the plurality of channel structures electrically isolated from one another (claim 3);
forming a first contact (1, Col. 3, line 57) on the semiconductor structure (Fig. 1);
forming a second contact (4, Col. 3, line 57) on the semiconductor structure (Fig. 1), the second contact spaced apart from the first contact (Fig. 1);
wherein each of the plurality of channel structures has a length extending between the first contact and the second contact (Fig. 1); and
wherein the isolation implant region extends along a length of one of the plurality of channel structures (Fig. 1).
In view of such teaching by Ramply, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the device of Ohno comprise the teachings of Ramply at least based on the rationale of using known technique/material to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
Claims 2-4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Ohno in view of Ramply and Kato and further in view of Drowley et al. [US PGPUB 20210193846] (hereinafter Drowley).
Regarding claim 2, the modified invention of Ohno teaches the limitation of claim 1 upon which it depends.
The modified invention does not specifically disclose wherein the Group III-nitride semiconductor structure has a recess between the plurality of channel structures.
Referring to the invention of Drowley, Drowley teaches various isolation trench structures, wherein in an instance (Fig. 4F), the isolation structure of the device is an isolation implant region comprising a recess 407 and implant region 409 (Para 45, Fig. 4D-4F).
In view of such teaching by Drowley, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the device of Ohno comprise the teachings of Drowley at least based on the rationale of using known technique/material to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C), wherein the isolation structure is a suitable alternate isolation structure (MPEP 2143.I.B).
Regarding claim 3, the modified invention of Ohno teaches the limitation of claim 1 upon which it depends.
The modified invention does not specifically disclose wherein the recess extends through the Group III-nitride semiconductor structure to a substrate.
Referring to the invention of Kato, Kato teaches forming isolation implant region (408, Para 16) extending at least partially into a substrate (substrate 41, Fig. 1).
In view of such teaching by Kato, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the modified invention comprise the teachings of Kato in order to have different types of FETs formed on a common substrate effectively isolated from one another.
Regarding claim 4, the modified invention of Ohno specifically in view of Drowley teaches wherein the recess has one or more sloped sidewalls (Fig. 4F, i.e., 90º slope).
Regarding claim 10, the modified invention of Ohno teaches the limitation of claim 1 upon which it depends.
The modified invention does not specifically disclose wherein each channel structure comprises a second isolation implant region in the channel structure opposite the isolation implant region.
Referring to the invention of Drowley, Drowley teaches various isolation trench structures, wherein in an instance (Fig. 4F), the isolation structure of the device is an isolation implant region comprising a recess 407 and implant region 409 (Para 45, Fig. 4D-4F).
In view of such teaching by Drowley, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the device of Ohno comprise the teachings of Drowley at least based on the rationale of using known technique/material to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C), wherein the isolation structure is a suitable alternate isolation structure (MPEP 2143.I.B).
In view of such teaching by Drowley, the recess 407 is the second isolation region of the device.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ohno in view of Ramply and Kato and further in view of Fujisawa et al. [US Patent 6380602] (hereinafter Fujisawa).
Regarding claim 15, the modified invention of Ohno teaches the limitation of claim 1 upon which it depends.
The modified invention does not specifically disclose wherein the implanted dopants have a peak dopant concentration of at least about 1 x 1018 dopants/cm3.
Referring to the invention9 of Fujisawa, Fujisawa teaches forming an isolation region with a surface concentration of 1018 dopants/cm3 (Col. 8, lines 50-53).
In view of such teaching by Fujisawa, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the device of Ohno comprise the teachings of Fujisawa at least based on the rationale of using known technique/material to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
Claims 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ohno in view of Ramply and Kato and further in view of Wu et al. [US PGPUB US 20160190298] (hereinafter Wu).
Regarding claim 9, the modified invention of Ohno teaches the limitation of claim 1 upon which it depends.
The modified invention does not specifically disclose the semiconductor device further comprising a field plate.
Referring to the invention of Wu, Wu teaches forming the gate contact as a field plate (Para 60).
In view of such teaching by Wu, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the device of Ohno comprise the teachings of Wu to improve device performance (Wu, Para 60).
Regarding claim 16, the modified invention of Ohno teaches the limitation of claim 1 upon which it depends.
The modified invention does not specifically disclose wherein the Group III-nitride semiconductor structure is an N-polar Group III-nitride semiconductor structure.
However, referring to the invention of Ramply, Ramplyh teaches a layer of the semiconductor device (layer 214), wherein the layer is a Group III-nitride semiconductor layer which is an N-polar Group III-nitride semiconductor layer (Para 26).
At least in view such teaching, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the device of Ohno formed wherein the Group III-nitride semiconductor structure is an N-polar Group III-nitride semiconductor structure.
Referring to the invention of Wu, Wu, teaches forming transistors to have different structures, wherein in an instance the transistor is a polar III-N device (Para 10).
In view of such teaching by Wu, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the device of Ohno comprise the teachings of Wu at least based on the rationale of using known technique/material to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Ohno in view of Ramply and Kato and further in view of Mitsunaga et al. [US PGPUB 20120126291] (hereinafter Mitsunaga).
Regarding claim 18, the modified invention of Ohno teaches the limitation of claim 1 upon which it depends.
The modified invention does not specifically disclose wherein, wherein the semiconductor device comprises a high electron mobility transistor.
However, a person having ordinary skills in the art can reasonably consider the modified device of Ohno a high electron mobility transistor based on the fact that the modified device of Ohno has the same structure as the claimed present invention.
Moreover, referring to the invention of Mitsunaga, Mitsunaga teaches that high electron mobility transistors (HEMTs) are adapted as n-channel FETs (field-effect transistors (Para 2), and in another instance, the n-channel field-effect transistor region may include a HEMT (Para 9).
In view of such teaching by Mitsunaga, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the device of Ohno comprise the teachings of Mitsunaga at least based on the rationale of using known technique/material to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C).
Allowable Subject Matter
Claims 56-57 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 56 is allowed because all prior arts on record on record either singularly or in combination fail to anticipate or render obvious a semiconductor device comprising:
wherein the Group III-nitride semiconductor structure has a recess between the plurality of channel structures, a heat spreading layer being on the plurality of channel structures and in the recess, in combination with the rest of claim limitations as claimed and defined by the Applicant.
Claim 57 is allowed because all prior arts on record on record either singularly or in combination fail to anticipate or render obvious a semiconductor device comprising:
wherein each channel structure of the plurality of channel structures has a first width and the recess between the plurality of channel structures has a second width, wherein a ratio of the first width to the second width is in a range of about 0.5:1 to about 2:1, in combination with the rest of claim limitations as claimed and defined by the Applicant.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ISMAIL A MUSE/ Primary Examiner, Art Unit 2812
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