DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 10, 2026 has been entered due to the RCE filed on June 23, 2026.
Response to Amendment
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 17-22, and 30-35 are rejected under 35 U.S.C. 103 as being unpatentable over Fung et al. (“Fung”), US 2018/0315837, in view of Chang et al. (“Chang”), US 9,520,482 (listed in the IDS filed 9/26/2023).
Regarding Claim 1, Fung discloses a device (Figs. 1E-2; ¶ 0004-0005), comprising:
a first region (middle portion of left side drawings of Figs. 1E-1F; ¶ 0005) that includes:
a first segment of an active region (middle portion of 104; Fig. 1E, portion 204 of Fig. 2; ¶ 0024, ¶ 0031 “portion of the fin structure 104 underneath the gate structure”, ¶ 0033 “portion 204 where the gate structure overlaps”);
a metal-containing gate electrode structure (114, 116, 117; Fig. 1F; ¶ 0028, 0030 “aluminum, tantalum, tungsten”) disposed over the first segment of the active region (drawing on the right of Fig. 1F; ¶ 0031 “portion of the fin structure 104 underneath the gate structure”) in a vertical direction (bottom to top of the drawing on the right of Fig. 1F) in a first cross-sectional side view (drawing on the right of Fig. 1F; ¶ 0016 “The right side…illustrates a cross-sectional view of the fin structure 104 corresponding to cross-section A as illustrated in the top view.”), wherein the first cross-sectional side view is defined by the vertical direction and a first horizontal direction (left to right of the left side drawings of Fig. 1F; ¶ 0016 “cross-section A as illustrated in the top view”), and wherein the metal-containing gate electrode structure at least partially wraps around the first segment of the active region in the first cross-sectional side view (Fig. 1F; ¶ 0028 “metal gate 117 is formed within the trench 115 that was formed by the etching process 111”, ¶ 0031 “portion of the fin structure 104 underneath the gate structure”); and
a second region (top and bottom portion of left side drawings of Figs. 1B-1F; ¶ 0005) that includes:
a second segment of the active region (104 extending from under the top and bottom gate spacers 105 on the left side drawings of Figs. 1B-1F, portion 202 of Fig. 2; ¶ 0022 “the portions 109 of the fin structure that are not covered by the dummy gate structure 108”, ¶ 0033 “portions 202 not covered by a gate structure”); and
a dielectric structure (110; left side drawings of Figs. 1C-1F; ¶ 0015 “portions of the fin structure are covered by the ILD”, ¶ 0022 “ILD layer 110”) disposed over the second segment of the active region in the vertical direction in the first cross-sectional side view (Figs. 1C-1F; ¶ 0022 “109 of the fin structure” “remain covered by the ILD layer 110”) or in the second cross-sectional side view (this limitation is part of a conditional “or” statement and is not required by the prior art), wherein the second segment of the active region (202; Fig. 2; ¶ 0033 fin “portions 202 not covered by a gate structure”) is thicker than (Fig. 2 width 206 is thicker than width 210; ¶ 0031 “regions not corresponding to the gate structure may have a greater width”, 0033 “portions 202 not covered by a gate structure remain the original width 206”) the first segment (204; Fig. 2; ¶ 0033 fin “portion 204 where the gate structure overlaps”) of the active region in a planar top view (Fig. 1E, 2; ¶ 0016 “illustrates a top view”, ¶ 0033).
Fung does not disclose
a gate spacer disposed on a side surface of the metal-containing gate electrode structure in a second cross-sectional side view, wherein the second cross-sectional side view is defined by the vertical direction and a second horizontal direction different from the first horizontal direction, wherein the metal-containing gate electrode structure interfaces with an upper surface of a first portion of the first segment of the active region in the second cross-sectional side view, wherein the gate spacer interfaces with an upper surface of a second portion of the first segment of the active region in the second cross-sectional side view, and wherein the first portion of the first segment of the active region has a same vertical direction as the second portion of the first segment of the active region in the second cross-sectional side view; and
wherein the upper surface of the second portion of the first segment of the active region is located at a higher position in the vertical direction than an upper surface of the second segment of the active region in the second cross-sectional side view, and wherein the second portion of the first segment of the active region has a greater dimension in the vertical direction than the second segment of the active region in the second cross-sectional side view.
Chang discloses a gate spacer (245; Figs. 2A and 16B; col. 9 lines 21-22 “sidewall spacers 245”) disposed on a side surface (Figs. 2A and 16B; col. 4 line 1) of the metal-containing gate electrode structure (414; Fig. 16B; col. 5 lines 20-22 “gate metal layer 414”) in a second cross-sectional side view (Figs. 2A, 16B; col. 2 lines 8-11 “FIGS. 16B…are cross-sectional views of an example semiconductor device in accordance with some embodiments, along the line AA-AA in FIG. 2A.”), wherein the second cross-sectional side view is defined by the vertical direction (bottom to top of Fig. 16B) and a second horizontal direction (along the line AA-AA in FIG. 2A; col. 2 lines 8-11 “FIGS. 16B…are cross-sectional views of an example semiconductor device in accordance with some embodiments, along the line AA-AA in FIG. 2A.”) different from the first horizontal direction (along the line B-B in FIG. 2A; col. 2 lines 12-15 “FIGS. 16C…are cross-sectional views of an example semiconductor device in accordance with some embodiments, along the line B-B in FIG. 2A.”), wherein the metal-containing gate electrode structure (414) interfaces with an upper surface (Fig. 16B the upper surface of 242; col. 3 line 60 “gate regions 242”) of a first portion (Fig. 16B the middle portion of 230) of the first segment (242; Fig. 16B; col. 3 line 60 “gate regions 242”) of the active region (230 of 210; Fig. 16B; col. 3 lines 60-61 “substrate 210, including…a portion of the fin features 230”; col. 3 lines 32-33 “substrate 210 may further include various active regions”) in the second cross-sectional side view (Figs. 2A, 16B), wherein the gate spacer (245) interfaces with an upper surface (Fig. 16B the upper surface of 242; col. 3 line 60 “gate regions 242”) of a second portion (Fig. 16B the left or right portions of 230) of the first segment (242; Fig. 16B; col. 3 line 60 “gate regions 242”) of the active region (230 of 210; Fig. 16B; col. 3 lines 60-61 “substrate 210, including…a portion of the fin features 230”; col. 3 lines 32-33 “substrate 210 may further include various active regions”) in the second cross-sectional side view (Fig. 16B),and wherein the first portion of the first segment of the active region has a same vertical direction (Fig. 16B a bottom to top “vertical direction”) as the second portion of the first segment of the active region in the second cross-sectional side view (Fig. 16B); and
wherein the upper surface of the second portion (Fig. 16B the left or right portions of 230) of the first segment of the active region is located at a higher position in the vertical direction (Fig. 16B the second portion is vertically higher than the upper surface of the second segment) than an upper surface (Fig. 16B the upper surface of 252; col. 4 lines 10-11 “source/drain (S/D) features 250 in source/drain regions 252 over the substrate 210”) of the second segment (252; Fig. 16B; col. 4 lines 10-11 “source/drain (S/D) features 250 in source/drain regions 252 over the substrate 210”) of the active region in the second cross-sectional side view (Fig. 16B), and wherein the second portion of the first segment of the active region has a greater dimension in the vertical direction (Fig. 16B in this instance the second portion has a greater height from the bottom of substrate 210 in the vertical direction than a height from the bottom of substrate 210 of the second segment) than the second segment (252) of the active region in the second cross-sectional side view (Fig. 16B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Fung to have a gate spacer disposed on a side surface of the metal-containing gate electrode structure in a second cross-sectional side view, wherein the second cross-sectional side view is defined by the vertical direction and a second horizontal direction different from the first horizontal direction, wherein the metal-containing gate electrode structure interfaces with an upper surface of a first portion of the first segment of the active region in the second cross-sectional side view, wherein the gate spacer interfaces with an upper surface of a second portion of the first segment of the active region in the second cross-sectional side view, and wherein the first portion of the first segment of the active region has a same vertical direction as the second portion of the first segment of the active region in the second cross-sectional side view; and wherein the upper surface of the second portion of the first segment of the active region is located at a higher position in the vertical direction than an upper surface of the second segment of the active region in the second cross-sectional side view, and wherein the second portion of the first segment of the active region has a greater dimension in the vertical direction than the second segment of the active region in the second cross-sectional side view, as taught by Chang, in order to “protect…the metal gate stack” (Chang, col. 12 lines 21-23), thereby improving the reliability of the device.
Regarding Claim 2, Fung discloses wherein the active region (104; Fig. 1A; ¶ 0016) includes a fin structure (Fig. 1A; ¶ 0016 “fin structure 104”) that protrudes vertically out of a substrate (¶ 0018 “fin structure 104 may be fabricated by patterning the substrate 102”, ¶ 0036 “the substrate may be etched to remove material at regions not corresponding to the fin structure”) in the first cross-sectional side view (Figs. 1A-1F).
Regarding Claim 3, Fung discloses wherein:
the planar top view is defined by the first horizontal direction (horizontal direction of the left side drawing of Fig. 1F, horizontal direction of Fig. 2) and the second horizontal direction (vertical direction of the left side drawing of Fig. 1F, vertical direction of Fig. 2), wherein the second horizontal direction is perpendicular to the first horizontal direction (left side drawing of Fig. 1F, Fig. 2);
the first region and the second region form an interface (the interface between 104 under 105 and 104 under 116, also the interface between 202 and 204; Figs 1B-1F and Fig. 2; ¶ 0019, 0033-0034) in the planar top view (left side drawings of Figs 1B-1F, Fig. 2); and
the interface extends in the first horizontal direction in the planar top view (left side drawings of Figs 1B-1F, Fig. 2).
Regarding Claim 4, Fung discloses wherein:
the first segment has a first horizontal dimension (210; Fig. 2; ¶ 0033 “smaller width 210”) in the first horizontal direction (Fig. 2);
the second segment has a second horizontal dimension (206; Fig. 2; ¶ 0033 “width 206”) in the first horizontal direction (Fig. 2).
Fung does not specifically disclose a ratio between the second horizontal dimension and the first horizontal dimension is in a range between about 4:1 and about 6:1.
MPEP 2144.04(IV)( A) describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Fung to have a ratio between the second horizontal dimension and the first horizontal dimension is in a range between about 4:1 and about 6:1 so that “regions not corresponding to the gate structure may have a greater width and provide greater mechanical stability” and “the smaller width at the portion of the fin structure 104 underneath the gate structure has a reduced width so as to provide better device performance” (Fung ¶ 0031; see also Fung ¶ 0014-0015, 0043, 0046).
Regarding Claim 5, Fung discloses wherein the first segment of the active region is continuous with the second segment of the active region (Figs. 1A-2; ¶ 0018 “the fin structure 104 on the substrate 102 may be made of the same originally deposited layer or wafer”, ¶ 0029 “The channel is the part of the fin structure extending between the source/drain regions 101.”, ¶ 0036 “the substrate may be etched to remove material at regions not corresponding to the fin structure”).
Regarding Claim 6, Fung specifically discloses wherein the active region is a first active region (104 in Fig. 1E and 204 in Fig. 2);
Fung does not specifically disclose wherein:
the device further includes a second active region;
the metal-containing gate electrode structure is disposed over a third segment of the second active region;
the dielectric structure is disposed over a fourth segment of the second active region;
the third segment of the second active region is separated from the first segment of the first active region by a first distance in the planar top view;
the fourth segment of the second active region is separated from the second segment of the first active region by a second distance in the planar top view; and
the first distance is greater than the second distance.
Fung states “while only a single transistor is illustrated in relation to the fin structure 104, it may be the case that multiple transistors are formed” (¶ 0031). See also Duplication of Parts, M.P.E.P. 2144.04 (VI) (B) - In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (The court held that mere duplication of parts has no patentable significance).
Regarding the remaining limitations of Claim 6, if two adjacent fins 104 having original width 206 (Fig. 2) are similarly etched then the resulting device structure would be what is shown in the annotated Fig. 2 infra. Specifically, it has
the device further includes a second active region (second 104 in the duplicate transistor seen on the right side in the annotate Fig. 2 infra);
the metal-containing gate electrode structure is disposed over a third segment of the second active region (the elements 114, 116, and 117 in Fig. 1F that would be part of second active region 104);
the dielectric structure is disposed over a fourth segment of the second active region (110 in Fig. 1F that would be part of the second active region);
the third segment of the second active region is separated from the first segment of the first active region (regions 204) by a first distance (the middle arow in annotated Fig. 2 infra) in the planar top view (annotated Fig. 2);
the fourth segment of the second active region is separated from the second segment of the first active region (regions 202) by a second distance (the top and bottom arrows in annotated Fig. 2 infra) in the planar top view (annotated Fig. 2); and
the first distance is greater than the second distance (the middle arrow is greater/wider in the horizontal direction than the top and bottom arrows).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Fung to have the duplicate second transistor adjacent the first transistor which would include the second active region and the elements describes supra, so that “regions not corresponding to the gate structure may have a greater width and provide greater mechanical stability” and “the smaller width at the portion of the fin structure underneath the gate structure has a reduced width so as to provide better device performance” (Fung ¶ 0043; see also Fung ¶ 0015-0016, 0031, 0046).
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Regarding Claim 7, Fung does not disclose wherein a ratio between the first distance and the second distance is in a range between about 1.3:1 and about 2:1.
MPEP 2144.04(IV)( A) describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Fung to have a ratio between the first distance and the second distance is in a range between about 1.3:1 and about 2:1 so that “regions not corresponding to the gate structure may have a greater width and provide greater mechanical stability” and “the smaller width at the portion of the fin structure underneath the gate structure has a reduced width so as to provide better device performance” (Fung ¶ 0043; see also Fung ¶ 0015-0016, 0031, 0046).
Regarding Claim 17, Fung discloses a device (Figs. 1E-2; ¶ 0004-0005), comprising:
an active region (104; Figs. 1A-1F, 2; ¶ 0016, 0033) that protrudes upwards in a vertical direction (bottom to top of right side drawing of Fig. 1A; ¶ 0016, ¶ 0018 “fin structure 104 may be fabricated by patterning the substrate 102”, ¶ 0036 “the substrate may be etched to remove material at regions not corresponding to the fin structure”) in a first cross-sectional side view (right side drawings of Figs. 1A-1F; ¶ 0016 “The right side of FIG. 1A illustrates a cross-sectional view of the fin structure 104 corresponding to cross-section A as illustrated in the top view.”), wherein the first cross-sectional side view is defined by the vertical direction and a first horizontal direction (left to right of the left side drawings of Figs. 1E-1F; ¶ 0016 “cross-section A as illustrated in the top view”);
a gate electrode (114, 116, 117; Fig. 1F; ¶ 0028) that at least partially wraps around the active region (drawing on the right side of Fig. 1F; ¶ 0019 “deposited over the fin structure 104”, ¶ 0028 “metal gate 117 is formed within the trench 115”, ¶ 0031 “fin structure 104 underneath the gate structure”) in the first cross-sectional side view (right side drawing of Fig. 1F); and
wherein:
the gate electrode extends in the first horizontal direction (horizontal direction of the left side drawing of Fig. 1F, ¶ 0016 “cross-section A as illustrated in the top view”) in a top view (drawing on the left side of Fig. 1F; ¶ 0016 “illustrates a top view”);
the active region extends in the second horizontal direction (104 extends in the vertical direction of the left side drawing of Fig. 1F and Fig. 2 ) in the top view (left side drawing of Fig. 1F and Fig. 2), and
a first portion of the active region located outside of the gate electrode (202; Fig. 2; ¶ 0033 fin “portions 202 not covered by a gate structure”) is thicker in the first horizontal direction (Fig. 2 width 206 is thicker than width 210; ¶ 0031 “regions not corresponding to the gate structure may have a greater width” “the portion of the fin structure 104 underneath the gate structure has a reduced width”, 0033) than a second portion of the active region wrapped under the gate electrode (204; Fig. 2; ¶ 0033 fin “portion 204 where the gate structure overlaps”).
Fung does not specifically disclose
a gate spacer disposed on a side surface of the gate electrode in a second cross-sectional side view, wherein the second cross-sectional side view is defined by the vertical direction and a second horizontal direction different from the first horizontal direction;
the gate electrode is disposed over and interfaces with an upper surface of a first segment of the second portion of the active region in the second cross-sectional side view;
the gate spacer is disposed over and interfaces with an upper surface of a second segment of the second portion of the active region in the second cross-sectional side view;
the first segment of the second portion of the active region has a same dimension as the second segment of the second portion of the active region in the second cross-sectional side view; and
the second segment of the second portion of the active region has a greater vertical elevation and a greater vertical dimension than the first portion of the active region in the second cross-sectional side view.
Chang discloses
a gate spacer (245; Figs. 2A and 16B; col. 9 lines 21-22 “sidewall spacers 245”) disposed on a side surface (Figs. 2A and 16B; col. 4 line 1) of the gate electrode (414; Fig. 16B; col. 5 lines 20-22 “gate metal layer 414”) in a second cross-sectional side view (Figs. 2A, 16B; col. 2 lines 8-11 “FIGS. 16B…are cross-sectional views of an example semiconductor device in accordance with some embodiments, along the line AA-AA in FIG. 2A.”), wherein the second cross-sectional side view is defined by the vertical direction (bottom to top of Fig. 16B) and a second horizontal direction (along the line AA-AA in FIG. 2A; col. 2 lines 8-11 “FIGS. 16B…are cross-sectional views of an example semiconductor device in accordance with some embodiments, along the line AA-AA in FIG. 2A.”) different from the first horizontal direction (along the line B-B in FIG. 2A; col. 2 lines 12-15 “FIGS. 16C…are cross-sectional views of an example semiconductor device in accordance with some embodiments, along the line B-B in FIG. 2A.”);
the gate electrode (414; Fig. 16B; col. 5 lines 20-22 “gate metal layer 414”) is disposed over and interfaces with an upper surface (Fig. 16B the upper surface of 242; col. 3 line 60 “gate regions 242”) of a first segment (Fig. 16B the middle portion of 242) of the second portion (242; Fig. 16B; col. 3 line 60 “gate regions 242”) of the active region (230 of 210; Fig. 16B; col. 3 lines 60-61 “”substrate 210, including…a portion of the fin features 230”; col. 3 lines 32-33 “substrate 210 may further include various active regions”) in the second cross-sectional side view (Figs. 2A, 16B; col. 2 lines 8-11 “Figs. 16B…are cross-sectional views of an example semiconductor device in accordance with some embodiments, along the line AA-AA in FIG. 2A”);
the gate spacer (245) is disposed over and interfaces with an upper surface (Fig. 16B the upper surface of 242; col. 3 line 60 “gate regions 242”) of a second segment (Fig. 16B the left or right portions of 242) of the second portion (242; Fig. 16B; col. 3 line 60 “gate regions 242”) of the active region (230 of 210; Fig. 16B; col. 3 lines 60-61 “substrate 210, including…a portion of the fin features 230”; col. 3 lines 32-33 “substrate 210 may further include various active regions”) in the second cross-sectional side view (Fig. 16B);
the first segment (Fig. 16B the middle portion of 242) of the second portion of the active region has a same dimension (Fig. 16B in this instance the middle portion of 242 has a same vertical height dimension as a vertical height dimension of left or right portions of 242) as the second segment (Fig. 16B the left or right portions of 242) of the second portion of the active region in the second cross-sectional side view (Fig. 16B); and
the second segment (Fig. 16B the left or right portions of 242) of the second portion of the active region has a greater vertical elevation (Fig. 16B the left or right portions of 242 have a greater vertical elevation than a vertical elevation of first portion 252) and a greater vertical dimension (Fig. 16B in this instance the left or right portions of 242 have a greater vertical height from the bottom of substrate 210 than a vertical height from the bottom of substrate 210 of first portion 252) than the first portion (252; Fig. 16B; col. 4 lines 10-11 “source/drain (S/D) features 250 in source/drain regions 252 over the substrate 210”) of the active region (col. 3 lines 32-33 “substrate 210 may further include various active regions”) in the second cross-sectional side view (Fig. 16B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Fung to have a gate spacer disposed on a side surface of the gate electrode in a second cross-sectional side view, wherein the second cross-sectional side view is defined by the vertical direction and a second horizontal direction different from the first horizontal direction; the gate electrode is disposed over and interfaces with an upper surface of a first segment of the second portion of the active region in the second cross-sectional side view; the gate spacer is disposed over and interfaces with an upper surface of a second segment of the second portion of the active region in the second cross-sectional side view; the first segment of the second portion of the active region has a same dimension as the second segment of the second portion of the active region in the second cross-sectional side view; and the second segment of the second portion of the active region has a greater vertical elevation and a greater vertical dimension than the first portion of the active region in the second cross-sectional side view, as taught by Chang, in order to “protect…the metal gate stack” (Chang, col. 12 lines 21-23), thereby improving the reliability of the device.
Regarding Claim 18, Fung discloses wherein the first portion of the active region extends to the second portion of the active region (Figs. 1A-2; ¶ 0018 “the fin structure 104 on the substrate 102 may be made of the same originally deposited layer or wafer”, ¶ 0029 “The channel is the part of the fin structure extending between the source/drain regions 101.”, ¶ 0036 “the substrate may be etched to remove material at regions not corresponding to the fin structure”).
Regarding Claim 19, Fung discloses wherein the first portion of the active region is at least 1.3 times thicker than the second portion of the active region in the first horizontal direction (Fig. 2; ¶ 0026 “the etching process 113 may be configured to reduce the width of the fin structure to a width value that is less than the predetermined threshold width value”, “the measured width is 20 nanometers, then the etching process 113 may be applied to reduce the width of the fin structure by about 10 nanometers” therefore in this instance the first portion of the active region is 2 times thicker than the second portion of the active region in the first horizontal direction, and “if the measured width is 15 nanometers, then the etching process 113 may be configured to reduce the width of the fin structure 104 by about 5 nanometers” therefore in this instance the first portion of the active region is 1.5 times thicker than the second portion of the active region in the first horizontal direction, ¶ 0042).
Regarding Claim 20, Fung specifically discloses wherein the active region is a first fin structure (104 in both Fig. 1E and Fig. 2);
Fung does not specifically disclose wherein:
the device further comprises a second fin structure that is substantially parallel to the first fin structure;
a dielectric structure overlaps with both the first portion of the first fin structure and a third portion of the second fin structure in the top view;
the gate electrode overlaps with both the second portion of the first fin structure and a fourth portion of the second fin structure in the top view;
a first distance separates the first portion of the first fin structure and the third portion of the second fin structure;
a second distance separates the second portion of the first fin structure and the fourth portion of the second fin structure; and
the second distance is at least 1.3 times greater than the first distance.
Fung states “while only a single transistor is illustrated in relation to the fin structure 104, it may be the case that multiple transistors are formed” (¶ 0031). See also Duplication of Parts, M.P.E.P. 2144.04 (VI) (B) - In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (The court held that mere duplication of parts has no patentable significance).
Regarding the second to sixth subparagraphs of Claim 20, if two adjacent fins 104 having original width 206 (Fig. 2) are similarly etched then the resulting device structure would be what is shown in the annotated Fig. 2 supra. Specifically, it has:
the device further comprises a second fin structure that is substantially parallel to the first fin structure (second 104 in the duplicate transistor seen on the right side in the annotate Fig. 2 infra);
a dielectric structure overlaps with both the first portion of the first fin structure and a third portion of the second fin structure in the top view (110 in Fig. 1F that would be part of the second active region);
the gate electrode overlaps with both the second portion of the first fin structure and a fourth portion of the second fin structure in the top view (the elements 114, 116, and 117 in Fig. 1F that would be part of second active region 104);
a first distance (the top and bottom arrows in annotated Fig. 2 supra) separates the first portion of the first fin structure and the third portion of the second fin structure (regions 202);
a second distance (the middle arow in annotated Fig. 2 supra) separates the second portion of the first fin structure and the fourth portion of the second fin structure (regions 204).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Fung to have the duplicate second transistor adjacent the first transistor which would include the second fin structure and the elements describes supra, so that “regions not corresponding to the gate structure may have a greater width and provide greater mechanical stability” and “the smaller width at the portion of the fin structure underneath the gate structure has a reduced width so as to provide better device performance” (Fung ¶ 0043; see also Fung ¶ 0015-0016, 0031, 0046).
Fung as modified does not specifically disclose the second distance is at least 1.3 times greater than the first distance.
MPEP 2144.04(IV)( A) describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Fung as modified to have the second distance is at least 1.3 times greater than the first distance so that “regions not corresponding to the gate structure may have a greater width and provide greater mechanical stability” and “the smaller width at the portion of the fin structure underneath the gate structure has a reduced width so as to provide better device performance” (Fung ¶ 0043; see also Fung ¶ 0015-0016, 0031, 0046).
Regarding Claim 21, Fung discloses further comprising:
a first source/drain component (610a; Fig. 7D; ¶ 0058 “source/drain regions 610a”) formed over the first fin structure (602a; Figs. 7A-7D; ¶ 0058 “fin structures 602a”); and
a second source/drain component (610b; Fig. 7D; ¶ 0058 “source/drain regions… 610b”) formed over the second fin structure (602b; Figs. 7A-7D; ¶ 0058 “fin structures… 602b”), wherein the first source/drain component and the second source/drain component are merged together (Fig. 7D; ¶ “the source/drain regions 610a, 610b are grown large enough so that they merge together”).
Regarding Claim 22, Fung discloses wherein at least a part of the second portion of the active region has a non-linear profile (Figs. 1E, 2; ¶ 0034 “the width gradually changes in the regions 212…between portions 202 and 204”) in the top view (Figs. 1E, 2).
Regarding Claim 30, Fung discloses a device (Figs. 1E-2; ¶ 0004-0005), comprising:
a metal-containing gate electrode (116 of 117; Fig. 1F; ¶ 0028 “metal gate 117 includes a gate dielectric layer 114 and a metal layer 116”, ¶ 0030 “metal layer 116…aluminum, tantalum, tungsten”) that extends in a first horizontal direction (left to right of left side drawing of Fig. 1F; ¶ 0016 “cross-section A as illustrated in the top view”) in a top view (left side drawing of Fig. 1F; ¶ 0016 “the top view”);
a first segment of a semiconductor fin structure (middle portion of 104; Fig. 1E, portion 204 of Fig. 2; ¶ 0024, ¶ 0031 “portion of the fin structure 104 underneath the gate structure”, ¶ 0033 “portion 204 where the gate structure overlaps”) that extends in a second horizontal direction (the vertical direction of the left side drawing in Fig. 1E, the vertical direction of Fig. 2) in the top view (left side drawing of Fig. 1E, Fig. 2), wherein the metal-containing gate electrode at least partially wraps around the first segment of the semiconductor fin structure (Fig. 1F; ¶ 0028 “metal gate 117 is formed within the trench 115 that was formed by the etching process 111”, ¶ 0031 “portion of the fin structure 104 underneath the gate structure”) in a first cross-sectional side view (right side drawing of Fig. 1F), and wherein the first cross-sectional side view is defined by a vertical direction (bottom to top of the right side drawing of Fig. 1F) and the first horizontal direction (right side drawing of Fig. 1F; ¶ 0016 “The right side…illustrates a cross-sectional view of the fin structure 104 corresponding to cross-section A as illustrated in the top view.”);
a second segment (104 extending from under the top and bottom spacers 105 on the left side drawings of Figs. 1B-1F; portion 202 of Fig. 2; ¶ 0022 “portions 109 of the fin structure that are not covered by the dummy gate structure 108”, ¶ 0033 “portions 202 not covered by a gate structure”) of the semiconductor fin structure that extends in the second horizontal direction in the top view (left side drawings of Figs. 1B-1F, Fig. 2), wherein the second segment of the semiconductor fin structure is located outside of the metal-containing gate electrode in the top view (104 extending from under the top and bottom spacers 105 on the left side drawings of Figs. 1B-1F; portion 202 of Fig. 2; ¶ 0022 “portions 109 of the fin structure that are not covered by the dummy gate structure 108”, ¶ 0033 “portions 202 not covered by a gate structure”), and wherein the second segment of the semiconductor fin structure has a greater dimension (Fig. 2 width 206 has a greater dimension than width 210; ¶ 0031 “regions not corresponding to the gate structure may have a greater width”, ¶ 0033 “portions 202 not covered by a gate structure remain the original width 206”) than the first segment of the semiconductor fin structure in the first horizontal direction in the top view (Figs. 1E and 2).
Fung does not disclose a gate spacer disposed on a side surface of the metal-containing gate electrode in a second cross-sectional side view, wherein the second cross-sectional side view is defined by the vertical direction and the second horizontal direction, wherein the metal-containing gate electrode is disposed over and interfaces with an upper surface of a first region of the first segment of the semiconductor fin structure in the second cross-sectional side view, wherein the gate spacer is disposed over and interfaces with an upper surface of a second region of the first segment of the semiconductor fin structure in the second cross-sectional side view, wherein the second region of the first segment of the semiconductor fin structure has a high vertical elevation and a greater vertical dimension than the second segment of the semiconductor fin structure in the second cross-sectional side view.
Chang discloses a gate spacer (245; Figs. 2A and 16B; col. 9 lines 21-22 “sidewall spacers 245”) disposed on a side surface (Figs. 2A and 16B; col. 4 line 1) of the metal-containing gate electrode (414; Fig. 16B; col. 5 lines 20-22 “gate metal layer 414”) in a second cross-sectional side view (Figs. 2A, 16B; col. 2 lines 8-11 “FIGS. 16B…are cross-sectional views of an example semiconductor device in accordance with some embodiments, along the line AA-AA in FIG. 2A.”), wherein the second cross-sectional side view is defined by the vertical direction (bottom to top of Fig. 16B) and the second horizontal direction (along the line AA-AA in FIG. 2A; col. 2 lines 8-11 “FIGS. 16B…are cross-sectional views of an example semiconductor device in accordance with some embodiments, along the line AA-AA in FIG. 2A.”), wherein the metal-containing gate electrode (414) is disposed over and interfaces with (Fig. 16B; col. 3 lines 60-61 “over a portion of the fin features 230”) an upper surface (Fig. 16B the upper surface of 242; col. 3 line 60 “gate regions 242”) of a first region (Fig. 16B the middle portion of 230) of the first segment (242; Fig. 16B; col. 3 line 60 “gate regions 242”) of the semiconductor fin structure (230; Fig. 16B; col. 3 line 52 “fin feature 230”) in the second cross-sectional side view (Fig. 16B), wherein the gate spacer (245) is disposed over and interfaces with an upper surface (Fig. 16B the upper surface of 242; col. 3 line 60 “gate regions 242”) of a second region (Fig. 16B the left or right portions of 230) of the first segment (242; Fig. 16B; col. 3 line 60 “gate regions 242”) of the semiconductor fin structure (230; Fig. 16B; col. 3 line 52 “fin feature 230”) in the second cross-sectional side view (Fig. 16B), wherein the second region (Fig. 16B the left or right portions of 230) of the first segment of the semiconductor fin structure has a high vertical elevation (Fig. 16B the left or right portions 230 have “a high” vertical elevation) and a greater vertical dimension (Fig. 16B in this instance the second region has a greater height from the bottom of substrate 210 in the vertical direction than a height from the bottom of substrate 210 of the second segment) than the second segment (252; Fig. 16B; col. 4 lines 10-11 “source/drain (S/D) features 250 in source/drain regions 252 over the substrate 210”) of the semiconductor fin structure (230; Fig. 16B; col. 3 line 52 “fin feature 230”) in the second cross-sectional side view (16B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Fung to have a gate spacer disposed on a side surface of the metal-containing gate electrode in a second cross-sectional side view, wherein the second cross-sectional side view is defined by the vertical direction and the second horizontal direction, wherein the metal-containing gate electrode is disposed over and interfaces with an upper surface of a first region of the first segment of the semiconductor fin structure in the second cross-sectional side view, wherein the gate spacer is disposed over and interfaces with an upper surface of a second region of the first segment of the semiconductor fin structure in the second cross-sectional side view, wherein the second region of the first segment of the semiconductor fin structure has a high vertical elevation and a greater vertical dimension than the second segment of the semiconductor fin structure in the second cross-sectional side view, as taught by Chang, in order to “protect…the metal gate stack” (Chang, col. 12 lines 21-23), thereby improving the reliability of the device.
Regarding Claim 31, Fung discloses wherein the first segment of the semiconductor fin structure is contiguous with the second segment of the semiconductor fin structure (Figs. 1A-2; ¶ 0018 “the fin structure 104 on the substrate 102 may be made of the same originally deposited layer or wafer”, ¶ 0029 “The channel is the part of the fin structure extending between the source/drain regions 101.”, ¶ 0036 “the substrate may be etched to remove material at regions not corresponding to the fin structure”).
Regarding Claim 32, Fung does not disclose further comprising a dielectric structure that is disposed over the second segment of the semiconductor fin structure in the second cross- sectional side view.
Chang discloses further comprising a dielectric structure (260; Fig. 16B; col. 4 lines 38-39 “interlayer dielectric (ILD) layer 260”) that is disposed over the second segment (252; Fig. 16B; col. 4 line 11 “source/drain regions 252”) of the semiconductor fin structure in the second cross- sectional side view (Fig. 16B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Fung to have further comprising a dielectric structure that is disposed over the second segment of the semiconductor fin structure in the second cross- sectional side view, as taught by Chang, in order to “protect…the metal gate stack” (Chang, col. 12 lines 21-23), thereby improving the reliability of the device.
Regarding Claim 33, Fung discloses wherein a dimension (206; Fig. 2; ¶ 0033 “width 206”) of the second segment of the semiconductor fin structure and a dimension (210; Fig. 2; ¶ 0033 “smaller width 210”) of the first segment of the semiconductor fin structure in the first horizontal direction (Fig. 2).
Fung does not specifically disclose a ratio between the dimension of the second segment and the dimension of the first segment is in a range between about 4:1 and about 6:1.
MPEP 2144.04(IV)( A) describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Fung to have a ratio between the dimension of the second segment and the dimension of the first segment is in a range between about 4:1 and about 6:1 so that “regions not corresponding to the gate structure may have a greater width and provide greater mechanical stability” and “the smaller width at the portion of the fin structure 104 underneath the gate structure has a reduced width so as to provide better device performance” (Fung ¶ 0031; see also Fung ¶ 0014-0015, 0043, 0046).
Regarding Claim 34, Fung does not disclose wherein a bottom surface of the first region of the first segment of the semiconductor fin structure and a bottom surface of the second region of the first segment of the semiconductor fin structure are substantially coplanar in the second cross-sectional side view.
Chang discloses wherein a bottom surface of the first region (Fig. 16 B a bottom surface of the middle portion of 230) of the first segment of the semiconductor fin structure and a bottom surface of the second region (Fig. 16B a bottom surface of the left or right portions of 230) of the first segment of the semiconductor fin structure are substantially coplanar (Fig. 16B a bottom surface of the middle portion of 230, a bottom portion of the left portion of 230, and a bottom surface of the right portion of 230 are substantially coplanar) in the second cross-sectional side view (Fig. 16B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Fung to have wherein a bottom surface of the first region of the first segment of the semiconductor fin structure and a bottom surface of the second region of the first segment of the semiconductor fin structure are substantially coplanar in the second cross-sectional side view, as taught by Chang, in order to “protect…the metal gate stack” (Chang, col. 12 lines 21-23), thereby improving the reliability of the device.
Regarding Claim 35, Fung does not disclose further comprising a source/drain disposed over the second segment of the active region in the second cross-sectional side view, and an interlayer dielectric (ILD) disposed over the source/drain in the second cross-sectional side view, wherein a side surface of the first segment of the active region extends to the source/drain but not to the ILD in the second cross-sectional side view, and wherein a side surface of the gate spacer extends to both the source/drain and the ILD in the second cross-sectional side view.
Chang discloses further comprising a source/drain (250; Fig. 16B; col. 4 lines 10-11 “source/drain (S/D) features 250”) disposed over (Fig. 16B; col. 4 lines 10-11 “source/drain (S/D) features 250 in source/drain regions 252”) the second segment (252) of the active region in the second cross-sectional side view (Fig. 16B), and an interlayer dielectric (ILD) (260; Fig. 16B; col. 4 lines 38-39 “interlayer dielectric (ILD) layer 260”) disposed over the source/drain (Fig. 16B) in the second cross-sectional side view (Fig. 16B), wherein a side surface of the first segment (Fig. 16B a side surface of 242) of the active region extends to the source/drain (Fig. 16B side surface of 242 contacts source/drain 250) but not to the ILD (Fig. 16B side surface of 242 does not contact ILD 260) in the second cross-sectional side view (Fig. 16B), and wherein a side surface of the gate spacer (Fig. 16B a side surface of gate spacer 245) extends to both the source/drain and the ILD (Fig. 16B a side surface of gate spacer 245 contacts both source/drain 250 and ILD 260) in the second cross-sectional side view (Fig. 16B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Fung to have further comprising a source/drain disposed over the second segment of the active region in the second cross-sectional side view, and an interlayer dielectric (ILD) disposed over the source/drain in the second cross-sectional side view, wherein a side surface of the first segment of the active region extends to the source/drain but not to the ILD in the second cross-sectional side view, and wherein a side surface of the gate spacer extends to both the source/drain and the ILD in the second cross-sectional side view, as taught by Chang, in order to “protect…the metal gate stack” (Chang, col. 12 lines 21-23), thereby improving the reliability of the device.
Allowable Subject Matter
Claim 36 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 36, the prior art does not teach or render obvious wherein the ILD, the gate spacer, and the metal-containing gate electrode structure have co-planar upper surfaces in the second cross-sectional side view. Therefore, the combination of the features of Claims 1, 35, and 36 is considered allowable.
Response to Arguments
In their amendment and response filed 6/10/2026, the Applicant states (page 9) “Claims 1-3, 5, 17-19, and 22 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Fung et al. ("Fung"), US 2018/0315837.”
In the Final Rejection dated 4/10/26, independent Claims 1 and 17 were rejected under 35 U.S.C. 103 as being unpatentable over Fung et al. (“Fung”), US 2018/0315837, in view of Chang et al. (“Chang”), US 9,520,482 (listed in the IDS filed 9/26/2023).
The Applicant states (page 9) that “not every element of amended claim 1 is taught by the cited art”.
As explained supra, every element of independent Claim 1 is taught by Fung in view of Chang.
The Applicant states (page 10) that “not every element of amended claim 17 is taught by the cited art”.
As explained supra, every element of independent Claim 17 is taught by Fung in view of Chang.
The Applicant states (page 11) that “not every element of amended claim 30 is taught by the cited art”.
As explained supra, every element of independent Claim 30 is taught by Fung in view of Chang.
Independent Claims 1, 17, and 30 are rejected for at least the reasons stated supra. Dependent Claims 2-7, 18-22, and 31-35 are rejected for at least the reasons stated supra. Dependent Claim 36 is objected to.
Conclusion
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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