Prosecution Insights
Last updated: August 17, 2026
Application No. 18/340,897

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Final Rejection §102§103§112
Filed
Jun 26, 2023
Examiner
HANUMASAGAR, SHAMITA S
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
74%
Grant Probability
Favorable
3-4
OA Rounds
1m
Est. Remaining
63%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
14 granted / 19 resolved
+5.7% vs TC avg
Minimal -10% lift
Without
With
+-10.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
24 currently pending
Career history
69
Total Applications
across all art units

Statute-Specific Performance

§103
52.2%
+12.2% vs TC avg
§102
27.1%
-12.9% vs TC avg
§112
20.7%
-19.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 19 resolved cases

Office Action

§102 §103 §112
Attorney Docket Number: 131119-US-PA Filing Date: 06/26/2023 Claimed Priority Date: none Inventors: Tseng et al. Examiner: Shamita S. Hanumasagar DETAILED ACTION This Office action responds to the amendment filed on 05/06/2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Amendment Status The amendment filed on 05/06/2026 in reply to the previous Office action mailed on 02/06/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-16 and 21-24. Initial Remarks For all instances of “Annotated Fig. 44”, please refer to the following image, which is an annotated and marked portion of figure 44 of published application US 2022/0199575 by inventor Karhade. No other changes have been made to the figure. PNG media_image1.png 288 416 media_image1.png Greyscale For all instances of “Annotated Fig. 24”, please refer to the following image, which is an annotated and marked portion of figure 24 of published application US 2025/0015002 by inventor Kurita. No other changes have been made to the figure. PNG media_image2.png 435 1057 media_image2.png Greyscale Claims The claims are objected to because of the following informalities: In line 4 of claim 11, “wherein the first solder portion protruded from the first underfill” should read “wherein the first solder portion is protruded from the first underfill” Appropriate correction is required. No new matter should be added. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 21-24 are rejected under 35 U.S.C. 112(b) for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Claim 21 recites the limitation “wherein an interface between the second conductive feature and the conductive pillar is offset from the top surface of the fist underfill”. Since “fist” is an existing word, it is unclear whether the limitation “the fist underfill” is a typographical error or whether the term “fist” is structurally intended to indicate a designation or type of underfill. Accordingly, this limitation in the claim is indefinite. Claims 22-24 depend from claim 21 and thus inherit the deficiencies identified supra. Claims 1 and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karhade (US 2022/0199575). Regarding claim 1, Karhade (see, e.g., figs. 1-2, 44, and Annotated Fig. 44) shows all aspects of the instant invention, including a device 150 comprising: first integrated circuit (IC) dies 130-1, 130-2 disposed side-by-side, one (e.g., 130-1) of the first IC dies comprising first die connectors 134 and second die connectors 132, wherein a first pitch 202 of the first die connectors is less than a second pitch 198 of the second die connectors (see, e.g., par.0030/ll.32-34); a second IC die 110 overlapping and electrically coupled to the first IC dies (see, e.g., par.0030/ll.10-14), the second IC die comprising third die connectors 118, wherein a third pitch 202 of the third die connectors is substantially equal to the first pitch of the first die connectors; and first conductive features 106/177 interposed between and electrically coupled to the first die connectors and the third die connectors (see, e.g., par.0085/ll.22-27), one (e.g., leftmost 106/177) of the first conductive features 106/177 comprising a first conductive bump (106 closest to 130 and directly contacting 177) and a first conductive joint 177/(106 farthest from 130 and directly contacting 177), the first conductive joint comprising (see Annotated Fig. 44): a first solder portion First Solder Portion interfaced with one of the third die connectors 118; and a second solder portion Second Solder Portion formed between the first solder portion and the fist conductive bump, wherein a first sidewall of the first solder portion is curved, and a second sidewall of the second solder portion is connected to the first sidewall Regarding claim 7, Karhade (see, e.g., fig. 44) shows second conductive features 106/175 surrounding the first conductive features 106/177, each of the second conductive features comprising: a second conductive bump (106 directly contacting 175) comprising a first side facing a corresponding second die connector 132 and a second side opposite to the first side; conductive pillars 175 surrounding the second IC die 110, each of the conductive pillars being in direct contact with the second side of one of the second conductive bump Regarding claim 8, Karhade (see, e.g., fig. 44) shows an underfill 147 surrounding the first 134 and second 132 die connectors, the first conductive features 106/177, and the second conductive features 106/175, the underfill comprising a top surface facing the second IC die 110 and an inner sidewall connected to the top surface, wherein bottom portions (widest portions of 175 closest to 130) of the conductive pillars 175 are in contact with the top surface and the inner sidewall of the underfill. Claims 1, 3-4, and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karhade. Regarding claim 1, Karhade (see, e.g., figs. 1-2, 44, and Annotated Fig. 44) shows all aspects of the instant invention, including a device 150 comprising: first integrated circuit (IC) dies 130-1, 130-2 disposed side-by-side, one (e.g., 130-1) of the first IC dies comprising first die connectors 134 and second die connectors 132, wherein a first pitch 202 of the first die connectors is less than a second pitch 198 of the second die connectors (see, e.g., par.0030/ll.32-34); a second IC die 110 overlapping and electrically coupled to the first IC dies (see, e.g., par.0030/ll.10-14), the second IC die comprising third die connectors 118, wherein a third pitch 202 of the third die connectors is substantially equal to the first pitch of the first die connectors; and first conductive features 177/(106 farthest from 130 and directly contacting 177) interposed between and electrically coupled to the first die connectors and the third die connectors (see, e.g., par.0085/ll.22-27), one of the first conductive features comprising a first conductive bump 177 and a first conductive joint (106 farthest from 130 and directly contacting 177), the first conductive joint comprising (see Annotated Fig. 44): a first solder portion First Solder Portion interfaced with one of the third die connectors 118; and a second solder portion Second Solder Portion formed between the first solder portion and the fist conductive bump, wherein a first sidewall of the first solder portion is curved, and a second sidewall of the second solder portion is connected to the first sidewall Regarding claim 3, Karhade (see, e.g., fig. 44) shows that the one of the first conductive features 106/177 further comprises a second conductive joint (106 closest to 130 and directly contacting 177) physically coupled to the first conductive bump 177 and a corresponding first die connector 134, and the second conductive joint comprising a curved sidewall. Regarding claim 4, Karhade (see, e.g., fig. 44) shows that the first conductive joint (106 farthest from 130 and directly contacting 177) and the second conductive joint (106 closest to 130 and directly contacting 177) are solder joints. Regarding claim 7, Karhade (see, e.g., fig. 44) shows second conductive features 106/175 surrounding the first conductive features 106/177, each of the second conductive features comprising: a second conductive bump (106 directly contacting 175) comprising a first side facing a corresponding second die connector 132 and a second side opposite to the first side; conductive pillars 175 surrounding the second IC die 110, each of the conductive pillars being in direct contact with the second side of one of the second conductive bump Regarding claim 8, Karhade (see, e.g., fig. 44) shows an underfill 147 surrounding the first 134 and second 132 die connectors, the first conductive features 106/177, and the second conductive features 106/175, the underfill comprising a top surface facing the second IC die 110 and an inner sidewall connected to the top surface, wherein bottom portions (widest portions of 175 closest to 130) of the conductive pillars 175 are in contact with the top surface and the inner sidewall of the underfill. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 13-15, 21, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Kurita (WO 2023022179 A1), published 02/23/2023, in view of Chang (US 2021/0280519) and Tanaka (US 2024/0096809). However, all reference, figure, paragraph/line citations, etc., from Kurita are taken from the equivalent U.S. document (US 2025/0015002). Regarding claim 13, Kurita (see, e.g., figs. 3 and 24) shows most aspects of the instant invention, including a device 10 (40) comprising: first IC dies 41, 42 disposed side-by-side; a second IC die 431 stacked upon and electrically coupled to the first IC dies (see, e.g., par.0096/ll.13-15); conductive pillars 401 (see, e.g., figs. 3 and 6) disposed over the first IC dies; a first electrical connection 47 electrically connected (see, e.g., par.0116/ll.10-13) to the second IC die and one of the first IC dies, the first electrical connection comprising a first solder joint 474 physically connected to a die connector 436 of the second IC die; a second electrical connection 493/492D/492A electrically connected (see, e.g., par.0116/ll.16-19) to one of the conductive pillars and one of the first IC dies, an interface between the second electrical connection and the one of the conductive pillars being free of a solder material (see, e.g., pars.0153/ll.14-23 and 0165/ll.14-24), wherein a dimension of a first conductive bump 472A of the first electrical connection is less than that of a second conductive bump 492D/492A of the second electrical connection; and a first underfill 45 surrounding the first IC dies and comprising a surface 45b, wherein the one of the conductive pillars comprises a second portion protruded from the surface of the first underfill Although Kurita appears to teach (see, e.g., figs. 3 and 24) that a dimension of Kurita’s first conductive bump of the first electrical connection is less than that of a second conductive bump of the second electrical connection, Kurita fails to explicitly specify this. Chang, in the same field of endeavor and in a similar device to Kurita, shows a device PK wherein a dimension W2 of a first conductive feature/bump 111B of a first electrical connection 111B/116c is explicitly less than that W1 of a second conductive feature/bump 111A of a second electrical connection 111A/112’, wherein the second electrical connection electrically connects to one of conductive pillars 114, and wherein an interface between the second electrical connection and the one of the conductive pillars is free of solder material (see, e.g., Chang: figs. 6 and 15 and pars.0016/ll.12-17, 0019/ll.11-12, 0020/ll.8-13, and 0020/ll.17). Chang is evidence showing that one of ordinary skill in the art would appreciate that a dimension of a first conductive bump of a first electrical connection being explicitly less than that of a second conductive bump of a second electrical connection would be equivalent to a dimension of a first conductive bump of a first electrical connection being implicitly less than that of a second conductive bump of a second electrical connection, and that such differences would result in no unexpected changes in the performance of the device of Kurita. That is, the dimensions of the first and second conductive bumps of both Kurita and Chang would yield the predictable result of providing electrically conductive pathways capable of electrically connecting respective IC dies or IC dies and conductive pillars. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a dimension of a first conductive bump of a first electrical connection be explicitly less than that of a second conductive bump of a second electrical connection, as taught by Chang, or a dimension of a first conductive bump of a first electrical connection be implicitly less than that of a second conductive bump of a second electrical connection, as taught by Kurita, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing electrically conductive pathways capable of electrically connecting respective IC dies or IC dies and conductive pillars. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007). Furthermore, Kurita shows a first underfill comprising a surface and surrounding the first IC dies, wherein a first portion of the one of the conductive pillars is coplanar with the surface. Kurita (see, e.g., fig. 24) further shows that the one of the conductive pillars is surrounded by underfill. Kurita, however, despite teaching that the interface and conductive pillar are encapsulated by underfill, fails to show that the one of the conductive pillars comprises a first portion inserted into the surface of the first underfill and that the surface of the first underfill is offset from the interface between the second electrical connection in a height direction of the one of conductive pillars. Tanaka, in the same field of endeavor and in a similar device to Kurita, teaches a device 100 comprising multiple underfill layers and multiple conductive pillars (125 with portion in 117), wherein a conductive pillar comprises a first portion inserted into a first underfill 127 and a second portion protruded from the first underfill, wherein an interface between a second conductive feature 140-1 and a conductive pillar is offset from the top surface of the first underfill and is disposed between the top surface and a second die connector 122 (see, e.g., Tanaka: fig. 2B and pars.0022/ll.1-7 and 0030/ll.20-22). Tanaka is evidence showing that one of ordinary skill in the art would appreciate that a conductive pillar comprising a first portion inserted into the surface of a first underfill, wherein the surface of the first underfill is offset from the interface between a second electrical connection in a height direction of the conductive pillar, would be equivalent to a conductive pillar comprising a first portion inserted into another underfill, wherein the surface of the first underfill aligns with the interface between a second electrical connection in a height direction of the conductive pillar, and that such differences would result in no unexpected changes in the performance of the device of Kurita. That is, the underfill dispositions of both Kurita and Tanaka would yield the predictable result of providing a suitable encapsulation structure for a conductive pillar capable of establishing a conductive pathway between a die and other conductive features of an electrical device. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a conductive pillar comprising a first portion inserted into the surface of a first underfill, wherein the surface of the first underfill is offset from the interface between a second electrical connection in a height direction of the conductive pillar, as taught by Tanaka, or a conductive pillar comprising a first portion inserted into another underfill, wherein the surface of the first underfill aligns with the interface between a second electrical connection in a height direction of the conductive pillar, as taught by Kurita, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a suitable encapsulation structure for a conductive pillar capable of establishing a conductive pathway between a die and other conductive features of an electrical device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007). Regarding claim 21, Kurita (see, e.g., figs. 3 and 24) shows most aspects of the instant invention, including a device 10 (40) comprising: a first IC die 41 comprising a first die connector 417 and a second die connector 414 larger than the first die connector (see, e.g., fig. 24, wherein a horizontal length of the second die connector appears to be larger than a horizontal length of the first die connector); a second IC die 431 disposed over the first IC die and comprising a third die connector 436 electrically coupled (see, e.g., pars.0116/ll.10-12 and 0121/ll.2-4) to the first die connector of the first IC die; a conductive pillar 401 disposed over and electrically coupled to the second die connector (see, e.g., fig. 3 and pars.0116/ll.16-19 and 0117/ll.4-8); a first conductive feature 47 vertically interposed between the third die connector and the first die connector; a second conductive feature 416/493/492D/492A vertically interposed between the conductive pillar and the second die connector; a first underfill 45 surrounding the first and second die connectors, the first conductive feature, and the second conductive feature, wherein the conductive pillar is inserted into underfill; and a second underfill 105 surrounding the third die connector and disposed on a top surface 45b of the first underfill, wherein an interface between the second conductive feature and the conductive pillar is disposed between the top surface of the first underfill and the second die connector (wherein “between” is interpreted inclusively), and is aligned with the top surface of the first underfill Kurita shows most aspects of the instant invention. Kurita further appears to show that Kurita’s second die connector is larger than Kurita’s first die connector. Kurita, however, fails to explicitly specify this. Chang, in the same field of endeavor and in a similar device to Kurita, shows a device PK wherein a second die connector 111A is explicitly larger than a first die connector 111B, and wherein the second electrical connection electrically connects to one of conductive pillars 114 (see, e.g., Chang: figs. 6 and 15 and pars.0016/ll.12-17 and 0020/ll.8-13). Chang is evidence showing that one of ordinary skill in the art would appreciate that a second die connector being explicitly larger than a first die connector would be equivalent to a second die connector being implicitly larger than a first die connector, and that such differences would result in no unexpected changes in the performance of the device of Kurita. That is, the first and second die connector sizes of both Kurita and Chang would yield the predictable result of providing suitable electrically conductive structures capable of electrically connecting respective IC dies or IC dies and conductive pillars. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a second die connector being explicitly larger than a first die connector, as taught by Chang, or a second die connector being implicitly larger than a first die connector, as taught by Kurita, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitable electrically conductive structures capable of electrically connecting respective IC dies or IC dies and conductive pillars. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007). Furthermore, Kurita teaches most aspects of the instant invention, including appearing to show that an interface between the second conductive feature and the conductive pillar is between a top surface of the second underfill and the second die connector (wherein “between” is interpreted inclusively) and showing that the interface aligned with the top surface of the first underfill (see, e.g., Kurita: figs. 3 and 24). Kurita, however, despite teaching that the interface and conductive pillar are encapsulated by underfill, fails to explicitly specify that the conductive pillar is inserted into the first underfill and that an interface between Kurita’s second conductive feature and conductive pillar is offset from the top surface of the first underfill and is disposed between the top surface (of the first underfill) and the second die connector. Tanaka, in the same field of endeavor and in a similar device to Kurita/Chang, teaches a device 100 comprising multiple underfill layers and conductive pillars (125 with portion in 117), wherein a conductive pillar is inserted into a first underfill 127 and an interface between a second conductive feature 140-1 and a conductive pillar is offset from the top surface of the first underfill and is disposed between the top surface and a second die connector 122 (see, e.g., Tanaka: fig. 2B and pars.0022/ll.1-7 and 0030/ll.20-22). Tanaka is evidence showing that one of ordinary skill in the art would appreciate that a conductive pillar inserted into a first underfill, wherein an interface between a second conductive feature and the conductive pillar is offset from the top surface of the first underfill and is disposed between the top surface and a second die connector, would be equivalent to a conductive pillar inserted into another underfill, wherein an interface between a second conductive feature and a first underfill aligns with the top surface, and that such differences would result in no unexpected changes in the performance of the device of Kurita. That is, the underfill dispositions of both Kurita and Tanaka would yield the predictable result of providing a suitable encapsulation structure for a conductive pillar capable of establishing a conductive pathway between a die and other conductive features of an electrical device. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a conductive pillar inserted into a first underfill, wherein an interface between a second conductive feature and the conductive pillar is offset from the top surface of the first underfill and is disposed between the top surface and a second die connector, as taught by Tanaka, or a conductive pillar inserted into another underfill, wherein an interface between a second conductive feature and a first underfill aligns with the top surface, as taught by Kurita, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a suitable encapsulation structure for a conductive pillar capable of establishing a conductive pathway between a die and other conductive features of an electrical device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007). With regards to other language recited in claim 21, see the comments stated above in paragraph 9. Regarding claim 14, Kurita (see, e.g., figs. 3 and 24) shows that the first electrical connection 47 further comprises a second solder joint 473 physically connected to a die connector 417 of the one of the first IC dies 41, 42. Regarding claim 15, Kurita (see, e.g., fig. 24) shows a second underfill 105 surrounding the second IC die 431 and comprising a sidewall slanted (see, e.g., sidewall of 105 directly contacting and matching the contour of 474) between a sidewall of the second IC die and the surface 45b of the first underfill 45, wherein the second underfill is interfaced with a first underfill 45. Regarding claim 24, Kurita (see, e.g., figs. 3 and 24 and pars.0116/ll.16-19 and 0117/ll.4-8) shows that the second conductive feature 416/493/492D/492A further comprises a solder joint 493 connected to the second die connector 414 and surrounded by the first underfill 45. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Karhade in view of Chang. Regarding claim 5, Karhade shows most aspects of the instant invention (see paragraphs 12 and 16 above). Furthermore, Karhade (see, e.g., fig. 44) appears to show that a lateral dimension of the first die connectors 134 is less than a lateral dimension of the second die connectors 132. Karhade, however, fails to explicitly specify this. Chang, in the same field of endeavor and in a similar device to Karhade, shows a device PK wherein a lateral dimension W2 of first die connectors 111B is explicitly less than a lateral W1 dimension of second die connectors 111A (see, e.g., Chang: figs. 6 and 15 and par.0016/ll.12-17). Chang is evidence showing that one of ordinary skill in the art would appreciate that a lateral dimension of first die connectors being explicitly less than a lateral dimension of second die connectors would be equivalent to a lateral dimension of first die connectors being implicitly less than a lateral dimension of second die connectors, and that such differences would result in no unexpected changes in the performance of the device of Karhade. That is, the first and second die connectors of both Karhade and Chang would yield the predictable result of providing suitably-sized electrically conductive structures capable of electrically connecting multiple IC dies to various components of a device. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a lateral dimension of first die connectors be explicitly less than a lateral dimension of second die connectors, as taught by Chang, or a lateral dimension of first die connectors be implicitly less than a lateral dimension of second die connectors, as taught by Karhade, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitably-sized electrically conductive structures capable of electrically connecting multiple IC dies to various components of a device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007). Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Karhade in view of Chen (US 2022/0367306) and Hwang (US 2022/0375829). Regarding claim 9, Karhade shows most aspects of the instant invention (see paragraphs 12, 13, 16, and 19 above). Furthermore, Karhade (see, e.g., fig. 44) shows that each of the conductive pillars 175 comprises a first portion (portion of 175 closest to 130) physically connected to the second side of the one of the second conductive bump (106 directly contacting 175) and comprising a lateral dimension and a second portion (portion of 175 directly contacting first portion) connected to the first portion and comprising a lateral dimension different from the lateral dimension of the first portion. However, Karhade fails to explicitly specify in this embodiment that the first portion comprises a lateral dimension substantially equal to that of the second side of the one of the second conductive bump and that Karhade’s second portion comprises a lateral dimension greater than that of the first portion. Karhade, however, shows another embodiment in which each of conductive pillars 175 comprises a first portion (portion of 175 closest to 130-1) physically connected to the second side of a one of a second conductive bump (106 directly contacting 175) and comprising a lateral dimension substantially equal to that of the second side of the one of the second conductive bump, and a second portion (portion of 175 directly contacting first portion) connected to the first portion and comprising a lateral dimension greater than the lateral dimension of the first portion, wherein Karhade suggests the equivalent functionality of all of Karhade’s device embodiments (see, e.g., Karhade: fig. 43 and pars.0024 and 0085/ll.1-3). Furthermore, Chen, in the same field of endeavor and in a similar device to Karhade, shows a device 1 in which each of conductive pillars 32 surrounding an IC die 30 comprises a first portion (portion of 32 corresponding to part of 54H) physically connected to the second side of a one of a second conductive bump 56 and comprising a lateral dimension W1/32T substantially equal to that W1 of the second side of the one of the second conductive bump, and a second portion (portion of 32 directly contacting the first portion) connected to the first portion and comprising a lateral dimension (W2 and greater) greater than the lateral dimension of the first portion (see, e.g., Chen: figs. 1-1A and par.0036/ll.6-8). Additionally, Hwang, in the same field of endeavor and in a similar device to Karhade, also teaches a device 10 wherein each of conductive pillars 300 surrounding an IC die 200 comprises a first portion 320 physically connected to the second side of a one of a second conductive bump 635 and comprising a lateral dimension W22 substantially equal to that of the second side of the one of the second conductive bump, and a second portion 310 connected to the first portion and comprising a lateral dimension W11 greater than the lateral dimension of the first portion (see, e.g., Hwang: figs. 1A-1B and pars.0051/ll.6-12 and 0052/ll.9-10). Hwang further teaches that the structure Hwang depicts prevents misalignment between and properly couples conductive pillar portions, promoting increased structural stability (see, e.g., Hwang: pars.0052/ll.5-16). Karhade’s other embodiment, Chen, and Hwang are evidence showing that one of ordinary skill in the art would appreciate that having conductive pillars each comprising a first portion comprising a lateral dimension substantially equal to that of the second side of a one of a second conductive bump and a second portion comprising a lateral dimension greater than the lateral dimension of the first portion would be equivalent to each of the conductive pillars comprising a first portion comprising a lateral dimension and a second portion comprising a lateral dimension different from the lateral dimension of the first portion, and that such differences would result in no unexpected changes in the performance of the device of Karhade. That is, the first and second pillar portion lateral dimensions of both Karhade and Karhade, Chen, or Hwang would yield the predictable result of providing suitably-shaped conductive pillars capable of electrically connecting various components of a device. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either conductive pillars each comprising a first portion comprising a lateral dimension substantially equal to that of the second side of a one of a second conductive bump and a second portion comprising a lateral dimension greater than the lateral dimension of the first portion, as taught by Karhade’s other embodiment, Chen, and Hwang, or conductive pillars each comprising a first portion comprising a lateral dimension and a second portion comprising a lateral dimension different from the lateral dimension of the first portion, as taught by Karhade, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitably-shaped conductive pillars capable of electrically connecting various components of a device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007). Furthermore, Hwang is evidence that at the time of filing the invention one of ordinary skill in the art would find particular incentive to have in Karhade’s device conductive pillars each comprising a first portion comprising a lateral dimension substantially equal to that of the second side of a one of a second conductive bump and a second portion comprising a lateral dimension greater than the lateral dimension of the first portion, as taught by Hwang, so as to prevent misalignment between and to properly couple Karhade’s conductive pillar portions, thereby promoting increased structural stability in the device. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kurita/Chang/Tanaka in view of Tsai (US 2020/0091077) and St. Amand (US 8,633,598). Regarding claim 16, Kurita/Chang/Tanaka shows most aspects of the instant invention (see paragraphs 23-29 above). Kurita (see, e.g. figs. 3 and 24) further shows that the first solder joint 474 comprises a curved sidewall connected to the die connector 436 of the second IC die 431. Kurita, however, fails to explicitly specify that the first solder joint also comprises a substantially vertical sidewall connected to the curved sidewall. However, it is noted that the specification fails to provide teachings about the criticality of having a substantially vertical sidewall connected to a curved sidewall, as claimed in the instant application. Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the sidewall shape disclosed by Kurita/Chang/Tanaka as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, and the particular sidewall shape claimed by applicant is nothing more than one of numerous sidewall shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation as a matter of choice or based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976). Furthermore, the claimed sidewall shape is known in the art: Tsai and St. Amand, in the same field of endeavor, teach that a solder joint shape can comprise a substantially vertical sidewall connected to a curved sidewall (see, e.g., Tsai: fig. 1N and St. Amand: fig. 8). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the shape of a substantially vertical sidewall connected to a curved sidewall as claimed in the structure of Kurita/Chang/Tanaka, because a substantially vertical sidewall connected to a curved sidewall is known in the semiconductor art for its use in solder joint interconnects, as suggested by Tsai and St. Amand, and implementing a known structure shape for its conventional use/purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007). Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Kurita/Chang/Tanaka in view of Karhade. Regarding claim 22, Kurita/Chang/Tanaka shows most aspects of the instant invention (see paragraphs 30-37 above). Kurita (see, e.g., figs. 3, 24, and Annotated Fig. 24) further shows that the first conductive feature 47 comprises a first solder joint 474 connected to the third die connector 436, the first solder joint comprising a first portion First Solder Portion surrounded by the second underfill 105 and a second solder portion Second Solder Portion connected to the first portion, wherein the first portion is laterally convex toward the second underfill, and a second solder joint 473 connected to the first die connector 417. Kurita, however, fails to explicitly specify that the first solder joint comprises a second portion surrounded by the first underfill. Karhade, in the same field of endeavor, shows a plurality of device embodiments, including a device embodiment wherein a first solder joint 106 comprises a first portion 106A surrounded by a second dielectric (e.g., underfill) 104 and a second portion 106B and surrounded by a first underfill 147, wherein the first portion is laterally convex toward the second underfill (see, e.g., Karhade: fig. 34 and pars.0028/ll.11-14, 0029/ll.7-10, and 0075/ll.15-20). Karhade also shows additional embodiments wherein a first solder joint 106 only comprises a first portion surrounded by either a second underfill 144 or 147 (see, e.g., Karhade: figs. 22 and 43-44), wherein Karhade suggests the equivalent functionality of all of Karhade’s device embodiments (see, e.g., Karhade: par.0024). Karhade is evidence showing that one of ordinary skill in the art would appreciate that a first solder joint further comprising a second portion connected to a first portion and surrounded by a first underfill would be equivalent to a first solder joint only comprising a first portion and surrounded by a second underfill, and that such differences would result in no unexpected changes in the performance of the device of Kurita/Chang/Tanaka. That is, the conductive pass-through contacts of both Kurita/Chang/Tanaka and Karhade would yield the predictable result of providing an underfill-encapsulated and reinforced solder structure capable of electrically connecting various conductive components of a device. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a first solder joint further comprising a second portion connected to a first portion and surrounded by a first underfill, as taught by Karhade, or a first solder joint only comprising a first portion surrounded by a second underfill, as taught by both Karhade and Kurita, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing an underfill-encapsulated and reinforced solder structure capable of electrically connecting various conductive components of a device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007). Allowable Subject Matter Claims 2, 6, 10-12, and 23 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s amendments to the specification and drawings as filed on 05/06/2026 have overcome the objections to the drawings put forth in the previous Office action mailed on 02/06/2026. Accordingly, the objections to the drawings put forth in the previous Office action are hereby withdrawn. Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection. Conclusion Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action. Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000. /Shamita S. Hanumasagar/Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
Read full office action

Prosecution Timeline

Jun 26, 2023
Application Filed
Feb 06, 2026
Non-Final Rejection mailed — §102, §103, §112
May 06, 2026
Response Filed
Jul 20, 2026
Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
74%
Grant Probability
63%
With Interview (-10.3%)
3y 3m (~1m remaining)
Median Time to Grant
Moderate
PTA Risk
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