DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The present amendment, filed on or after 5/8/2026, has been entered. The Applicant has amended claim 1, canceled claim 2 and added claim 7 as a new claim. Claims 5-6 were previously withdrawn due to a restriction requirement. Accordingly, claims 1, 3-4, and 7 remain pending in the application.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in Japanese Patent Application No. JP2002-107241, filed on 7/1/2022.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/13/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 7 is objected to because of the following informalities: On line 2 of claim 7, “in the laser processing step of the laser beam is applied” should be changed to “in the laser processing step”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Shigematsu (JP 2015153770 A) in view of Kobayashi (US 2003/0045031 A1).
Regarding claim 1, Shigematsu teaches a device wafer processing method (Figs. 8-9, [0039]-[0050]) of dividing a device wafer (semiconductor wafer 2, Fig. 1, [0017]) having a plurality of devices (devices 23, Fig. 1, [0017]) formed on a face side (front side 21a, Fig. 1, [0018]) thereof by a functional layer (functional layer 21, Fig. 1, [0017]) laminated on a substrate (substrate 20, Fig. 1, [0017]), along a plurality of intersecting streets (dividing lines 22, Fig. 1, [0017]) that demarcate the devices (devices 23, Fig. 1), the processing method (Figs. 8-9, [0039]-[0050]) comprising:
a holding step (Fig. 8a, [0039]) of holding the face side of the device wafer (semiconductor wafer 2, Fig. 8: functional layer 21 is towards the first chuck table 21a, [[0036]) by a holding table (the first chuck-table 64a, Figs. 8a-b, [0023]), wherein a reverse side (back surface 20b, Figs. 8a-c, [0035]) of the device wafer (semiconductor wafer 2, Figs. 8a-c) is without a protective film (see Figs. 8a-c: back surface 20b is directly exposed without a protective layer);
a cutting step (Figs. 8a-c, [0040]-[0046]) of cutting the device wafer (semiconductor wafer 2, Figs. 8a-c) by a cutting blade (blade 833, Figs. 8a-b, [0040]) from a reverse side (back face 20b, Figs. 8a-c) of the device wafer (semiconductor wafer 2, Figs. 8a-c) along the streets (dividing lines 22, Fig. 8c, [0042]) and forming cutting grooves (cut groove 210, Fig. 8c, [0040]) that do not reach the functional layer (functional layer 21, Fig. 8c), after the holding step (Fig. 8a, [0039]) is carried out; and
a laser processing step (Figs. 9a-c, [0047]-[0049]) of applying a laser beam (laser beam LB, Figs. 9a-c, [0047]-[0049]) having a wavelength absorbable ([0047]: “… pulsed laser beams having wavelengths absorbable by the substrate 20 and the functional layer 21 from the focusing means 94.”) by the device wafer (semiconductor wafer 2 comprising substrate 20 and the functional layer 21, Figs. 9a-c ) to the device wafer (semiconductor wafer 2, Figs. 9a-c) from the reverse side (back face 20b, Figs. 9a-c) of the device wafer (semiconductor wafer 2, Figs. 9a-c) along the cutting grooves (cut groove 210, Figs. 9a-c, [0047]) and dividing the device wafer (semiconductor wafer 2, Figs. 9c) into individual devices (devices 23, Fig. 9c: the laser cut (dividing line 201, [0049]) goes through the whole semiconductor wafer 2 at the dividing lines 22, thereby separating individual devices), after the cutting step is carried out (Figs. 8a-c, [0040]-[0046]),
wherein the laser processing step (Figs. 9a-c, [0047]-[0049]) is carried out in a state in which the device wafer (semiconductor wafer 2, Figs. 8-9) is continuously held on the holding table (first chuck table 64a, Figs. 8-9, [0046]) without being unloaded from the holding table (first chuck table 64a, Figs. 8-9, [0046]: “first chuck table 64a holding the semiconductor wafer 2 on which the first cut groove forming step has been carried out to the laser processing region”, therefore the device wafer is not removed from the holding table (chuck table 64a) during and between the cutting step and laser processing step), after the cutting step (Figs. 8a-c, [0040]-[0046]) is carried out.
Shigematsu, however, does not teach that
in the laser processing step, a liquid layer is formed on the reverse side of the device wafer, and the laser beam is applied to the device wafer through the liquid layer.
Kobayashi, on the other hand, teaches a device wafer processing method (dicing method, Figs 1a-c, [0030]) to divide a wafer (comprising substrate 20 and plurality of semiconductor devices 10, Figs 1a-c, [0030]) into individual devices (Fig. 1c), wherein the method comprises a cutting step (Fig. 1a, [0031]: dicing the device with a disc-like blade 40 from the reverse side.) for cutting the substrate (substrate 20, Fig. 1a: substrate 20 is exposed and does not have a protective layer in the reverse (cutting) side) of the wafer from the reverse side without reaching the semiconductor device layer (semiconductor devices 10 and protective layer 90, Fig. 1a, [0035]), and laser processing step (Fig. 1b, [0031]) for cutting through the rest of the wafer and dividing the wafer into individual devices (Figs. 1b-c). Kobayashi further discloses that
in the laser processing step (Figs. 1b-c and 3), a liquid layer (water accumulation or pool 65, and stream of water 60 delivered onto the cutting surface, Figs. 1b-c, 3, and 5, [0038]) is formed on the reverse side (substrate 20, Fig. 5) of the device wafer (comprising substrate 20 and plurality of semiconductor devices 10, Figs 1a-c), and the laser beam (laser light 70, Figs. 3-5, [0033]) is applied to the device wafer (comprising substrate 20 and plurality of semiconductor devices 10, Figs 1a-c) through the liquid layer (stream of water 60, Fig. 5).
Kobayashi further discloses that delivering the laser beam through a water stream limits the laser light spread to the region within a cross section of the stream of water, so that the power of laser light can be reduced, and the cut substrate can be prevented from being scattered ([0009]). Thus, the possibility in which a burn, a burr and a fracture layer in machining are produced on a cut face, i.e., a diced face, can be reduced ([0009]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the method of Shigematsu to include a water stream for delivering the laser beam during the laser processing step as taught by Kobayashi to reduce the possibility of damaging the wafer during cutting and to improve the cutting quality.
Regarding claim 7, Shigematsu in view of Kobayashi teaches the device wafer processing method according to claim 1, wherein
Shigematsu further teaches that in the laser processing step (Figs. 9a-c, [0047]-[0049]) (laser beam LB, Figs. 9a-c, [0047]-[0049]) is applied to bottoms of the cutting grooves (bottom of the cut groove 210, Fig. 9c) to remove a part of the bottoms of the cutting grooves (bottom of the cut groove 210 is removed by laser ablation to form laser processed groove 220, Fig. 9c) and part of the functional layer (functional layer 21, Fig. 9C: a part of the functional layer 21 is also removed to form laser processed groove 220) to divide the device wafer (semiconductor wafer 2, Fig. 1) into the plurality of devices (devices 23, Fig. 1).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Shigematsu (JP 2015153770 A) in view of Kobayashi (US 2003/0045031A1) as applied to claims 1 and 7 above, and further in view of Matsumoto (JP 2019096768 A).
Regarding claim 3, Shigematsu in view of Kobayashi teaches the device wafer processing method according to claim 1, wherein
Shigematsu teaches that the method further comprises
a tape affixing step (Fig. 2, [0018]) of affixing a tape (protective tape/member 3, Fig. 2, [0018] and [0037])) to the face side (front side 21a, Fig. 2, [0018]) of the device wafer (semiconductor wafer 2, Fig. 2, [0018]), wherein,
in the holding step (Fig. 8a, [0039]), the face side (front side 21a, Fig. 8a) of the device wafer (semiconductor wafer 2, Fig. 8a) is held via the tape (protective tape/member 3, Fig. 8a, [0035]: the semiconductor wafer is held by suction via protective tape/member 3).
neither Shigematsu nor Kobayashi, however, teaches that the method further comprises
a water-soluble resin coating step of coating the face side of the device wafer with water-soluble resin before the holding step is carried out; and
a tape affixing step of affixing a tape to the face side of the device wafer after the water-soluble resin coating step is carried out.
Matsumoto, on the other hand, teaches a method for preventing adhesive residue from being generated on the surface to be held of a plate-like object, such as a semiconductor wafer, after processing (Abstact and [0002]), wherein the method comprises
a water-soluble resin coating step (Fig. 2, [0012]) of coating the face side (upper surface Wa, Fig. 2, [0013]) of the device wafer (plate-like object W including devices D, Fig. 2, [0013]) with water-soluble resin (water-soluble surfactant, Fig. 2, [0016]) before the holding step is carried out (Fig. 5, [0024]); and
a tape affixing step (sheet disposing step, Fig. 4, [0021]) of affixing a tape (long sheet K, Fig. 4, [0023]) to the face side (upper surface Wa, Fig. 4, [0023]) of the device wafer (plate-like object W including devices D, Fig. 4) after the water-soluble resin coating step (Fig. 2, [0012]) is carried out.
Matsumoto further discloses that including a water-soluble resin (water-soluble surfactant, Fig. 7) between the fixing tape (long sheet K, Fig. 7) and front side (upper surface Wa, Fig. 7) of the device wafer (plate-like object W including devices D, Fig. 7) prevents adhesive glue residues remain on the surface of the wafer ([0010]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the method of Shigematsu in view of Kobayashi according to the teachings of Matsumoto to include steps for forming a water-soluble resin on the face side of the device wafer before the holding step to prevent the formation of glue residues on the face side of the device wafer. Thus, the combination of Shigematsu, Kobayashi, and Matsumoto meets all the limitations of claim 3 such that the method further comprises:
a water-soluble resin coating step of coating the face side of the device wafer with water-soluble resin before the holding step is carried out; and
a tape affixing step of affixing a tape to the face side of the device wafer after the water-soluble resin coating step is carried out, wherein,
in the holding step, the face side of the device wafer is held via the tape.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Shigematsu (JP 2015153770 A) in views of Kobayashi (US 2003/0045031A1) and Matsumoto (JP 2019096768 A) as applied to claim 3 above, and further in view of Yoshitama (JP 2019212839 A).
Regarding claim 4, Shigematsu in views of Kobayashi and Matsumoto teaches the device wafer processing method according to claim 3, wherein
Shigematsu further teaches that the method further comprises:
a transferring step (wafer supporting step, Fig. 11, [0057]-[0058]) of affixing a reverse side tape (dicing tape 97, Fig. 11, [0057]-[0058]) to the reverse side (back surface 20b, Fig. 11, [0057]) of the device wafer (semiconductor wafer 2, Fig. 11) and removing the tape (protective tape/member 3, Fig. 11c, [0057]: “the protective member 3 affixed to the front surface of the functional layer 21 constituting the semiconductor wafer 2 is peeled off.”) from the face side (front side 21a, Fig. 11c) of the device wafer (semiconductor wafer 2, Fig. 11c), after the reverse side cleaning step is carried out.
Shigematsu and Kobayashi, however, are silent on that the method further comprises
a reverse side cleaning step of cleaning the reverse side of the device wafer after the laser processing step is carried out; and
a face side cleaning step of cleaning the face side of the device wafer and removing the water-soluble resin, after the transferring step is carried out.
Matsumoto, on the other hand, teaches a method for preventing adhesive residue from being generated on the surface to be held of a plate-like object, such as a semiconductor wafer, after processing (Abstact and [0002]), wherein the method comprises
a face side cleaning step (washing step, Fig. 9, [0038]) of cleaning the face side (upper surface Wa, Fig. 9, [0039]) of the device wafer (the plate-shaped body W, Fig. 9, [0039]) and removing the water-soluble resin ([0038]: ”The spin coater 3 used in the forming step can play a role of cleaning and removing the residue of the glue layer M from the upper surface Wa of the plate-shaped body W, in addition to a role of forming the glue layer M made of the water-soluble surfactant on the upper surface Wa of the plate-shaped body W. The remainder of the glue layer M may be cleaned and removed from the plate-shaped workpiece W by a cleaning device other than the spin coater 3.”), after the transferring step (removal step. [0036], Figs. 7-8)) is carried out.
Matsumoto further discloses that washing step removes the water-soluble resin (water-soluble surfactant, Fig. 7) and adhesive glue residues remaining on the surface of the wafer ([0038]-[0039]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the method of Shigematsu in views of Kobayashi and Matsumoto according to the teachings of Matsumoto to include steps for cleaning the face side of the device wafer after the transferring step, to remove any resin and glue residues form the surface. Thus, the combination of Shigematsu, Kobayashi, and Matsumoto meets the limitations that the method further comprises:
a transferring step of affixing a reverse side tape to the reverse side of the device wafer and removing the tape from the face side of the device wafer, after the reverse side cleaning step is carried out; and
a face side cleaning step of cleaning the face side of the device wafer and removing the water-soluble resin, after the transferring step is carried out.
Shigematsu, Kobayashi and Matsumoto, however, do not teach that the method further comprises
a reverse side cleaning step of cleaning the reverse side of the device wafer after the laser processing step is carried out.
Yoshitama, on the other hand, teaches a method for wafer processing (Overview) for separating individual devices (devices 5, Fig. 1, [0016]) on a device wafer (wafer 1, Fig. 1, [0016]), wherein the method comprises mounting the device wafer (wafer 1, Figs. 2-3, [0018]-[0019]) back face up on a platform (Fig. 3), performing a cutting process with blades from the back side of the device wafer (Fig. 3, [0020]-[0021]) and separating the individual devices with a laser processing step (functional layer cutting step ST4, Figs. 8-9, [0035]-[0036]). Yoshitama discloses that the method further comprises
a reverse side cleaning step (washing step ST5, Fig. 10, [0038]) of cleaning the reverse side (reverse side 7, Fig. 10, [0022]) of the device wafer (wafer 1, Fig. 10) after the laser processing step (functional layer cutting step ST4, Figs. 8-9, [0035]-[0036]) is carried out.
Yoshitama further discloses that the washing step ST5 is a step of supplying washing water 57 to the wafer 1 after the functional layer slicing step ST4 to remove the debris 310 generated by the application of the laser beams 51 and adhering to the inner surfaces of the cut grooves 300 (Fig. 9, [0038]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include a reverse side cleaning process in the method of Shigematsu in views of Kobayashi and Matsumoto, as taught by Yoshitama, to be able to remove the debris remaining in the grooves after laser processing.
Thus, the combination of Shigematsu, Kobayashi, Matsumoto, and Yoshitama meets all the limitations of claim 4.
Response to Arguments
It has been acknowledged that the applicant has amended claim 1, canceled claim 2 and added claim 7 as a new claim per response dated on 5/8/2026.
Applicant's arguments with respect to claims have been fully considered. The Examiner agrees with the Applicant on that the amended claim 1, now also disclosing the new limitations that “a reverse side of the device wafer is without a protective film” and “in the laser processing step, a liquid layer is formed on the reverse side of the device wafer, and the laser beam is applied to the device wafer through the liquid layer” (the limitations of canceled claim 2), overcame the rejections made previously based on the prior art Shigematsu (JP 2015153770 A). The examiner also agrees with the Applicant that the combination of Shigematsu and Hadano (US 2019/0232431 A1), which was used to reject claim 2, now also fails to teach the amended claim 1, as Hadano’s method includes a protective layer on the side of the wafer where the laser beam is applied.
However, amended claim 1 are now rejected under new grounds based on the combination of Shigematsu and a new prior-art, Kobayashi (US 2003/0045031A1), in the current office action. Rejections are also made on all remaining claims, including new claim 7, based on Shigematsu and Kobayashi or their combination with the prior-art from the initial office action.
For the purpose of compact prosecution, the Examiner notes that further describing how the laser beam is applied through the liquid layer and/or how the liquid layer is formed on the wafer might make independent claim 1 to overcome the current rejections.
The Examiner is available for an interview at Applicant' s convenience if the Applicant would like to discuss the application.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hadano (US 2019/0122907 A1) teaches a laser processing, method wherein the laser beam applied on to the wafer through a liquid layer formed on the wafer, which is relevant to claim 1.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights