DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-10 and 16-25 are pending.
Claims 11-15 are cancelled.
Claims 21-25 are new.
Election/Restrictions
Applicant’s election without traverse of Group I, corresponding to claims 1-10 and 16-20, and newly added claims 21-25, in the reply filed on 12/29/2025 is acknowledged. Group II, corresponding to claims 11-15 is cancelled from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/29/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/27/2023 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
SRAM DEVICE HAVING CHANNEL LAYERS WITH VARYING DIMENSIONS AND MANUFACTURING METHODS THEREOF
Claim Objections
Claims 1, 6-10, 17, 18, and 21 are objected to because of the following informalities:
Regarding claims 1 and 21, differentiation should be made between the source/drain region (180) corresponding to the bottom-tier transistors and the source/drain region (185) corresponding to the top-tier transistors, see paragraph 0020.
Claim 1, line 4 should read: “the first and second bottom-tier transistors sharing a first same source/drain region”
Claim 1, line 10 should read: “the first and second top-tier transistors sharing a second same source/drain region”
Claim 21, line 6 should read: “the first and second bottom-tier transistors sharing a first same source/drain region”
Claim 21, line 12 should read: “the first and second top-tier transistors sharing a second same source/drain region”
Regarding claims 6-10, 17, and 18, the examiner recommends that the term “longest” as used in the phrases “first longest side,” “second longest side,” “third longest side,” and “fourth longest side” be removed for clarity. These terms appear to refer to S1, S2, S3, and S4 of at least Fig. 2A, discussed in at least paragraph 0029 of the specification, which refer to the overlap of the channel layer and the gate electrode in a width direction. The examiner believes that referring to these sides in the claims as “longest side(s)” provides confusion, as this portion of the channel layer is not the “longest” in comparison to other portions of the channel, and additionally does not refer to the entire side of the channel layer. Rather, referring to these sides as the “first side,” “second side,” “third side,” and “fourth side” along with the already-included claim limitation “side extending along a first direction perpendicular to the lengthwise to the direction of the gate structure” would provide more clarity for claim interpretation. This change should be made to all appropriate claims and portions in the specification for term consistency.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (2021/0020643; herein known as Yang) in view of Chanemougame et al. (2022/0102362; herein known as Chanemougame).
Regarding claim 1, Yang teaches (annotated Fig. 4A below) forming a first top-tier transistor (222, [0039]) over the first bottom-tier transistor, the first top-tier transistor comprising a first channel layer (402, [0040]) and a first gate structure (Fig. 3C, 340, [0038]) around the first channel layer; and forming a second top-tier transistor (206, [0039]) over the second bottom-tier transistor, the second top- tier transistor comprising a second channel layer (408, [0040]) and a second gate structure (Fig. 3C, 340, [0038]) around the second channel layer, the first and second top-tier transistors sharing a same source/drain region (not pictured, [0031]), wherein from a top view, a first dimension (Annotated Fig. 4a below, W1) of the first channel layer (402, [0040]) in a lengthwise direction (x) of the first gate structure is different than a second dimension (W2) of the second channel layer (408, [0040]) in the lengthwise direction of the first gate structure ([0040]).
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Yang does not explicitly teach forming a first bottom-tier transistor; forming a second bottom-tier transistor, the first and second bottom-tier transistors sharing a same source/drain region.
Chanemougame teaches (Fig. 4B) forming a first bottom-tier transistor (PG1, [0050]); forming a second bottom-tier transistor (PD1, [0050]) the first and second bottom-tier transistor sharing a same source/drain region ([0050]).
Because Yang and Chanemougame are both directed toward GAA SRAM devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yang and Chanemougame to include forming a first bottom-tier transistor; forming a second bottom-tier transistor, the first and second bottom-tier transistors sharing a same source/drain region, in order to provide better power, performance and area (PPA) scaling (Chanemougame, [0004]).
Regarding claim 2, Yang in view of Chanemougame teaches the method of claim 1, wherein the first and second bottom-tier transistors (Chanemougame, Fig. 4B, PG1, PD1) and the first and second top-tier transistors (Yang, Fig. 4A, 222, 206, [0039]) are of a static random access memory cell (Yang, [0011]).
Regarding claim 3, Yang in view of Chanemougame teaches (Yang, Fig. 4A), the method of claim 1, wherein the first top-tier transistor (222, [0040]) is a pull-down transistor ([0040]), and the second top-tier transistor (206, [0040]) is a pass-gate transistor ([0040]).
Claims 4-6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Chanemougame as applied to claim 1 above, and further in view of Liaw (US PGPub 2020/0135740; herein known as Liaw).
Regarding claim 4, Yang in view of Chanemougame teaches the method of claim 1 but does not explicitly teach wherein the second dimension of the second channel layer of the second top-tier transistor is greater than the first dimension of the first channel layer of the first top-tier transistor.
Liaw teaches (Fig. 2A) wherein the second dimension (W1, [0027]) of the second channel layer (202, [0027]) of the second top-tier transistor (PG-1, [0027]) is greater than the first dimension (W3, [0027]) of the first channel layer (206, [0027]) of the first top-tier transistor (PU-1, [0027]).
Because Yang in view of Chanemougame and Liaw are both directed toward GAA SRAM devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yang in view of Chanemougame and of Liaw to include wherein the second dimension of the second channel layer of the second top-tier transistor is greater than the first dimension of the first channel layer of the first top-tier transistor, in order to avoid adopting write assist features in SRAM driving logic (Liaw, [0027]).
Regarding claim 5, Yang in view of Chanemougame teaches the method of claim 1, wherein the second dimension of the second channel layer of the second top-tier transistor is about 1.1 to about 2 times the first dimension of the first channel layer of the first top-tier transistor.
Liaw teaches (Fig. 2A) wherein the second dimension (W1, [0027]) of the second channel layer (202, [0027]) of the second top-tier transistor (PG-1, [0027]) is about 1.1 to about 2 times ([0027]) the first dimension (W3, [0027]) of the first channel layer (206, [0027]) of the first top-tier transistor (PU-1, [0027]).
Because Yang in view of Chanemougame and Liaw are both directed toward GAA SRAM devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yang in view of Chanemougame and of Liaw to include wherein the second dimension of the second channel layer of the second top-tier transistor is about 1.1 to about 2 times the first dimension of the first channel layer of the first top-tier transistor, in order to avoid adopting write assist features in SRAM driving logic (Liaw, [0027])
Regarding claim 6, Yang in view of Chanemougame teaches the method of claim 1, but does not explicitly teach wherein from the top view, the first channel layer of the first top-tier transistor has a first longest side extending along a first direction perpendicular to the lengthwise direction of the first gate structure, the second channel layer of the second top-tier transistor has a second longest side extending along the first direction, the first longest side is inward relative to the second longest side in the lengthwise direction of the first gate structure.
In short, the width of the second channel layer is greater than the width of the first channel layer, therefore the first and second channel layers must necessarily not be aligned on at least one side.
Liaw teaches (Fig. 2A) wherein the second dimension (W1, [0027]) of the second channel layer (202, [0027]) of the second top-tier transistor (PG-1, [0027]) is greater than the first dimension (W3, [0027]) of the first channel layer (206, [0027]) of the first top-tier transistor (PU-1, [0027]).
Because Yang in view of Chanemougame and Liaw are both directed toward GAA SRAM devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yang in view of Chanemougame and of Liaw to include wherein the width of the second channel layer is greater than the width of the first channel layer in order to avoid adopting write assist features in SRAM driving logic (Liaw, [0027]).
Yang in view of Chanemougame and Liaw teaches wherein the width of the second channel layer is greater than the width of the first channel layer, and therefore, must necessarily teach wherein from the top view, the first channel layer of the first top-tier transistor has a first longest side extending along a first direction perpendicular to the lengthwise direction of the first gate structure, the second channel layer of the second top-tier transistor has a second longest side extending along the first direction, the first longest side is inward relative to the second longest side in the lengthwise direction of the first gate structure.
Regarding claim 8, Yang in view of Chanemougame and Liaw teaches (Yang, Fig. 5B) the method of claim 6, wherein from the top view, the first channel layer of the first top-tier transistor (222) has a third longest side (S3) opposing the first longest side (S1), the second channel layer of the second top-tier transistor (206) has a fourth longest side (S4) opposing the second longest side (S2), the third longest side (S3) is aligned with the fourth longest side (S4).
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Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Chanemougame and Liaw as applied to claim 6 above, and further in view of Lee et al. (US PGPub 2017/0194330; herein known as Lee).
Regarding claim 7, Yang in view of Chanemougame and Liaw teaches the method of claim 6, wherein from the top view, the first channel layer of the first top-tier transistor has a third longest side opposing the first longest side, the second channel layer of the second top-tier transistor has a fourth longest side opposing the second longest side.
Yang in view of Chanemougame and Liaw teaches wherein one side of the channel layer of the first transistor and one side of the channel layer of the second transistor are aligned, perpendicular to the direction of the gate electrode.
Yang in view of Chanemougame and Liaw does not explicitly teach wherein the third longest side is inward relative to the fourth longest side in the lengthwise direction of the first gate structure.
Lee teaches wherein the third longest side (annotated Fig. 9 below, S3) is inward relative to the fourth longest side (Annotated Fig. 9 below, S4) in the lengthwise direction (D1) of the first gate structure (G2).
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Additionally, Lee teaches wherein width of the channel layers can be determined due to a number of factors, including transistor type, and wherein modifying the channel width can improve the performance of the SRAM cell and/or reduce an occupying area of the SRAM cell (Lee, [0049]).
Absent a teaching of criticality of the relative widths of the channel layers, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use simple substitution to substitute the channel width of Lee for the channel width of Yang in view of Chanemougame and Liaw for the known result of improving the performance of the SRAM cell and/or reduce an occupying area of the SRAM cell (Lee, [0049]). See MPEP 2143.I.B.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Chanemougame and Liaw as applied to claim 8 above, and further in view of Chou et al. (US PGPub 2023/0380130; herein known as Chou).
Regarding claim 9, Yang in view of Chanemougame and Liaw teaches the method of claim 8, but does not explicitly teach wherein the first top-tier transistor comprises a first source/drain region at a side of the first gate structure opposing to the second gate structure, the method further comprising: forming a source/drain contact over the first source/drain region; and forming a source/drain via over the source/drain contact, wherein from the top view, the first longest side is between the third longest side and the source/drain via.
Liaw further teaches (Fig. 2B) wherein the first top-tier transistor (206, [0025]) comprises a first source/drain region (250, [0029]) at a side of the first gate structure (230, [0029]) opposing to the second gate structure (230, [0029]), the method further comprising: forming a source/drain contact (270, [0029]) over the first source/drain region; and forming a source/drain via (Fig. 4, X) over the source/drain contact.
Because Yang in view of Chanemougame and Liaw are directed toward GAA SRAM devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Yang, Chanemougame, and Liaw in order to provide connection to source/drain regions, as is known in the art (Liaw, [0029]).
Yang in view of Chanemougame and Liaw does not explicitly teach wherein from the top view, the first longest side is between the third longest side and the source/drain via.
Chou teaches (annotated Fig. 6A below, [0055]) wherein from the top view, the first longest side (FLS) is between the third longest side (TLS) and the source/drain via (SDV).
Chou teaches wherein the alignment of the channel layers can be modified to change the distance between adjacent channel layers, and wherein the size of the source/drain contact located between the adjacent channel layers can be tuned dependent on the distance between adjacent channel layers in order to improve the performance of the SRAM device ([0055]).
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Absent a teaching of criticality in the claimed invention of wherein from the top view, the first longest side is between the third longest side and the source/drain via, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the alignment of the channel layers, taught by Chou, in the SRAM device of Yang in view of Chanemougame and Liaw, to include wherein from the top view, the first longest side is between the third longest side and the source/drain via to apply the known technique of source/drain contact size tuning in order to yield the predictable result of an SRAM device with improved device performance.
Regarding claim 10, Yang in view of Chanemougame and Liaw teaches the method of claim 8, but does not explicitly teach wherein the first top-tier transistor comprises a first source/drain region at a side of the first gate structure opposing the second gate structure, the method further comprising: forming a source/drain contact over the first source/drain region; and forming a source/drain via over the source/drain contact, wherein from the top view, the third longest side is between the first longest side and the source/drain via.
Liaw further teaches (Fig. 2B) wherein the first top-tier transistor (206, [0025]) comprises a first source/drain region (250, [0029]) at a side of the first gate structure (230, [0029]) opposing to the second gate structure (230, [0029]), the method further comprising: forming a source/drain contact (270, [0029]) over the first source/drain region; and forming a source/drain via (Fig. 4, X) over the source/drain contact.
Because Yang in view of Chanemougame and Liaw are directed toward GAA SRAM devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Yang, Chanemougame, and Liaw in order to provide connection to source/drain regions, as is known in the art (Liaw, [0029]).
Yang in view of Chanemougame and Liaw does not explicitly teach wherein from the top view, the third longest side is between the first longest side and the source/drain via.
Chou teaches (Annotated Fig. 6A below, [0055]) wherein from the top view, the third longest side (TLS) is between the first longest side (FLS) and the source/drain via (SDV).
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Chou teaches wherein the alignment of the channel layers can be modified to change the distance between adjacent channel layers, and wherein the size of the source/drain contact located between the adjacent channel layers can be tuned dependent on the distance between adjacent channel layers in order to improve the performance of the SRAM device ([0055]).
Absent a teaching of criticality in the claimed invention of wherein from the top view, the first longest side is between the third longest side and the source/drain via, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the alignment of the channel layers, taught by Chou, in the SRAM device of Yang in view of Chanemougame and Liaw, to include wherein from the top view, the third longest side is between the first longest side and the source/drain via to apply the known technique of source/drain contact size tuning in order to yield the predictable result of an SRAM device with improved device performance.
Claims 16, 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chanemougame in view of Liaw.
Regarding claim 16, Chanemougame teaches (annotated Fig. 4B below) a semiconductor structure, comprising: a first transistor (T1) of a static random access memory (SRAM) cell (INV1), the first transistor (T1) comprising: first semiconductor sheets (GAA structure, [0050]); and a first gate structure surrounding each of the first semiconductor sheets ([0050]); a second transistor (T2) of the SRAM cell over the first transistor; a third transistor (T3) of the SRAM cell laterally adjacent to the first transistor; and a fourth transistor (T4) of the SRAM cell over the third transistor, the fourth transistor comprising: second semiconductor sheets (GAA structure, [0050]); and a second gate structure surrounding each of the second semiconductor sheets ([0050]),
Chanemougame does not explicitly teach wherein from a top view, a first dimension of one of the first semiconductor sheets in a lengthwise direction of the first gate structure is less than a second dimension of one of the second semiconductor sheets in the lengthwise direction of the first gate structure.
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Liaw teaches (Fig. 2A) wherein from a top view, a first dimension (W3, [0027]) of one of the first semiconductor sheets (206, [0027]) in a lengthwise direction of the first gate structure is less than a second dimension (W1, [0027]) of one of the second semiconductor sheets (202, [0027]) in the lengthwise direction of the first gate structure.
Because Chanemougane and Liaw are both directed toward GAA SRAM devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chanemougame and of Liaw to include wherein the direction of the first gate structure is less than a second dimension of one of the second semiconductor sheets in the lengthwise direction of the first gate structure in order to avoid adopting write assist features in SRAM driving logic (Liaw, [0027]).
Regarding claim 17, Chanemougame in view of Liaw teaches the semiconductor structure of claim 16, wherein from the top view, the one of the first semiconductor sheets has a first longest side extending along a first direction perpendicular to the lengthwise direction of the first gate structure, the one of the second semiconductor sheets has a second longest side extending along the first direction, the first longest side is inward relative to the second longest side in the lengthwise direction of the first gate structure.
In short, the width of the second channel layer is greater than the width of the first channel layer, therefore the first and second channel layers must necessarily not be aligned on at least one side. Chanemougame in view of Liaw teaches (Liaw, Fig. 2A) wherein the second dimension (W1, [0027]) of the second channel layer (202, [0027]) of the second top-tier transistor (PG-1, [0027]) is greater than the first dimension (W3, [0027]) of the first channel layer (206, [0027]) of the first top-tier transistor (PU-1, [0027]), and therefore must necessarily teach wherein one of the first semiconductor sheets has a first longest side extending along a first direction perpendicular to the lengthwise direction of the first gate structure, the one of the second semiconductor sheets has a second longest side extending along the first direction, the first longest side is inward relative to the second longest side in the lengthwise direction of the first gate structure.
Regarding claim 19, Chanemougame in view of Liaw teaches (Chanemougame, Fig. 4B) the semiconductor structure of claim 16, wherein the first transistor (PD1, [0050]) is a pull-down transistor ([0050]).
Regarding claim 20, Chanemougame in view of Liaw teaches (Chanemougame, Fig. 4B) the semiconductor structure of claim 16, wherein the fourth transistor is a pass-gate transistor. Chanemougame teaches wherein the pass-gate is in the stack adjacent to the pull-down transistor ([0050]) and where the pass-gate can alternately be located in the second deck (i.e. the fourth transistor position), ([0006]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Chanemougame in view of Liaw as applied to claim 17 above, and further in view of Lee.
Regarding claim 18, Chanemougame in view of Liaw teaches the semiconductor structure of claim 17, wherein from the top view, the one of the first semiconductor sheets has a third longest side opposing the first longest side, the one of the second semiconductor sheets has a fourth longest side opposing the second longest side, the third longest side is inward relative to the fourth longest side in the lengthwise direction of the first gate structure.
Chanemougame in view of Liaw teaches wherein one side of the channel layer of the first transistor and one side of the channel layer of the second transistor are aligned, perpendicular to the direction of the gate electrode.
Chanemougame in view of Liaw does not explicitly teach wherein the third longest side is inward relative to the fourth longest side in the lengthwise direction of the first gate structure.
Lee teaches wherein the third longest side (annotated Fig. 9 below, S3) is inward relative to the fourth longest side (Annotated Fig. 9 below, S4) in the lengthwise direction (D1) of the first gate structure (G2).
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Additionally, Lee teaches wherein width of the channel layers can be determined due to a number of factors, including transistor type, and wherein modifying the channel width can improve the performance of the SRAM cell and/or reduce an occupying area of the SRAM cell (Lee, [0049]).
Absent a teaching of criticality of the relative widths of the channel layers, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use simple substitution to substitute the channel width of Lee for the channel width of Chanemougame in view of Liaw with the known result of improving the performance of the SRAM cell and/or reduce an occupying area of the SRAM cell (Lee, [0049]). See MPEP 2143.I.B.
Claims 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Chanemougame in view of Liaw.
Regarding claim 21, Chanemougame teaches (annotated Fig. 4B below, [0050]) a method, comprising: forming a first bottom-tier transistor (T1), the first bottom-tier transistor comprising a first channel layer and a first gate structure around the first channel layer; forming a second bottom-tier transistor (T3), the second bottom-tier transistor comprising a second channel layer and a second gate structure around the second channel layer, the first and second bottom-tier transistors sharing a same source/drain region, forming a first top-tier transistor (T2) over the first bottom-tier transistor; and forming a second top-tier transistor (T2) over the second bottom-tier transistor, the first and second top-tier transistors sharing a same source/drain region (SD2).
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Chanemougame does not explicitly teach wherein from a top view, a first dimension of the first channel layer in a lengthwise direction of the first gate structure is less than a second dimension of the second channel layer in the lengthwise direction of the first gate structure.
Liaw teaches (Fig. 2A) wherein the first dimension (W3, [0027]) of the first channel layer (206, [0027]) in a lengthwise direction of the first gate structure is less than the first dimension (W1, [0027]) of the first channel layer (202, [0027]) in the lengthwise direction of the first gate structure.
Because Chanemougame and Liaw are both directed toward GAA SRAM devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chanemougame and of Liaw to include teach wherein from a top view, a first dimension of the first channel layer in a lengthwise direction of the first gate structure is less than a second dimension of the second channel layer in the lengthwise direction of the first gate structure in order to avoid adopting write assist features in SRAM driving logic (Liaw, [0027]).
Regarding claim 22, Chanemougame in view of Liaw teaches (annotated Fig. 4B above) the method of claim 21, wherein the first bottom-tier transistor (T1) is a pull-down transistor (PD1, [0027]), the first top-tier transistor (T2) is a pull-up transistor (PU1, [0027]), and the second bottom-tier transistor (T3) is a pass-gate transistor (PG1, [0027]).
Regarding claim 23, Chanemougame in view of Liaw teaches the method of claim 21, but does not explicitly teach wherein from the top view, a third dimension of a third channel layer of the first top-tier transistor in the lengthwise direction of the first gate structure is less than the second dimension of the second channel layer of the second bottom-tier transistor.
Chanemougame teaches (Fig. 4B) wherein the first top-tier transistor is a pull-up transistor and wherein the second-tier transistor is a pass gate transistor ([0050]).
Liaw teaches wherein the channel width of a pass gate transistor can be wider than that of a pull-up transistor ([0027]).
Because Chanemougame and Liaw are both directed toward GAA SRAM devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Chanemougame and of Liaw to include wherein from the top view, a third dimension of a third channel layer of the first top-tier transistor in the lengthwise direction of the first gate structure is less than the second dimension of the second channel layer of the second bottom-tier transistor in order to avoid adopting write assist features in SRAM driving logic (Liaw, [0027]).
Regarding claim 24, Chanemougame in view of Liaw teaches (Chanemougame, annotated Fig. 4A below) the method of claim 23, wherein the third dimension (TH2) of the third channel layer of the first top-tier transistor is the same as the first dimension (TH1) of the first channel layer of the first bottom-tier transistor.
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Regarding claim 25, Chanemougame in view of Liaw teaches the method of claim 21, but does not explicitly teach wherein from the top view, a third dimension of a third channel layer of the second top-tier transistor in the lengthwise direction of the first gate structure is greater than the first dimension of the first channel layer of the first bottom-tier transistor.
Liaw further teaches (Fig. 2A) wherein the first dimension (W3, [0027]) of the first channel layer (206, [0027]) in a lengthwise direction of the first gate structure is less than the first dimension (W1, [0027]) of the first channel layer (202, [0027]) in the lengthwise direction of the first gate structure, and Chanemougame teaches wherein the channel width of upper transistors is equal to the channel width of the channels beneath, as shown in Fig. 4A.
Because Chanemougame and Liaw are both directed toward GAA SRAM devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chanemougame and of Liaw to include teach wherein from the top view, a third dimension of a third channel layer of the second top-tier transistor in the lengthwise direction of the first gate structure is greater than the first dimension of the first channel layer of the first bottom-tier transistor in order to avoid adopting write assist features in SRAM driving logic (Liaw, [0027]).
Conclusion
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/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812