DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I in the reply filed on 12/11/2025 is acknowledged. The traversal is on the ground(s) that there is no serious search burden between the claims.
Applicant’s arguments, filed 12/11/2025, with respect to the restriction between groups I and II have been fully considered and are persuasive. Groups I and II are hereby rejoined and fully examined for patentability under 37 CFR 1.104.
Because all claims previously withdrawn from consideration under 37 CFR 1.142 have been rejoined, the restriction requirement as set forth in the Office action mailed on 10/24/2025 is hereby withdrawn.
Status of Claims
This action is in reply to the response filed on 12/11/2025. Claims 1-20 are currently pending and have been examined.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1 (Currently Amended), the limitation “upon performing the double-sided polishing on the batch of semiconductor wafers according to the identified recipe, storing statistical process control (SPC) feedback data in a database to perform one or more additional iterations of the double-sided polishing on the batch of semiconductor wafers” is indefinite because the term “upon” renders the claim unclear if this step is conditional or if this step is performed while as the Office is able to read it both ways. If the term “upon” is read as conditional, then the limitation is not required and then claim 1 would require an analysis and possible rejection under 35 USC 101. However if the term “upon” is read as to limit the step to being done while performing the double-sided polishing, then this reads as a practical application of the steps within the controller. As such since it can be read two different ways, with two different interpretations, the limitation is therefore considered indefinite as the Office does not know what the applicant intends. For purposes of examination the Office will interpret the limitation to not be conditional and to read as “based on the amount of tuning required for the one or more flatness control parameters, identifying, or generating a recipe to perform the double-sided polishing on the batch of semiconductor wafers; [[and]
and
storing statistical process control (SPC) feedback data in a database to perform one or more additional iterations of the double-sided polishing on the batch of semiconductor wafers”.
Claims 2-10 are rejected as being dependent on claim 1.
Regarding claim 20 (Currently Amended), the limitation “upon performing an iteration of the double-sided polishing on the batch of semiconductor wafers according to the recipe, storing SPC feedback data corresponding to the performed iteration in a database” is indefinite because the term “upon” renders the claim unclear if this step is conditional or if this step is performed while as the Office is able to read it both ways. If the term “upon” is read as conditional, then the limitation is not required and then claim 1 would require an analysis and possible rejection under 35 USC 101. However if the term “upon” is read as to limit the step to being done while performing the double-sided polishing, then this reads as a practical application of the steps within the controller. As such since it can be read two different ways, with two different interpretations, the limitation is therefore considered indefinite as the Office does not know what the applicant intends. For purposes of examination the Office will interpret the limitation to not be conditional and to read as “based on the amount of tuning required for the one or more flatness control parameters, identifying a recipe to perform the double-sided polishing on the batch of semiconductor wafers, the recipe is identified based on analysis of historical statistical process control (SPC) feedback data; [[and]]
and
storing SPC feedback data corresponding to the performed iteration in a database.”
Claim Rejections - 35 USC § 101
The Office has examined claims 1-20 for compliance with 35 USC 101 and has concluded that the claims are subject matter eligible. That while the claims do recite abstract ideas (e.g. “determining whether a batch of semiconductor wafers is loaded on the wafer carrier for double-sided polishing” or “retrieving specification for the batch of semiconductor wafers” or “determining an amount of tuning required for one or more flatness control parameters” or “identifying or generating a recipe to perform the double-sided polishing on the batch of semiconductor wafers”) the claims also recite a practical application for the steps (claim 1, as interpreted under 112(b) above, recites “
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-17 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyazaki (US PGPUB No. 2020/0353585), hereinafter referred to as Miyazaki.
Regarding claim 1 (currently amended), Miyazaki discloses a polishing apparatus for double-sided polishing of semiconductor wafers, the polishing apparatus comprising:
a first platen [Miyazaki, fig 1, 2];
a second platen [Miyazaki, fig 1, 4];
a wafer carrier disposed within a gap formed between the first platen and the second platen [Miyazaki, fig 1, 12]; and
a controller [Miyazaki, fig 1, 16] configured to perform operations comprising:
determining whether a batch of semiconductor wafers is loaded on the wafer carrier for double-sided polishing [Miyazaki, page 4, pp 0094, the wafer is loaded before being measured and being polished];
in accordance with the determining that the batch of semiconductor wafer is loaded, retrieving specification for the batch of semiconductor wafers [Miyazaki, page 1, pp’s 0011-0016 teaching that a wafer is within the batch to start the method];
based on the retrieved specification for the batch of semiconductor wafers, determining an amount of tuning required for one or more flatness control parameters [Miyazaki, page 1, pp’s0007 and 0014-0016, teaching that polishing time is linked to polishing amount and wafer thickness]
based on the amount of tuning required for the one or more flatness control parameters, identifying, or generating a recipe to perform the double-sided polishing on the batch of semiconductor wafers [Miyazaki, page 1, pp 0015, polishing time is the recipe and page 5, pp’s 0102-0104 GBIR and ESFQD]; and
upon performing the double-sided polishing on the batch of semiconductor wafers according to the identified recipe, storing statistical process control (SPC) feedback data in a database to perform one or more additional iterations of the double-sided polishing on the batch of semiconductor wafers [Miyazaki, page 2, pp’s 0032-0047 and page 4, pp 0094 the arithmetic unit calculates the values using sensor data that is statistical control feedback data and is used for calculation of the next iteration of batches].
Regarding claim 2 (Currently Amended), Miyazaki further discloses the polishing apparatus of claim 1, wherein retrieving specification for the batch of semiconductor wafers comprises retrieving at least one of: incoming specification for the batch of semiconductor wafers, current specification for the batch of semiconductor wafers, or target specification for the batch of semiconductor wafers [Miyazaki, fig 2, S110 or S120].
Regarding claim 3 (Original), Miyazaki further discloses the polishing apparatus of claim 1, wherein the one or more flatness control parameters include at least one of: edge roll-off, or doming [Miyazaki, page 6, pp’s 0106-0107 teaching that the doming of flatness control is by the ESFQD term].
Regarding claim 4 (Currently Amended), Miyazaki further discloses the polishing apparatus of claim 1, wherein the identifying or generating the recipe comprises: based on the retrieved specification for the batch of semiconductor wafers [Miyazaki, page 1, pp’s0007 and 0014-0016], identifying a set of double-sided polishing parameters for tuning and a respective value for each parameter of the set of double-sided polishing parameters to perform an iteration of the double- sided polishing on the batch of semiconductor wafers [Miyazaki, page 5, pp’s 0102-0105, the ESFQD and GBIR value are a set of parameters for tuning the flatness of the wafer and are used in iterative for the following batches, where the second embodiment includes all of embodiment 1, with the added value of ESFQD]; making predictions of a respective value of each of the one or more flatness control parameters based on identified set of double-sided polishing parameters for tuning and the respective value for each parameter of the set of double-sided polishing parameters [Miyazaki, page 5, pp 0104, target ESFQD and target GBIR values]; and based on the predictions of the respective value of each of the one or more flatness control parameters, identifying or generating the recipe corresponding to the identified set of double-sided polishing parameters for tuning and the respective values for each parameter [Miyazaki, page 5, pp 0103].
Regarding claim 5 (Currently Amended), Miyazaki further discloses the polishing apparatus of claim 4, wherein the identifying or generating the recipe further comprises determining whether the set of double- sided polishing parameters for tuning and the respective value for each parameter of the set of double-sided polishing parameters are available for performing the double-sided polishing on the batch of semiconductor wafers [Miyazaki, page 5, pp’s 0102].
Regarding claim 6 (Original), Miyazaki further discloses the polishing apparatus of claim 4, wherein the set of double-sided polishing parameters for tuning includes at least one of: thickness or step time [Miyazaki, page 6, pp 0106, ESFQD is based on thickness data].
Regarding claim 7 (Original), Miyazaki further discloses the polishing apparatus of claim 4, wherein the set of double-sided polishing parameters for tuning includes at least one of: a top platen profile or a bottom platen profile [Miyazaki, page 5, pp 0105, the shape of the carrier plate which is interpreted to cover both the top platen profile or the bottom platen profile].
Regarding claim 8 (Original), Miyazaki further discloses the polishing apparatus of claim 4, wherein the set of double-sided polishing parameters for tuning includes at least one of: a rotational speed of a top platen, a rotational speed of bottom platen, a number of inner pin gears, or a number of outer pin gears [Miyazaki, page 4, pp 0091, the controller 16 controls the rotation of the upper plate 2 and the lower plate 4, sun gear 8, and internal gear 10].
Regarding claim 9 (Original), Miyazaki further discloses the polishing apparatus of claim 4, wherein making the predictions of the respective value of each of the one or more flatness control parameters comprises making predictions using one or more algorithms configured to predict the respective value of each of the one or more flatness control parameters based on historical SPC feedback data [Miyazaki, page 5, pp 0103, ESFQD value of wafer after polishing in previous batch term].
Regarding claim 10 (Currently Amended), Miyazaki further discloses the polishing apparatus of claim 1, wherein the SPC feedback data includes incoming specification for the batch of semiconductor wafers, current specification for the batch of semiconductor wafers, or target specification for the batch of semiconductor wafers, a batch run number, information of a customer, information of a customer order, or batch ID of semiconductor wafers [Miyazaki, page 5, pp’s 0100-0101].
Regarding claim 11 (Currently Amended), Miyazaki discloses a control system [Miyazaki, fig 1, 16] operatively connected with a polishing apparatus for double-sided polishing of semiconductor wafers [Miyazaki, fig 1], the control system comprising:
at least one memory configured to store instructions [Miyazaki, page 4, pp 0091, 20]; and
at least one processor configured to execute the stored instructions [Miyazaki, page 4, pp 0091, 19], which when executed, cause the at least one processor to perform operations comprising:
determining whether a batch of semiconductor wafers is loaded on a wafer carrier of the polishing apparatus [Miyazaki, page 4, pp 0094, the wafer is loaded before being measured and being polished];
in accordance with the determining that the batch of semiconductor wafer is loaded, retrieving specification for the batch of semiconductor wafers [Miyazaki, page 1, pp’s 0011-0016];
based on the retrieved specification for the batch of semiconductor wafers, determining an amount of tuning required for one or more flatness control parameters [Miyazaki, page 1, pp’s0007 and 0014-0016, teaching that polishing time is linked to polishing amount and wafer thickness];
based on the amount of tuning required for the one or more flatness control parameters, identifying, or generating a recipe to perform the double-sided polishing on the batch of semiconductor wafers [Miyazaki, page 1, pp 0015, polishing time is the recipe and page 5, pp’s 0102-0104 GBIR and ESFQD];
causing the polishing apparatus to perform double-sided polishing on the batch of semiconductor wafers using the recipe [Miyazaki, fig 1, S130]; and
receiving and storing statistical process control (SPC) feedback data in a database to perform one or more additional iterations of the double-sided polishing on the batch of semiconductor wafers [Miyazaki, page 2, pp’s 0032-0047 and page 4, pp 0094 the arithmetic unit calculates the values using sensor data that is statistical control feedback data and is used for calculation of the next iteration of batches].
Regarding claim 12 (Original), Miyazaki further discloses the control system of claim 11, wherein retrieving specification for the batch of semiconductor wafers comprises retrieving at least one of: incoming specification for the batch of semiconductor wafers, current specification for the batch of semiconductor wafers, or target specification for the batch of semiconductor wafers [Miyazaki, fig 2, S110 or S120].
Regarding claim 13 (Original), Miyazaki further discloses the control system of claim 11, wherein the one or more flatness control parameters include at least one of: edge roll-off, or doming [Miyazaki, page 6, pp’s 0106-0107 teaching that the doming of flatness control is by the ESFQD term].
Regarding claim 14 (Currently Amended), Miyazaki further discloses the control system of claim 11, wherein the identifying or generating the recipe comprises: based on the retrieved specification for the batch of semiconductor wafers [Miyazaki, page 1, pp’s0007 and 0014-0016], identifying a set of double-sided polishing parameters for tuning and a respective value for each parameter of the set of double-sided polishing parameters to perform an iteration of the double- sided polishing on the batch of semiconductor wafers [Miyazaki, page 5, pp’s 0102-0105, the ESFQD and GBIR value are a set of parameters for tuning the flatness of the wafer and are used in iterative for the following batches, where the second embodiment includes all of embodiment 1, with the added value of ESFQD]; making predictions of a respective value of each of the one or more flatness control parameters based on identified set of double-sided polishing parameters for tuning and the respective value for each parameter of the set of double-sided polishing parameters [Miyazaki, page 5, pp 0104, target ESFQD and target GBIR values]; and based on the predictions of the respective value of each of the one or more flatness control parameters, identifying or generating the recipe corresponding to the identified set of double-sided polishing parameters for tuning and the respective values for each parameter [Miyazaki, page 5, pp 0103].
Regarding claim 15 (Currently Amended), Miyazaki further discloses the control system of claim 14, wherein the identifying or generating the recipe further comprises determining whether the set of double-sided polishing parameters for tuning and the respective value for each parameter of the set of double-sided polishing parameters are available for performing the double-sided polishing on the batch of semiconductor wafers [Miyazaki, page 5, pp’s 0102].
Regarding claim 16 (Original), Miyazaki further discloses the control system of claim 14, wherein the set of double-sided polishing parameters for tuning includes at least one of: thickness, step time, a top platen profile, a bottom platen profile, a rotational speed of a top platen, a rotational speed of bottom platen, a number of inner pin gears, or a number of outer pin gears [Miyazaki, page 4, pp 0091, the controller 16 controls the rotation of the upper plate 2 and the lower plate 4, sun gear 8, and internal gear 10].
Regarding claim 17 (Original), Miyazaki further discloses the control system of claim 14, wherein making the predictions of the respective value of each of the one or more flatness control parameters comprises making predictions using one or more algorithms configured to predict the respective value of each of the one or more flatness control parameters based on historical SPC feedback data [Miyazaki, page 5, pp 0103, ESFQD value of wafer after polishing in previous batch term].
Regarding claim 19 (Currently Amended), Miyazaki further discloses the control system of claim 11, wherein the SPC feedback data includes incoming specification for the batch of semiconductor wafers, current specification for the batch of semiconductor wafers, or target specification for the batch of semiconductor wafers, a batch run number, information of a customer, information of a customer order, or batch ID of semiconductor wafers [Miyazaki, page 5, pp’s 0100-0101].
Regarding claim 20 (Currently Amended), Miyazaki discloses a method, comprising:
determining whether a batch of semiconductor wafers is loaded on a wafer carrier of a double-sided polishing apparatus [Miyazaki, page 4, pp 0094, the wafer is loaded before being measured and being polished];
in accordance with the determining that the batch of semiconductor wafer is loaded, retrieving specification for the batch of semiconductor wafers [Miyazaki, page 1, pp’s 0011-0016];
based on the retrieved specification for the batch of semiconductor wafers, determining an amount of tuning required for one or more flatness control parameters;
based on the amount of tuning required for the one or more flatness control parameters, identifying a recipe to perform the double-sided polishing on the batch of semiconductor wafers [Miyazaki, page 1, pp’s0007 and 0014-0016, teaching that polishing time is linked to polishing amount and wafer thickness], the recipe is identified based on analysis of historical statistical process control (SPC) feedback data [Miyazaki, page 1, pp 0015, polishing time is the recipe and page 5, pp’s 0102-0104 GBIR and ESFQD]; and
upon performing an iteration of the double-sided polishing on the batch of semiconductor wafers according to the recipe, storing SPC feedback data corresponding to the performed iteration in a database [Miyazaki, page 2, pp’s 0032-0047 and page 4, pp 0094 the arithmetic unit calculates the values using sensor data that is statistical control feedback data and is used for calculation of the next iteration of batches].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Miyazaki (US PGPUB No. 2020/0353585) as applied to claim 17 above, and in further view of Brooks et al (US PGPUB No. 2022/0146991), hereinafter referred to as Miyazaki and Brooks, respectively.
Regarding claim 18 (Original), Miyazaki further discloses the control system of claim 17, but does not explicitly disclose wherein the one or more algorithms are machine-learning algorithms trained using the historical SPC feedback data.
Brooks teaches a control system operatively connected with a polishing apparatus for polishing of semiconductor wafers [Brooks, abstract], the control system comprising: at least one memory configured to store instructions [Brooks, pp 0332]; and at least one processor configured to execute the stored instructions [Brooks, pp 0332], which when executed, cause the at least one processor to perform operations comprising: identifying, or generating a recipe to perform the polishing on the batch of semiconductor wafers [Brooks, fig 7, 702]; and receiving and storing statistical process control (SPC) feedback data in a database to perform one or more additional iterations of the polishing on the batch of semiconductor wafers [Brooks, fig 7, 704 -710]; wherein the identifying or generating the recipe comprises: based on the retrieved specification for the batch of semiconductor wafers, identifying a set of polishing parameters for tuning and a respective value for each parameter of the set of polishing parameters to perform an iteration of the polishing on the batch of semiconductor wafers [Brooks, fig 7, 704]; making predictions of a respective value of each of the one or more flatness control parameters based on identified set of polishing parameters for tuning and the respective value for each parameter of the set of polishing parameters [Brooks, fig 7, 706]; and based on the predictions of the respective value of each of the one or more flatness control parameters, identifying or generating the recipe corresponding to the identified set of polishing parameters for tuning and the respective values for each parameter [Brooks, fig 7, 708]; wherein making the predictions of the respective value of each of the one or more flatness control parameters comprises making predictions using one or more algorithms configured to predict the respective value of each of the one or more flatness control parameters based on historical SPC feedback data [Brooks, pp 0223]; and wherein the one or more algorithms are machine-learning algorithms trained using the historical SPC feedback data [Brooks, pp 0219].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have used machine-learning algorithms using the historical SPC feedback date as taught by Brooks in the control system of Miyazaki because this helps in identifying the best variables to make decisions and group data [Brooks, pp 0219, summarized].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kubota et al (US PGPUB No. 2021/0245321) teaches a double-sided polishing apparatus comprising a computing unit that groups data of thicknesses on a work basis and extracts shaped component of the work. Aoki et al (US Patent No. 9,156,123) teaches polishing and measuring flatness and improving flatness with being affected by variations in carrier thickness over time.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT NEIBAUR whose telephone number is (571)270-7979. The examiner can normally be reached M - F 8:00 am - 5:00 pm.
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/ROBERT F NEIBAUR/Primary Examiner, Art Unit 3723
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