Attorney Docket Number: 107642-1373212-010600US
Filing Date: 06/27/2023
Claimed Priority Date: none
Inventors: Wu et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the election filed on 01/12/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Elections/Restrictions
Applicant’s election of Invention I, reading on a semiconductor device, and Species 1, reading on figure 1F, in the reply filed on 01/12/2026, is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Applicant has canceled claims 15-20 and indicated that previously-presented claims 1-14 and newly-added claims 21-26 read on the elected species. The examiner agrees. Accordingly, pending in this Office action are claims 1-14 and 21-26.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "160" and "164" have both been used to designate a probe mark in figure 1B.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "164" has been used to designate both a corner portion (see, e.g., figure 1A) and a probe mark (see, e.g., figure 1B).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
The claims are objected to because of the following informalities:
In line 2 of claim 12, “extending through the first and second cover layer” should read “extending through the first and second cover layers”
Appropriate correction is required. No new matter should be added.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-14, 21, and 23-24 are rejected under 35 U.S.C. 112(b) for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1 and 21 each individually recite the limitation “a first cover layer disposed on the front side of the test pad”. No distinct side of the test pad has been previously sufficiently recited in either claim to constitute a “front side” of the test pad. Accordingly, there is insufficient antecedent basis for this limitation in the claims.
Claim 10 recites the limitation “… a third material having a stress level less than the stress level of the second material”. No form of any “stress level of the second material” has been previously sufficiently recited in the claim or in any parental claim. Accordingly, there is insufficient antecedent basis for this limitation in the claim.
Claims 1-14 depend from claim 1 and thus inherit the deficiencies identified supra.
Claims 23-24 depend from claim 21 and thus inherit the deficiencies identified supra.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 9, 11-13, 22, and 25-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen I (US 2020/0395254).
Regarding claim 1, Chen I (see, e.g., fig. 2B and par.0042/ll.8-10) shows all aspects of the instant invention, including a semiconductor structure 10 comprising:
a die 201 having a test pad (222 of 200 – hereinafter 222) (see, e.g., par.0026/ll.7-8) disposed on a front side 201a of the die, wherein:
the test pad 222 has a probe mark (227 of 200 – hereinafter 227) in an upper portion of the test pad; and
the probe mark has an open end (e.g., line corresponding to where 227 is horizontally aligned with 222t – see, e.g., topmost unmarked horizontal line corresponding to D1 as seen in fig. 1C) at a top surface 222t of the test pad, a bottom wall, a sidewall connected to the bottom wall, and a space (portion of 222 unfilled by 222 corresponding to 227) between the open end, the bottom wall, and the sidewall;
a first cover layer (225 of 200 – hereinafter 225) disposed on a front side 222t of the test pad and in the space (portion of 222 unfilled by 222 corresponding to 227), and on the sidewall and the bottom wall of the probe mark 227, and the first cover layer comprises a first material (e.g., silicon nitride) (see, e.g., par.0027/ll.12-13); and
a second cover layer (230a of 200 – hereinafter 230a) disposed on the first cover layer and in the space, wherein the second cover layer comprises a second material (e.g., silicon oxide) different from the first material (see, e.g., par.0029/ll.7-11)
With regards to other language recited in claim 1, see the comments stated above in paragraph 10.
Regarding claim 22, Chen I (see, e.g., fig. 1F and par.0029/ll.7-8) shows all aspects of the instant invention, including a semiconductor structure 100 comprising:
a die 101 having a test pad 122 (see, e.g., par.0026/ll.7-8), the test pad having a probe mark 127 in an upper portion thereof;
a first cover layer 125 disposed on the test pad and partially filling the probe mark; and
a second cover layer 130a disposed on the first cover layer;
wherein:
the second cover layer 130a comprises a protruding structure (e.g., portion of 130a filling space of 127 and recessed portion made by 125) that protrudes vertically into the probe mark from a first end aligned with a front surface of the first cover layer 125 to a second end within the probe mark 127
Regarding claim 2, Chen I (see, e.g., fig. 2B and pars.0029/ll.7-8 and 0042/ll.8-10) shows that the first cover layer 225 fills a first portion of the space (portion of 222 unfilled by 222 corresponding to 227) of the probe mark 227, the second cover 230a layer fills a second portion of the space of the probe mark, the first portion is connected to the sidewall and bottom wall of the probe mark, and the second portion is complementary to the first portion.
Regarding claim 9, Chen I (see, e.g., fig. 2B and par.0042/ll.8-10) shows a third cover layer (230b of 200 – hereinafter 230b) disposed on the second cover layer.
Regarding claim 11, Chen I (see, e.g., fig. 2B and par.0042/ll.8-10) shows a bonding layer 236 or 230c disposed on the third cover layer 230b, the bonding layer configured to form a bonding interface (e.g., 35) with another die 200’ or 201’ to be stacked onto the die 201.
Regarding claim 12, Chen I (see, e.g., fig. 2B and par.0042/ll.8-10) shows a connector (234 of 200 – hereinafter 234) in contact with the test pad 222 and extending through the first 225 and second 230a cover layer, the connector is proximate to the probe mark 227 and configured to be connected to another die 200’ or 201’.
Regarding claim 13, Chen I (see, e.g., fig. 2B and par.0042/ll.8-10) shows that the connector 234 is configured to be connected to another test pad (222 of 200’) in another die 200’ or 201’.
Regarding claim 25, Chen I (see, e.g., fig. 1F and par.0031/ll.16-23) shows a third cover layer 130c disposed on the second cover layer 130a, wherein the third cover layer comprises a planarized top surface.
Regarding claim 26, Chen I (see, e.g., fig. 1F and pars.0026/ll.16-20 and 29-31 and 0027/ll.6-8) shows that the protruding structure (e.g., portion of 130a filling space of 127 and recessed portion made by 125) has a bottom side (WP) at the first end that is less than an opening width (WO) (e.g., line corresponding to where 127 is horizontally aligned with 122t) of the probe mark 127.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen I.
Regarding claim 5, Chen I shows most aspects of the instant invention (see paragraphs 16-17 above). Chen I (see, e.g., fig. 2B) further shows that the first portion has a volume and the second portion has a volume, which are based on a total volume of the space (portion of 222 unfilled by 222 corresponding to 227) of the probe mark 227. Chen I, however, is silent with respect to the exact percentage of volume occupied by the first and second portions.
However, differences in percentage/volume will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed volume percentages, i.e., at least 35% and at most 65%, it would have been obvious to one of ordinary skill in the art to use these values in the device of Chen I.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed volume percentages or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 6, Chen I (see, e.g., figs. 1D and 2B and pars.0026/ll.28-30 and 0042/ll.8-10) shows that the probe mark 227 has a width W1 and a height D1, wherein the width as measured by a horizontal dimension of the open end (e.g., line corresponding to where 227 is horizontally aligned with 222t – see, e.g., topmost unmarked horizontal line corresponding to D1 as seen in fig. 1C) is from 12 µm to 16 µm, and the height as measured by a vertical distance from the open end to the bottom wall is from 0.5 µm to 0.8 µm.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66. Similarly, a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap but are close enough that one skilled in the art would have expected them to have the same properties. Titanium Metals Corp. of Amer.v.Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
"[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005).
Nevertheless, differences in width and height will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. Since the applicant has not established the criticality of the claimed width and height, i.e., from 12 µm to 16 µm and from 0.5 µm to 0.8 µm, it would have been obvious to one of ordinary skill in the art to use these values in the device of Chen I. See also the comments stated above in paragraphs 28-31 with respect to claim 5 regarding criticality, which are considered to be repeated here.
Claims 21 and 23 rejected under 35 U.S.C. 103 as being unpatentable over Chen I in view of West (US 2024/0113094).
Regarding claim 21, Chen I (see, e.g., fig. 1F) shows most aspects of the instant invention, including a semiconductor structure 100 comprising:
a die 101 having a test pad 122 (see, e.g., par.0026/ll.7-8) disposed on a front side 101a of the die, the test pad comprising a probe mark 127 defining a space (e.g., (portion of 122 unfilled by 122 corresponding to 127);
a first cover layer 125 disposed on a front side 122t of the test pad and lining the space of the probe mark, wherein the first cover layer comprises oxygen (see, e.g., par.0027/ll.12-13); and
a second cover layer 130a disposed on the first cover layer and filling a remaining portion of the space of the probe mark, wherein the second cover layer comprises oxygen (see, e.g., par.0029/ll.10)
Chen I shows most aspects of the instant invention. Chen I further teaches that Chen I’s first cover layer and second cover layer may each comprise oxygen and that Chen I’s cover layers are disposed above a silicon semiconductor substrate (see, e.g., par.0016/ll.1-2). Chen I, however, fails to explicitly specify that Chen I’s first cover layer comprises a low-stress oxide having a first stress level and that Chen I’s second cover layer comprises a high-stress oxide having a second stress level higher than the first stress level. West, in the same field of endeavor, teaches a semiconductor structure including a first cover layer comprising a low-stress oxide having a first stress level and a second cover layer comprising a high-stress oxide having a second stress level higher than the first stress level (see, e.g., West: par.0044/ll.28-30). West teaches that such a cover layer structure advantageously reduces bow or distortion of an underlying silicon semiconductor substrate while simultaneously improving the mechanical strength of the cover layer stack (see, e.g., West: par.0044/ll.31-34).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Chen I’s first cover layer comprise a low-stress oxide having a first stress level and Chen I’s second cover layer comprise a high-stress oxide having a second stress level higher than the first stress level, as taught by West, so as to advantageously reduces bow or distortion of Chen I’s underlying silicon semiconductor substrate while simultaneously improving the mechanical strength of Chen I’s cover layer stack.
With regards to other language recited in claim 21, see the comments stated above in paragraph 10.
Regarding claim 23, West (see, e.g., par.0018/ll.1-3) shows that the first cover layer (e.g., 117) comprises a tetraethyl orthosilicate (TEOS) oxide layer.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen I in view of Chen II (CN 113517220 A – published 10/19/2021). All citations from Chen II are taken from the equivalent U.S. document US 2023/0238306.
Regarding claim 7, Chen I shows most aspects of the instant invention (see paragraphs 16-17 above). Furthermore, Chen I (see, e.g., fig. 2B) shows that the first cover layer 225 has a first thickness and the second cover layer 230a has a second thickness, wherein Chen I appears to show that the second cover layer has a second thickness greater than the first thickness. However, Chen I does not explicitly state that the second cover layer has a second thickness greater than the first thickness. Chen II, in the same field of endeavor, teaches first and second cover layers composed of material similar to Chen I and disposed above a test pad, wherein the first and second cover layers having respective first and second thicknesses, and wherein the second cover layer has a second thickness greater than the first thickness (see, e.g., Chen II: par.0025/ll.10-12). Chen II teaches that such a dual cover-layer structure, taught by Chen II such that the second thickness of the second cover layer is greater than the first thickness of the first cover layer, can allow the second cover layer to provide a buffer to the test pad by alleviating stress generated from the first cover layer (see, e.g., Chen II: par.0025/ll.11-12).
Chen II is evidence showing that one of ordinary skill in the art would appreciate that a second thickness being explicitly greater than a first thickness would be equivalent to a second thickness being implicitly greater than a first thickness, and that such differences would result in no unexpected changes in the performance of the semiconductor structure of Chen I. That is, the first and second thicknesses of both Chen I and Chen II would yield the predictable result of providing suitably formed and sized cover layers capable of integration and mechanical connection with a test pad.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a second thickness explicitly greater than a first thickness, as taught by Chen II, or a second thickness implicitly greater than a first thickness, as taught by Chen I, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitably formed and sized cover layers capable of integration and mechanical connection with a test pad. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Furthermore, Chen II is evidence that at the time of filing the invention it would have been obvious that one of ordinary skill in the art would find particular incentive to have Chen I’s second cover layer possess a second thickness greater than the first thickness, so as to allow Chen I’s second cover layer to provide a buffer to Chen I’s test pad by alleviating stress generated from the first cover layer. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Chen I’s second cover layer have a second thickness greater than the first thickness, as taught by Chen II, so as to allow Chen I’s second cover layer to provide a buffer to Chen I’s test pad by alleviating stress generated from the first cover layer.
Regarding claim 8, Chen II (see, e.g., Chen II: par.0025/ll.10-12) shows that the first thickness (e.g., of 122a) is from 0.3 µm to 0.7 µm.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66. Similarly, a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap but are close enough that one skilled in the art would have expected them to have the same properties. Titanium Metals Corp. of Amer.v.Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
"[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005).
Nevertheless, differences in thickness will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. Since the applicant has not established the of the claimed thickness, i.e., from 0.3 µm to 0.7 µm, it would have been obvious to one of ordinary skill in the art to use these values in the device of Chen I or Chen I/Chen II. See also the comments stated above in paragraphs 28-31 with respect to claim 5 regarding criticality, which are considered to be repeated here.
Claims 3-4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen I in view of Assefa (US 2014/0091374) and West.
Regarding claim 3, Chen I (see paragraphs 16-17) shows most aspects of the instant invention, including a first cover layer 225 of a first material and a second cover layer 230a of a second material, wherein the first material and second material are different. Chen I (see, e.g., fig. 2B and par.0016/ll.1-2) further shows that the first and second cover layers encapsulate conductive structures of Chen I’s device and that Chen I’s cover layers are disposed over a silicon semiconductor substrate. Chen I, however, fails to explicitly specify that the first material has a first stress level and that the second material has a second stress level higher than the first stress level. Assefa, in the same field of endeavor, teaches a semiconductor structure including a conductive-encapsulating structure having a first cover layer of a first material having a first stress level and a second cover layer of a second material having a second stress level higher than the first stress level (see, e.g., Assefa: pars.0020/ll.41-42, 0021/ll.11-12, and 0024/ll.12-16). Assefa teaches that such a multi-layered and varied stress structure may minimize cracks and contamination in the encapsulated conductive structure (see, e.g., Assefa: par.0014/ll.14-18). Furthermore, West, also in the same field of endeavor, teaches a structure having a first cover layer comprising a first material having a first stress level and a second cover layer comprising a second material having a second stress level higher than the first stress level (see, e.g., West: pars.0031/ll.1-4 and 0044/ll.28-30). West teaches that such a cover layer structure advantageously reduces bow or distortion of an underlying silicon semiconductor substrate while simultaneously improving the mechanical strength of the cover layer stack (see, e.g., West: par.0044/ll.31-34).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Chen I’s first material have a first stress level and Chen I’s second material have a second stress level higher than the first stress level, as taught by Assefa and West, so as to minimize cracks and contamination in Chen I’s encapsulated conductive structures while advantageously reducing bow or distortion of Chen I’s underlying silicon semiconductor substrate and improving the mechanical strength of the cover layer stack.
Regarding claim 4, Assefa (see, e.g., pars.0020/ll.41-42 and 0021/ll.11-12) shows that the first stress level (e.g., of 152) is from 130 MPa to 160 MPa, and the second stress level (e.g., of 154) is from 170 MPa to 230 MPa.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66. Similarly, a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap but are close enough that one skilled in the art would have expected them to have the same properties. Titanium Metals Corp. of Amer.v.Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
"[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005).
Nevertheless, differences in levels of stress will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. Since the applicant has not established the of the claimed stresses, i.e., from 130 MPa to 160 MPa and from 170 MPa to 230 MPa, it would have been obvious to one of ordinary skill in the art to use these values in the device of Chen I/Assefa/West. See also the comments stated above in paragraphs 28-31 with respect to claim 5 regarding criticality, which are considered to be repeated here.
Regarding claim 10, Chen I (see paragraphs 16-17 and 20) shows most aspects of the instant invention, including a second cover layer 230a of a second material and a third cover layer 230b of a third material (see, e.g., pars.0030/ll.3-4 and 0042/ll.8-10). Chen I (see, e.g., fig. 2B and par.0016/ll.1-2) further shows that the first, second, and third cover layers encapsulate conductive structures of Chen I’s device and that Chen I’s cover layers are disposed over a silicon semiconductor substrate. Chen I, however, fails to explicitly specify that the third cover layer comprises a third material having a stress level less than a stress level of the second material. Assefa, in the same field of endeavor, teaches a semiconductor structure including a conductive-encapsulating structure having a third cover layer comprising a third material having a stress level less than a stress level of a second material (see, e.g., Assefa: pars.0020/ll.41-42, 0021/ll.12, and 0022/ll.10-15). Assefa teaches that such a multi-layered and varied stress structure may minimize cracks and contamination in the encapsulated conductive structure (see, e.g., Assefa: par.0014/ll.14-18). Furthermore, West, also in the same field of endeavor, teaches a structure having a third cover layer comprising a third material having a stress level less than a stress level of a second material (see, e.g., West: par.0044/ll.28-30). West teaches that such a cover layer structure advantageously reduces bow or distortion of an underlying silicon semiconductor substrate while simultaneously improving the mechanical strength of the cover layer stack (see, e.g., West: par.0044/ll.31-34).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Chen I’s third cover layer comprise a third material having a stress level less than a stress level of the second material, as taught by Assefa and West, so as to minimize cracks and contamination in Chen I’s encapsulated conductive structures while advantageously reducing bow or distortion of Chen I’s underlying silicon semiconductor substrate and improving the mechanical strength of the cover layer stack.
With regards to other language recited in claim 10, see the comments stated above in paragraph 11.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chen I in view of Yang (US 2019/0131277).
Regarding claim 14, Chen I shows most aspects of the instant invention (see paragraphs 16-17 and 22-23 above), and further shows that Chen I’s connector 234 is conductive (see, e.g., par.0043/ll.11-13). Chen I (see, e.g., par.0074) further teaches that Chen I’s semiconductor structure may be equivalently modified while maintaining the scope of Chen I’s device. Chen I, however, fails to explicitly specify that Chen I’s connector is a micro-bump. Yang, in the same field of endeavor, teaches micro-bumps to be suitable conductive connection structures capable of integration with test pads and other conductive assemblies in a semiconductor device (see, e.g., Yang: par.0043/ll.13-15).
Yang is evidence showing that one of ordinary skill in the art would appreciate that a micro-bump connector would be equivalent to another conductive connector, and that such differences would result in no unexpected changes in the performance of the semiconductor structure of Chen I. That is, the connector structures of both Chen I and Yang would yield the predictable result of providing a suitable conductive pathway in a semiconductor structure capable of mechanical and electrical integration with test pads and other conductive assemblies.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a micro-bump connector, as taught by Yang, or a conductive connector of another form, as taught by Chen I, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a suitable conductive pathway in a semiconductor structure capable of mechanical and electrical integration with test pads and other conductive assemblies. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Chen I/West in view of Chen II.
Regarding claim 24, Chen I/West shows most aspects of the instant invention (see paragraphs 37-40 above). Chen I (see, e.g., fig. 1F) further shows that Chen I’s first cover layer 125 has a first thickness on a top surface 122t of the test pad 122, and the second cover layer 130a has a thickness (T4) measured from a front surface of the first cover layer to a front surface of the second cover layer, wherein Chen I appears to show that T4 is greater than the first thickness. Chen I, however, is silent with respect to a ratio of T4 to the first thickness being at least 2. Chen II, in the same field of endeavor, teaches first and second cover layers similar to Chen I and disposed above a test pad, wherein the first and second cover layers having respective first and T4 thicknesses, and wherein a ratio of T4 to the first thickness is at least 2 (see, e.g., Chen II: par.0025/ll.10-12). Chen II teaches that such a dual cover-layer structure, taught by Chen II such that a ratio of T4 to the first thickness may be at least 2, can allow the second cover layer to provide a buffer to the test pad by alleviating stress generated from the first cover layer (see, e.g., Chen II: par.0025/ll.11-12).
Chen II is evidence showing that one of ordinary skill in the art would appreciate that having a ratio of T4 to the first thickness being at least 2 would be equivalent to having another relation of a ratio of T4 to the first thickness, and that such differences would result in no unexpected changes in the performance of the semiconductor structure of Chen I. That is, the T4 to first thickness thickness ratios of both Chen I and Chen II would yield the predictable result of providing suitably formed and sized cover layers capable of interaction and mechanical connection with a test pad.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a ratio of T4 to the first thickness be at least 2, as taught by Chen II, or another relation of a ratio of T4 to the first thickness, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a conductive pathway between layers of an integrated circuit structure. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Furthermore, Chen II is evidence that at the time of filing the invention it would have been obvious that one of ordinary skill in the art would find particular incentive to have Chen I’s ratio of T4 to the first thickness be at least 2, so as to allow Chen I’s second cover layer to provide a buffer to Chen I’s test pad by alleviating stress generated from the first cover layer. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Chen I’s ratio of T4 to the first thickness being at least 2, as taught by Chen II, so as to allow Chen I’s second cover layer to provide a buffer to Chen I’s test pad by alleviating stress generated from the first cover layer.
Nevertheless, differences in ratio of thickness will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. Since the applicant has not established the of the claimed thickness ratio, i.e., at least 2, it would have been obvious to one of ordinary skill in the art to use these values in the device of Chen I/West. See the comments stated above in paragraphs 28-31 with respect to claim 5 regarding criticality, which are considered to be repeated here.
Conclusion
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814