Prosecution Insights
Last updated: April 19, 2026
Application No. 18/342,751

SEMICONDUCTOR STACKING STRUCTURE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§103
Filed
Jun 28, 2023
Examiner
SIPLING, KENNETH MARK
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
100%
Grant Probability
Favorable
1-2
OA Rounds
3y 5m
To Grant
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allow Rate
2 granted / 2 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
45 currently pending
Career history
47
Total Applications
across all art units

Statute-Specific Performance

§103
61.0%
+21.0% vs TC avg
§102
21.4%
-18.6% vs TC avg
§112
17.7%
-22.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 2 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election filed on 5/30/2024, to prosecute the claims of Invention I, claims 1-16 and new claims 21-24 is acknowledged. Applicant’s election of Invention I in the reply filed on 11/6/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Information Disclosure Statement The information disclosure statement (IDS) submitted on 5/30/2024 is being considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 5-7, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yaung et al. (US 20160211248 A1, IDS). Re Claim 1 Yaung teaches a stacking structure (FIG. 9), comprising: a first die (212) [0028] having a first region (120 + regions between 120 and the die edge) [0023] and a second region (118) [0023] encircled by the first region (120 + regions between 120 and the die edge), wherein the first die (212) includes first metallization structures (232 [0031], 236 [0028]) embedded in a first insulating material (226) [0031] and a first bonding (224) [0033] structure located over the first insulating material (226) and the first metallization structures (232, 236), wherein, in the first region, the first metallization structures (232, 236) include a first seal ring structure (236) [0028] and the first bonding structure (224) includes first dummy pads (224B) [0034] located over the first seal ring structure (236); and a second die stacked (112) [0017] on and bonded with the first die (212), wherein the second die (112) includes second metallization structures (132 [0024], 136 [0040]) embedded in a second insulating material (126) [0023] and a second bonding structure (124) [0023] located over the second insulation material (126) and the second metallization structures (132, 136), wherein the second metallization structures include a second seal ring structure (136) [0040], and the second bonding structure (124) includes second dummy pads (124B) [0026] located over the second seal ring structure (136), wherein the first die and the second die are bonded through bonding of the first (224) and second (124) bonding structures, the first (236) and second seal ring structures (136) are substantially vertically aligned, and the first dummy pads (224B) are respectively bonded with the second dummy pads (124B, FIG. 8 and 9). Re Claim 2 Yaung teaches the structure of claim 1, wherein there is a first pad-free zone in the first insulation material (226) located above the first seal ring structure (236) and overlapped with the first seal ring structure (236, FIG. 8 and 9). Re Claim 3 Yaung teaches the structure of claim 2, wherein the first pad-free zone is sandwiched between the first seal ring (236) structure and the first dummy pads (224B, FIG. 8 and 9). Re Claim 5 Yaung teaches the structure of claim 2, wherein there is a second pad-free zone (126 [0023] material under 136 [0017], FIG. 8 and 9) in the second insulation material (126) located above the second seal ring structure (136) and overlapped with the second seal ring structure (FIG. 3 shows 112 rotated 180 degrees compared to 112 in FIG. 9. Therefore, the second pad-free zone would be above seal ring structure 136 during manufacturing). Re Claim 6 Yaung teaches the structure of claim 4, wherein the second pad-free zone (126 material under 136, FIG. 9) is sandwiched between the second seal ring structure (136) and the second dummy pads (124B, [0026], FIG. 9 ). Re Claim 7 Yaung teaches the structure of claim 1, wherein in the second region (118), the first bonding structure (224) includes first bonding pads (224A) [0034], and the second bonding structure (124) includes second bonding pads (124A) [0026], and the first bonding pads are respectively bonded (224A) with the second bonding pads (124A), and the first (212) and second (112) dies are electrically connected through the first (232, 236) and second (132) metallization structures and the first (224A) and second (124A) bonding pads (FIG. 9). Re Claim 21 Yaung teaches a structure (FIG. 9), comprising: a first die (212) [0028] having a first region (120 + regions between 120 and the die edge) and a second region (118) around the first region, wherein the first die (212) includes a first insulating material (226) [0031], a first seal ring (236) [0028] structure embedded in the first insulating material (226), and a first bonding structure (224) [0033] located over the first insulating material (226), wherein, in the first region (120 + regions between 120 and the die edge), the first bonding structure includes first dummy pads (224B) [0034] located over the first seal ring structure (236) in the first region and first bonding pads (224A) [0034] in the second region (118); and a second die (112) [0017], disposed on and bonded with the first die (212), wherein the second die includes a second insulating material (126) [0023], a second seal ring structure (136) [0040] embedded in the second insulating material (126), and a second bonding structure (124) [0023] located over the second insulation material (126), wherein the second bonding structure (124) includes second dummy pads (124B) [0026] located over the second seal ring structure (136) and second bonding pads (124A) [0026], wherein the second bonding structure (124) is bonded with the first bonding structure (224), a location of the second seal ring structure (136) is overlapped with a location of the first seal ring structure (236), and the second dummy pads (124B) are respectively bonded with the first dummy pads (224B) in the first region (120 + regions between 120 and the die edge, FIG. 8 and 9). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yaung et al. (US 20160211248 A1, IDS) in view of Hu (US 20190164914 A1). Re Claim 4 Yaung teaches the structure of claim 2, but does not teach at least one nail via is located between and connects the second seal ring structure and at least one second dummy pad. Hu teaches at least one nail via (554) [0106] is located between and connects the second seal ring structure (534) and at least one second dummy pad (552, [0106], 542B is the same material as 542B and only connects to pad 752 which has no electrical connection besides 552, FIG. 15). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Hu in combination with Yaung since Hu teaches a stacked die structure. The ordinary artisan would have been motivated to modify Hu in combination with Yaung in the above manner for the motivation of integrating a nail via into the semiconductor device to connect dies to one another and ensure optimal electrical connections. [0023] states, “Dies may be designed with bond pads to provide electrical and mechanical attachment points to bond another die or device thereto to form a package.” Claims 8-12, 14, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Yaung et al. (US 20160211248 A1, IDS) in view of Cho (US 20220189854 A1). Re Claim 8 Yaung teaches the structure of claim 1, but does not teach a redistribution structure disposed on the second die. Cho teaches a redistribution structure (RDL10) [0055] disposed on the second die (45) [0051] (FIG. 1K). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Cho in combination with Yaung since Cho teaches a stacked die structure. The ordinary artisan would have been motivated to modify Cho in combination with Yaung in the above manner for the motivation of integrating a RDL over the second die to help the structure as chip size continues to scale lower. [0002] states, “For the most part, this improvement in integration density has come from continuous reductions in minimum feature size, which allows more of the smaller components to be integrated into a given area.” Re Claim 9 Yaung in view of Cho teaches the structure of claim 8, wherein the second metallization structures (Cho, 41, 43) [0052] include through semiconductor vias (43), and the redistribution structure (RDL10) is electrically connected with the second die (45) via the through semiconductor vias (43, FIG. 1K). Re Claim 10 Yaung teaches a stacking structure (FIG. 9), comprising: a first die (212) [0028] having a first region (120 + regions between 120 and the die edge) and a second region (118) encircled by the first region, wherein the first die (212) includes first metallization structures (232 [0031], 236 [0028]) embedded in a first insulating material (226) [0031] and a first bonding structure (224) [0033] located over the first insulating material (226) and the first metallization structures (232, 236), wherein, in the first region (120 + regions between 120 and the die edge), the first metallization structures (232, 236) include a first seal ring structure (236) [0028] and the first bonding structure (224) includes first dummy pads (224B) [0034] located over the first seal ring structure (FIG. 9); a second die (112) [0017] stacked on and bonded with the first die (212), wherein the second die includes second metallization structures (132 [0024], 136 [0040]) embedded in a second insulating material (126) [0023] and a second bonding structure (124) [0023] located over the second insulation material (126) and the second metallization structures (132, 136), wherein the second metallization structures include a second seal ring structure (136) [0040], and the second bonding structure (124) includes second dummy pads (124B) [0026] located over the second seal ring structure (136); and wherein the second bonding structure (124) is bonded with the first bonding structure (224), the second seal ring structure (136) is partially aligned with the first seal ring structure (236), and the second dummy pads (124B) are respectively bonded with the first dummy pads (224B) in the first region (120 + regions between 120 and the die edge, FIG. 8 and 9). Yaung does not teach a filling material disposed on the first die and around the second die. Cho teaches a filling material (48) [0053] disposed on the first die (25) [0031] and around the second die (45, [0051], FIG. 1I). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Cho in combination with Yaung since Cho teaches a stacked die structure. The ordinary artisan would have been motivated to modify Cho in combination with Yaung in the above manner for the motivation of integrating a filler layer around the second die to ensure the die is electrically encapsulated and functions at a peak level. [0053] states, “Still referring to FIG. 1I, an encapsulant material layer 48 is then formed on the RDL structure 32 to encapsulant sidewalls and top surfaces of the die 45…” Re Claim 11 Yaung in view of Cho teaches the structure of claim 10, further comprising a redistribution structure (Cho, RDL10) [0055] disposed on the second die (45), and the redistribution structure (RDL10) is electrically connected with through semiconductor vias (43) [0056] of the second die (45, FIG. 1K). Re Claim 12 Yaung in view of Cho teaches the structure of claim 10, wherein there is a first pad-free zone in the first insulation material (Yaung, 226) sandwiched between the first seal ring structure (236) and the first dummy pads (224B) and overlapped with the first seal ring structure (236, FIG. 8 and 9). Re Claim 14 Yaung in view of Cho teaches the structure of claim 12, wherein there is a second pad-free zone in the second insulation material (Yaung, 126) sandwiched between the second seal ring structure (136) and the second dummy pads (124B) and overlapped with the second seal ring structure (136), and the first and second pad-free zones within the first region (120 + regions between 120 and the die edge) are aligned (FIG. 8 and 9). Re Claim 22 Yaung teaches the structure of claim 21, but does not teach a filling material disposed over the first die and covering the second die, and the filling material is in contact with at least one first dummy pad. Cho teaches a filling material (48) [0053] disposed over the first die (25) [0031] and covering the second die (45) [0051], and the filling material is in contact with at least one first dummy pad (FIG. 1K, Integrating the filling layer from Cho into the device from Yaung would cause the Cho filling material to be part of the same semiconductor structure as the Yaung first dummy pads putting the 2 components into mechanical contact.). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Cho in combination with Yaung since Cho teaches a stacked die structure. The ordinary artisan would have been motivated to modify Cho in combination with Yaung in the above manner for the motivation of integrating a filler layer around the second die to ensure the die is electrically encapsulated and functions at a peak level. [0053] states, “Still referring to FIG. 1I, an encapsulant material layer 48 is then formed on the RDL structure 32 to encapsulant sidewalls and top surfaces of the die 45…” Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yaung et al. (US 20160211248 A1, IDS) in view of Cho (US 20220189854 A1) and further in view of Hu (US 20190164914 A1). Re Claim 13 Yaung in view of Cho teaches the structure of claim 12, but does not teach at least one nail via is located between and connects the second seal ring structure and at least one second dummy pad. Hu teaches at least one nail via (554) [0106] is located between and connects the second seal ring structure (534) and at least one second dummy pad (552, [0106], 542B is the same material as 542B and only connects to pad 752 which has no electrical connection besides 552, FIG. 15). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Hu in combination with Yaung in view of Cho since Hu teaches a stacked die structure. The ordinary artisan would have been motivated to modify Hu in combination with Yaung in view of Cho in the above manner for the motivation of integrating a nail via into the semiconductor device to connect dies to one another and ensure optimal electrical connections. [0023] states, “Dies may be designed with bond pads to provide electrical and mechanical attachment points to bond another die or device thereto to form a package.” Claims 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Yaung et al. (US 20160211248 A1, IDS) in view of Cho (US 20220189854 A1) and further in view of Uryu (US 10879260 B2). Re Claim 23 Yaung in view of Cho teaches the structure of claim 22, but does not teach a third die disposed on the first die and bonded with the first die. Uryu teaches a third die (900C, col 27 line 39) disposed on the first die and bonded with the first die (900A, col 27 line 36, FIG. 22). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Uryu in combination with Yaung in view of Cho since Uryu teaches a stacked die structure. The ordinary artisan would have been motivated to modify Uryu in combination with Yaung in view of Cho in the above manner for the motivation of forming a third die in the stacked die structure to optimally control peripheral circuitry. Col 41 line 61 states, “The peripheral circuitry of the support die 700 may be configured to control two or more three-dimensional arrays of memory elements provided in a respective memory die…” Yaung in view of Cho and Uryu does not explicitly teach the third die includes a third insulating material, a third seal ring structure, and a third bonding structure located over the third insulation material, and the third bonding structure includes third dummy pads located over the third seal ring structure and third bonding pads, the second and third dummy pads are respectively bonded with the first dummy pads, and the second and third bonding pads are respectively bonded with the first bonding pads, and wherein a location of the third seal ring structure is overlapped with the location of the first seal ring structure. One can repeat the process (Yaung, FIG. 8 and 9) of stacking the first and second dies to integrate a third die. Use 112 [0017] as the third die, 126 [0023] is the third insulating material, 136 [0017] can be a third seal ring structure, 124 [0023] is a third bonding structure located over the third insulating material (126), and the third bonding structure (124) includes third dummy pads (124B) [0026] located over the third seal ring structure (136) and third bonding pads (124A) [0026], the second (224B) and third (124B) bonding pads are respectively bonded to the first bonding pads (first bonding pads will be bonded through other semiconductor layers to [124A and 224B] what are being used as 2nd and 3rd bonding pads), and wherein a location of the third seal ring structure (136) is overlapped with the location of the first seal (236 is being used as 2nd seal rung structure, but it was previously taught the second seal ring is over the first seal ring. The third seal ring is over the second seal ring. Therefore the third seal ring will be over the first seal ring) ring structure. The ordinary artisan would have been motivated to modify Yaung in combination with Yaung in view of Cho and Uryu in the above manner for the motivation of stacking a third die into the die structure and lining up the chip features for optimal semiconductor device performance. Re Claim 24 Yaung in view of Cho and Uryu teaches the structure of claim 23, further comprising a redistribution layer disposed (Cho, RDL10) [0055] on the second and third dies (25 and 45, repeat process from first and second dies) and the filling material (48) [0053], and conductive terminals (43) [0052] disposed on the redistribution layer (Cho, FIG. 1M). Allowable Subject Matter Claims 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KENNETH MARK SIPLING/Examiner, Art Unit 2818 /DUY T NGUYEN/Primary Examiner, Art Unit 2818 2/6/26
Read full office action

Prosecution Timeline

Jun 28, 2023
Application Filed
Feb 05, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 3 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
3y 5m
Median Time to Grant
Low
PTA Risk
Based on 2 resolved cases by this examiner. Grant probability derived from career allow rate.

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