DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 16-30 in the reply filed on 12/25/2025 is acknowledged.
Claims 1-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group I invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/25/2025.
Newly submitted claims 31-35 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
Claim 31 is drawn to an embodiment of Figs. 6A-6E, wherein a cutting structure is formed before removing the first dummy gate structure. However, the originally filed claims 16 and 18 are drawn to an embodiment of Figs. 2A-2H, wherein a cutting structure is formed over the dielectric wall that is formed after removing the first dummy gate structure. Specifically, claim 16 requires “after removing the first dummy gate structure, removing a portion of the isolation material to form an isolation structure, and a remaining portion of the isolation material becomes a dielectric wall”, and claim 18 recites “forming a cutting structure over the dielectric wall” that is formed “after removing the first dummy gate structure”, as shown in Fig. 2H-3; and that is distinct from the embodiment of Figs. 6A-6E, wherein a cutting structure is formed before removing the first dummy gate structure (e.g., Fig. 6B-3).
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 31-35 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Objections
Claim 21 is objected to because of the following informalities:
Claim 21 recites “though a portion” which should be replaced with “through a portion” to improve claim language.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 23 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 23 recites “forming a cutting structure over the dielectric wall; and after forming the cutting structure, removing the first dummy gate structure”. However, claim 16 recites “after removing the first dummy gate structure, removing a portion of the isolation material to form an isolation structure, and a remaining portion of the isolation material becomes a dielectric wall” such that “the dielectric wall” is formed “after removing the first dummy gate structure”. Thus, “a cutting structure over the dielectric wall” (recited in claim 23) is formed “after removing the first dummy gate structure”, but not before removing the first dummy gate structure. Thus, claims 23 fails to include all the limitations of the claim 16 upon which it depends.
It appears that claim 23 is drawn to an embodiment of 6A-6E, wherein a cutting structure is formed before removing the first dummy gate structure (e.g., Fig. 6B-3). However, claim 16 is drawn to an embodiment of Figs. 2A-2H, wherein a cutting structure is formed over the dielectric wall that is formed after removing the first dummy gate structure (e.g., Fig. 2H-3).
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16-17, 20, 22, 24, and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0366908 to Pan et al. (hereinafter Pan).
With respect to claim 16, Pan discloses a method for forming a semiconductor structure (e.g., fabrication process for a semiconductor structure including a dielectric fin for isolating metal gates, see the annotated Figs. 10, 12, 23, and 24 below) (Pan, Figs. 2-26, 27A-27E, ¶0010-¶0050), comprising:
forming a first fin structure (e.g., a first fin 218) (Pan, Fig. 2, ¶0013-¶0017) and a second fin structure (e.g., a second fin 218) over a first region and a second region of a substrate (201), respectively, wherein the first fin structure (e.g., the first fin 218) comprises first semiconductor material layers (215) and second semiconductor material layers (210) alternately stacked, and the second fin structure (e.g., the second fin 218) comprises the first semiconductor material layers (215) and the second semiconductor material layers (210) alternately stacked;
forming an isolation material (230/232/233/234) (Pan, Figs. 4-11, ¶0019-¶0024) adjacent to the first fin structure (e.g., the first fin 218) and the second fin structure (e.g., the second fin 218);
forming a first dummy gate structure (240) (Pan, Fig. 12, ¶0025) over the isolation material (230/232/233/234), the first fin structure (e.g., the first fin 218) and the second fin structure (e.g., the second fin 218);
removing the first dummy gate structure (Pan, Figs. 20-22, ¶0033-¶0034) to expose the first fin structure (e.g., the first fin 218) and the second fin structure (e.g., the second fin 218);
after removing the first dummy gate structure, removing a portion of the isolation material (e.g., trimming process to remove portions of the isolation material 232/233/234) (Pan, Fig. 23, ¶0036-¶0038) to form an isolation structure (e.g., dielectric fin 229-2 including isolation material 230/232/233), and a remaining portion of the isolation material becomes a dielectric wall (e.g., dielectric fin 229-1 including isolation material 230/232/233/234) between the first
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fin structure and the second fin structure;
removing all of the second semiconductor material layers (210) (Pan, Fig. 22, ¶0035) to expose the first semiconductor material layers (215); and
forming a gate structure (349/350) (Pan, Fig. 24, ¶0039-¶0040) to surrounding the first semiconductor material layers (215), wherein the gate structure (349/350) is in direct contact with the dielectric wall (229-1) and the isolation structure (229-2).
Regarding claim 17, Pan discloses the method for forming the semiconductor structure as claimed in claim 16. Further, Pan discloses the method, wherein a top surface of the isolation material (230/232/233/234) (Pan, Fig. 10, ¶0023) is substantially coplanar with a top surface of the first fin structure (e.g., the first 218) and a top surface of the second fin structure (e.g., the second 218) before forming the first dummy gate structure.
Regarding claim 20, Pan discloses the method for forming the semiconductor structure as claimed in claim 16. Further, Pan discloses the method, further comprising: forming a first gate spacer layer (247) (Pan, Fig. 15, ¶0028) adjacent to the first dummy gate structure (240); and forming an inner spacer (255) directly below the first gate spacer layer (247), wherein a topmost surface of the inner spacer (255) is lower than a top surface of the dielectric wall (e.g., the dielectric fin 229-1 with a top surface of the dielectric portion 234).
Regarding claim 22, Pan discloses the method for forming the semiconductor structure as claimed in claim 16. Further, Pan discloses the method, further comprising: forming a refill material (e.g., low-k dielectric fill material 233) (Pan, Fig. 8, ¶0022) on the isolation material (e.g., 230/232, including high-k dielectric material 232) (Pan, Fig. 8, ¶0021), wherein the refill material (233) and the isolation material (230/232) are made of different materials.
Regarding claim 24, Pan discloses the method for forming the semiconductor structure as claimed in claim 16. Further, Pan discloses the method, further comprising: removing a portion of the first fin structure (e.g., the first 218) and a portion of the second fin structure (e.g., the second 218) to form a first S/D recess (e.g., the first S/D trench 250) (Pan, Fig. 13, ¶0027) and a second S/D recess (e.g., the second S/D trench 250); forming a first S/D structure (260-1) (Pan, Fig. 16, ¶0029) in the first S/D recess (e.g., the first S/D trench 250); and forming a second S/D structure (260-2) in the second S/D recess (e.g., the second S/D trench 250), wherein the isolation material (230/232/233/234) is between the first S/D structure (260-1) and the second S/D structure (260-2).
Regarding claim 25, Pan discloses the method for forming the semiconductor structure as claimed in claim 16. Further, Pan discloses the method, wherein forming the gate structure (349/350) (Pan, Fig. 24, ¶0039-¶0040) further comprises: forming a gate dielectric layer (349) on a top surface of the dielectric wall (229-1); and forming a gate electrode layer (350) on the gate dielectric layer (349).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0366908 to Pan in view of Chiang et al. (US 2021/0265508, hereinafter Chiang).
Regarding claim 18, Pan discloses the method for forming the semiconductor structure as claimed in claim 16. Further, Pan does not specifically disclose the method, further comprising: forming a cutting structure over the dielectric wall.
However, Chiang teaches forming a cutting structure (154) (Chiang, Figs. 2O-2S, ¶0013-¶0014, ¶0089-¶0101) over the dielectric wall (123’) to separate the metal gate stack (142) into multiple portions that are electrically isolated from each other, wherein the cutting structure (154) (Chiang, Figs. 2O-2S, ¶0101) does not have to be formed penetrating through the entire metal gate stack that reduces significantly the etching loading for forming the “cut metal gate”.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method for forming the semiconductor structure of Pan by forming a cutting structure as taught by Chiang to have the method for forming the semiconductor structure, further comprising: forming a cutting structure over the dielectric wall, in order to provide an improved method of forming cut metal gate structure with reduced etching loading (without penetrating through the entire metal gate stack) (Chiang, ¶0095, ¶0101).
Regarding claim 21, Pan discloses the method for forming the semiconductor structure as claimed in claim 16. Further, Pan does not specifically disclose the method, further comprising: forming an etch stop layer over the gate structure; forming a dielectric layer on the etch stop layer; and forming a cutting structure through the etch stop layer and the dielectric layer, wherein the cutting structure is through a portion of the dielectric wall.
However, Chiang teaches forming a cutting structure (154) (Chiang, Figs. 2O-2S, ¶0013-¶0014, ¶0089-¶0101) over the dielectric wall (123’) to separate the metal gate stack (142) into multiple portions that are electrically isolated from each other, wherein a sacrificial layer (146) (Chiang, Figs. 2O-2S, ¶0089) including a combination of silicon carbide layer and silicon oxide layer is formed over the gate structure (142); and forming a cutting structure (154) through the sacrificial layer (146), wherein the cutting structure (154) is through a portion of the dielectric wall (123’) (Chiang, Figs. 2O-2S, ¶0095) to a small depth of 1 nm to about 25 nm.
In Chiang, the cutting structure (154) (Chiang, Figs. 2O-2S, ¶0101) does not have to be formed penetrating through the entire metal gate stack that reduces significantly the etching loading for forming the “cut metal gate”.
Further, Chiang teaches that silicon carbide is used as an etch stop layer (308) (Chiang, Fig. 3D, ¶0063-¶0066) and a dielectric layer including silicon oxide (310) is formed on the etch stop layer (308) to protect the structure during subsequent etching process.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method for forming the semiconductor structure of Pan by forming a cutting structure by using a sacrificial layer as taught by Chiang, wherein the sacrificial layer includes a combination of silicon carbide and silicon oxide material layers as an etch stop layer and a protective dielectric layer to have the method for forming the semiconductor structure, further comprising: forming an etch stop layer over the gate structure; forming a dielectric layer on the etch stop layer; and forming a cutting structure through the etch stop layer and the dielectric layer, wherein the cutting structure is through a portion of the dielectric wall, in order to provide an improved method of forming cut metal gate structure with reduced etching loading (without penetrating through the entire metal gate stack) (Chiang, ¶0063-¶0066, ¶0089-¶0091, ¶0095, ¶0101).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0366908 to Pan in view of Chiang (US 2021/0265508) as applied to claim 18, and further in view of Lin et al. (US Patent No. 11,251,284, hereinafter Lin).
Regarding claim 19, Pan in view of Chiang discloses the method for forming the semiconductor structure as claimed in claim 18. Further, Pan does not specifically disclose the method, further comprising: forming a gate dielectric layer lining on a sidewall surface of the cutting structure.
However, Lin teaches forming the gate cut structure (Lin, Fig. 12B, Col. 10, lines 41-67; Col. 11, lines 1-12), wherein a gate dielectric layer (62) lining on a sidewall surface of the cutting structure (52) having a specific shape, to provide gate replacement stack without voids.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method for forming the semiconductor structure of Pan/Chiang by forming a cutting structure covered with the gate dielectric layer of the gate replacement stack as taught by Lin to have the method for forming the semiconductor structure, further comprising: forming a gate dielectric layer lining on a sidewall surface of the cutting structure, in order to provide an improved method of forming gate replacement stack without voids (Lin, Col 11, lines 2-12).
Claims 26-27 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0366908 to Pan in view of Chen et al. (US 2019/0393324, hereinafter Chen).
With respect to claim 26, Pan discloses a method for forming a semiconductor structure (e.g., fabrication process for a semiconductor structure including a dielectric fin for isolating metal gates, see the annotated Figs. 12, 19, 23, and 24 below) (Pan, Figs. 2-26, 27A-27E, ¶0010-¶0050), comprising:
forming a first fin structure (e.g., a first fin 218) (Pan, Fig. 2, ¶0013-¶0017) and a second fin structure (e.g., a second fin 218) along a first direction (e.g., the x-direction) over a substrate (201), respectively, wherein the first fin structure (e.g., the first fin 218) comprises first semiconductor material layers (210) and second semiconductor material layers (215) alternately stacked, and the second fin structure (e.g., the second fin 218) comprises the first semiconductor material layers (210) and the second semiconductor material layers (215) alternately stacked;
forming an isolation material (230/232/233/234) (Pan, Figs. 4-11, ¶0019-¶0024) adjacent to the first fin structure (e.g., the first fin 218) and the second fin structure (e.g., the second fin 218);
forming a first dummy gate structure (240) (Pan, Fig. 12, ¶0025) along a second direction (e.g., the y-direction) over the isolation material (230/232/233/234), the first fin structure (e.g., the first fin 218) and the second fin structure (e.g., the second fin 218);
removing the first dummy gate structure (e.g., recessing dummy gate electrode 245) (Pan, Fig. 18, ¶0031);
after removing the first dummy gate structure (e.g., removing a portion of the first dummy gate structure 240), forming a photoresist layer (e.g., etch mask 241 including patterned photosensitive resist) (Pan, Fig. 19, ¶0032) on the isolation material (230/232/233/234), wherein the photoresist layer (241) is between the first fin structure (e.g., the first fin 218) and the second fin structure (e.g., the second fin 218);
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removing a first portion of the isolation material (e.g., etching the second dielectric fin 229-2 to remove a portion 234) (Pan, Fig. 20, ¶0033), such that a second portion of the isolation material covered by photoresist (241) is left to form a dielectric wall (e.g., the dielectric fin 229-1 including isolation material 230/232/233/234) between the first fin structure (e.g., the first fin 218) and the second fin structure (e.g., the second fin 218);
removing the first semiconductor material layers (210) (Pan, Fig. 22, ¶0035) to form a plurality of nanostructures (215); and
forming a gate structure (349/350) (Pan, Fig. 24, ¶0039-¶0040) on the dielectric wall (229-1).
Further, Pan does not specifically disclose removing the first dummy gate structure to expose the first fin structure and the second fin structure; after removing the first dummy gate structure, forming a photoresist layer on the isolation material.
However, Chen teaches forming FinFET device comprising removing the first dummy gate structure (30) (Chen, Figs. 6A-6B, ¶0025) to expose the first fin structure (24) (Chen, Fig. 8C) and the second fin structure (24) and to form replacement gate stack (60) (Chen, Figs. 6A-6B, ¶0026), wherein gate dielectric layer (54) is formed on the exposed surfaces of the fins (24’); after removing the first dummy gate structure, forming a photoresist layer (63) (Chen, Figs. 9A-9C, ¶0032) on the isolation material (22), and removing a portion of the isolation material (22, the etching is stopped at an intermediate level between a top surface and a bottom surface of the isolation region 22) (Chen, Figs. 10A-10C, ¶0035), to form dielectric isolation region (76) (Chen, Figs. 11A-11C, ¶0038) by using cut-metal-gate processes for tightly spaced circuits (Chen, ¶0010, ¶0051).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method for forming the semiconductor structure of Pan by forming a photoresist layer on the isolation material after removing the dummy gate structure as taught by Chen to have the method for forming the semiconductor structure comprising: removing the first dummy gate structure to expose the first fin structure and the second fin structure; after removing the first dummy gate structure, forming a photoresist layer on the isolation material, in order to form dielectric isolation region by using cut-metal-gate processes for tightly spaced circuits (Chen, ¶0010, ¶0051).
Regarding claim 27, Pan in view of Chen discloses the method for forming the semiconductor structure as claimed in claim 26. Further, Pan discloses the method, further comprising: after removing the first dummy gate structure, removing the first portion of the isolation material (e.g., trimming process to remove portions of the isolation material 232/233/234) (Pan, Fig. 23, ¶0036-¶0038) to form an isolation structure (e.g., dielectric fin 229-2 including isolation material 230/232/233), wherein a top surface of the isolation structure (229-2) is lower than a top surface of the dielectric wall (229-1, including isolation material 230/232/233/234).
Regarding claim 30, Pan in view of Chen discloses the method for forming the semiconductor structure as claimed in claim 26. Further, Pan discloses the method, further comprising: forming a refill material (e.g., low-k dielectric fill material 233) (Pan, Fig. 8, ¶0022) on the isolation material (e.g., 230/232, including high-k dielectric material 232) (Pan, Fig. 8, ¶0021), wherein the refill material (233) and the isolation material (230/232) are made of different materials.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0366908 to Pan in view of Chen (US 2019/0393324) as applied to claim 27, in view of Chiang (US 2021/0265508).
Regarding claim 28, Pan in view of Chen discloses the method for forming the semiconductor structure as claimed in claim 27. Further, Pan does not specifically disclose the method, further comprising: forming a cutting structure over the dielectric wall, wherein a portion of the cutting structure extends into the dielectric wall.
However, Chiang teaches forming a cutting structure (154) (Chiang, Figs. 2O-2S, ¶0013-¶0014, ¶0089-¶0101) over the dielectric wall (123’) to separate the metal gate stack (142) into multiple portions that are electrically isolated from each other, wherein the cutting structure (154) extends through a portion of the dielectric wall (123’) (Chiang, Figs. 2O-2S, ¶0095) to a small depth of 1 nm to about 25 nm.
In Chiang, the cutting structure (154) (Chiang, Figs. 2O-2S, ¶0101) does not have to be formed penetrating through the entire metal gate stack that reduces significantly the etching loading for forming the “cut metal gate”.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method for forming the semiconductor structure of Pan/Chen by forming a cutting structure over the dielectric wall as taught by Chiang to have the method for forming the semiconductor structure, further comprising: forming a cutting structure over the dielectric wall, wherein a portion of the cutting structure extends into the dielectric wall, in order to provide an improved method of forming cut metal gate structure with reduced etching loading (without penetrating through the entire metal gate stack) (Chiang, ¶0063-¶0066, ¶0089-¶0091, ¶0095, ¶0101).
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0366908 to Pan in view of Chen (US 2019/0393324) as applied to claim 26, in view of Chen et al. (US 2021/0343600, hereinafter Chen’600).
Regarding claim 29, Pan in view of Chen discloses the method for forming the semiconductor structure as claimed in claim 26. Further, Pan does not specifically disclose the method, wherein a top surface of the dielectric wall is leveled with a topmost surface of the second semiconductor material layers.
However, Chen’600 teaches forming multi-gate device including gate-all-around device (Chen’600, Fig. 29C, ¶0003, ¶0008, ¶0010-¶0012, ¶0014-¶0052) comprising a dielectric wall (e.g., dielectric fin 280B) (Chen’600, Fig. 29C, ¶0044) between the first fin structure of the n-type transistor region (202A) and the second fin structure of the p-type transistor region (202B), wherein the first semiconductor material layers (215) (Chen’600, Fig. 29C, ¶0047-¶0048) are removed in the channel region with minimal to no etching of the second semiconductor layers (220) such that the second semiconductor layers (220) are released and a top surface of the dielectric wall (280B) is leveled with a topmost surface of the topmost channel layer (220’) of the semiconductor material layers (220), to form multi-gate device with improved gate control to increase gate-channel coupling and reduce short-channel effects (Chen’600, ¶0003, ¶0008, ¶0010-¶0012, ¶0048).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method for forming the semiconductor structure of Pan/Chen by forming a multi-gate device including gate-all-around device including the dielectric fin in the channel region as taught by Chen’600 to have the method for forming the semiconductor structure, wherein a top surface of the dielectric wall is leveled with a topmost surface of the second semiconductor material layers, in order to provide a multi-gate device with improved gate control to increase gate-channel coupling and reduce short-channel effects (Chen’600, ¶0003, ¶0008, ¶0010-¶0012, ¶0048).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891