DETAILED ACTION
This correspondence is in response to the communications received November 4, 2025. Claims 1-9 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election without traverse of Group I claims 1-9 in the reply filed on October 1, 2025 is acknowledged. Claims 10-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II method claims, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on October 1, 2025.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Fig. 1, a display device comprising:
a light blocking layer (BML, ¶ 0052) positioned on a substrate (SUB) and including:
a first portion (B1, ¶ 0053); and
a second portion (B2, ¶ 0053) having a thickness greater than a thickness of the first portion (see above drawing);
a buffer layer (BUF, ¶ 0054) positioned above the light blocking layer (over BML);
a semiconductor layer (ACT, ¶ 0057) positioned over the buffer layer (over BUF) and including:
a source region (SA);
a channel region (CA); and
a drain region (DA);
a gate insulating layer (GI) positioned over the semiconductor layer (over ACT);
a gate electrode (GE) positioned over the gate insulating layer (over GI);
an interlayer insulating layer (ILD) positioned over the gate electrode (over GE), and including:
a first opening (OP1) overlapping the second portion of the light blocking layer in a plan view (overlapping B2); and
a second opening (OP2) overlapping the source region of the semiconductor layer in a plan view (overlapping SA); and
a dummy gate electrode (DGE, ¶ 0064) positioned on a side surface of the first opening (DGE at OP1 sidewall region).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5 and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 11,751,439) in view of (KR 10208366 B1, hereinafter referred to as ‘366) in view of Guo et al. (US 2015/0348999) in view of Jeong et al. (US 2022/0173184).
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Regarding claim 1, the prior art of Kim discloses in Fig. 1, a display device comprising:
a light blocking layer (“light blocking layer 111,”, col. 6, lines 42) positioned on a substrate (“substrate 100, col. 6, line 38”) and including:
a first portion (portion of 111 under the TFT T1); and
a second portion (portion of 111 not under the TFT T1);
a buffer layer (“buffer layer 120”, col. 6, line 61) positioned above the light blocking layer (120 above 111);
a semiconductor layer (“semiconductor layers 150a”, col. 6, line 53) positioned over the buffer layer (150a over 120) and including:
a source region (155a, the label “source” is understood to merely signify that this region is a highly doped “source/drain” region, where drain and source are interchangeable. See discussion below.);
a channel region (“channel region 154a”, col. 7, line 29); and
a drain region (153a, the label “drain” is understood to merely signify that this region is a highly doped “source/drain” region, where drain and source are interchangeable. See discussion below.);
a gate insulating layer (“gate insulating pattern 144”, col. 7, line 39) positioned over the semiconductor layer (144 over portion 154a of 150a);
a gate electrode (“Gate electrodes 124a”, col. 7, line 44) positioned over the gate insulating layer (124a over 144);
an interlayer insulating layer (“intermediate film 160”, col. 7, lines 55-66, discuss the insulator materials used in the film 160) positioned over the gate electrode (160 over 124a ), and including:
a first opening overlapping the second portion of the light blocking layer in a plan view (OP1 over second region of 111 not under TFT T1); and
a second opening overlapping the source region of the semiconductor layer in a plan view (OP3 over first region of 111 under TFT T1, where OP3 is at the left most “source/drain region” 155a).
First, Kim fails to disclose the italicized portion of the following limitation,
“a light blocking layer … including:
a first portion; and
a second portion having a thickness greater than a thickness of the first portion”.
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The ‘366 reference discloses in Fig. 3j, a light blocking layer (317 including 217a and 217b, and 315, since all three films are light blocking metals, they function as “light blocking layers”) … including:
a first portion (“light blocking pattern 315”, last sentence, pg. 3, where 315 is made of copper, “the third copper pattern 221 is etched to form the light blocking pattern 315”, third paragraph on pg. 7); and
a second portion (“electrode 317”, last sentence, pg. 3, which includes 217a and 217b, hereinafter referred to as ‘SP’. Where materials for 217a and 217b are as follows, “copper pattern 217b and a first molybdenum pattern 217a”, first sentence, pg. 7) having a thickness greater than a thickness of the first portion (SP is thicker than 315). The purpose of having a thicker portion is for the reason of lowering the resistance of the electrical pathways, see sixth paragraph, pg. 8.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“a light blocking layer … including:
a first portion; and
a second portion having a thickness greater than a thickness of the first portion”, as disclosed by ‘366 reference in the system of Kim, for the purpose of lowering the resistance of the electrical pathways. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Kim fails to disclose that the left most TFT “source/drain region” is specifically a “source region” and that the right most TFT “source/drain region” is specifically a “drain region”.
Guo teaches in ¶ 0094, “In addition, although the embodiments of the present invention are described by only taking that the source is connected with the data line and the drain is electrically connected with the anode as an example, the person skilled in the art should understand that, since the source and the drain are exchangeable in structure and composition, the drain can be connected with the data line and the source can be electrically connected with the anode, which is an equivalent of the embodiments of the present invention.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the left most TFT “source/drain region” is specifically a “source region” and that the right most TFT “source/drain region” is specifically a “drain region”, as disclosed by Guo in the system of Kim, for the purpose of providing high concentrations regions to the thin film transistor so that it may function as the switching device necessary to electrically control and access the light emitting device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Third, Kim does not disclose the limitation of, “a dummy gate electrode positioned on a side surface of the first opening.”
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Jeong discloses in Fig. 13A, a dummy gate electrode (ML4, ¶ 0210. The term “gate electrode” is understood to be a label for the metal pattern formed in the second insulation layer above the target metal layer CE2. As the dummy electrode of the instant application is not used as a gate electrode, the label is understood to mean that the metal is of the same metallization level of the actual functioning gate electrode. So as the second insulation/metallization level ML4/116 above the target metal to be contacted CE2, would then be analogous to the gate metal level 124a of Fig. 1 of Kim) positioned on a side surface (“ML4-S”, ¶ 0210) of the first opening (CE2).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “a dummy gate electrode positioned on a side surface of the first opening.”, as disclosed by Jeong in the system of Kim et al., for the purpose of etch control so as to prevent unwanted lateral etching beyond a certain depth, which can improve the contact structure pattern integrity. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 5, the prior art of Kim disclose the display device of claim 1, and the ‘366 reference discloses in Fig. 3j, wherein the semiconductor layer (319, paragraph 7, pg. 4, as can be seen in Fig. 3h) overlaps the first portion of the light blocking layer (315) in a plan view (vertically).
Regarding claim 7, the prior art of Kim disclose the display device of claim 1, and ‘366 discloses in Fig. 3j, wherein the second portion of the light blocking layer (portion 317 including 217a, 217b) does not overlap the gate insulating layer or a dummy gate insulating layer in a plan view (noted second portion does not overlap the 320a, vertically).
Regarding claim 8, the prior art of Kim disclose the display device of claim 1, and the combination of references disclose,
further comprising:
a source electrode (Kim discloses in Fig. 1, portion of 191, contacting the 155a region, which is explained as a source in the rejection of claim 1) positioned on the interlayer insulating layer (on 160); and
a drain electrode (‘366 discloses in Fig. 3j, 323b) positioned on the interlayer insulating layer (equivalent layer being 305),
wherein the source electrode is in contact with the light blocking layer through the first opening, and in contact with the source region of the semiconductor layer through the second opening (‘366 discloses in Fig. 3j, opening allowing access to 317, connects also to equivalent source region 319b, by way of metal 323a).
Regarding claim 9, the prior art of Kim disclose the display device of claim 8, wherein the drain electrode is in contact with the drain region of the semiconductor layer through a third opening (‘366 in Fig. 3j, has 323b making contact with 319c).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 11,751,439) in view of (KR 10208366 B1, hereinafter referred to as ‘366) in view of Guo et al. (US 2015/0348999) in view of Jeong et al. (US 2022/0173184) in view of Baek et al. (US 2022/0085131).
Regarding claim 2, the prior art of Kim disclose the display device of claim 1, however Kim does not disclose,
“further comprising:
a dummy gate insulating layer positioned on a side surface of the second opening; and
a dummy gate electrode positioned on the side surface of the second opening.”
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Baek discloses in Fig. 4, further comprising:
a dummy gate insulating layer (“insulating pattern GI2”, ¶ 0070) positioned on a side surface of the second opening (opening over D1); and
a dummy gate electrode (EST1, ¶ 0098 disclosed that EST1 can be metallic) positioned on the side surface of the second opening (opening where via is over D1). It is noted that the terms “dummy gate insulating layer” and “dummy gate electrode” are understood to be labels for the sole reason that they are positioned at the metallization level of the actual functioning gates.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “a dummy gate electrode positioned on a side surface of the first opening.”, as disclosed by Jeong in the system of Kim et al., for the purpose of etch control so as to prevent unwanted lateral etching beyond a certain depth, which can improve the contact structure pattern integrity. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 3, the prior art of Kim disclose the display device of claim 2, and Jeong discloses in Fig. 4, wherein the interlayer insulating layer (analogous layer being VIA) further includes a third opening (CNT3 and CNT4) overlapping the drain region (S1, see discussion of interchangeability with source region in the rejection of claim 1) of the semiconductor layer (ACT1) in a plan view (vertically oriented), and the display device further comprises:
a dummy gate insulating layer (“insulating pattern GI3”, ¶ 0070) positioned on a side surface of the third opening (CNT3 and CNT4); and
a dummy gate electrode (EST2, ¶ 0100, where EST2 is disclosed to be optionally made of metal) positioned on the side surface of the third opening (on side surface of CNT3 and CNT4). It is noted that the terms “dummy gate insulating layer” and “dummy gate electrode” are understood to be labels for the sole reason that they are positioned at the metallization level of the actual functioning gates.
Regarding claim 4, the prior art of Kim disclose the display device of claim 3, and Jeong discloses in Fig. 4, wherein the dummy gate electrodes (EST2) and the gate electrode (GAT1) are positioned on a same layer (as shown positioned at same metallization level), and the dummy gate insulating layers (GI3) and the gate insulating layer (GI1) are positioned on a same layer (as shown positioned at same metallization level).
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
“6. The display device of claim 1, wherein an uppermost surface of the buffer layer positioned over the second portion of the light blocking layer is positioned further from the substrate than an uppermost surface of the semiconductor layer.”
Lee et al. (US 12,075,665) discloses a similar arrangement but does not show in Fig. 3B, wherein the equivalent buffer layer (IL1) is over the top most portion of the semiconductor layer (top most portion of ACT1).
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Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893