Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of group I in the reply filed on 10/22/25 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-6, 21-22, and 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fagot et al., US 2019/0057981.
Fagot shows the invention as claimed including a method for manufacturing a high-voltage transistor 6 in and on a high-voltage region of a silicon-on-insulator type bulk (for example, 8, 10, 12) including a semiconductor film having a first thickness, electrically insulated from a carrier bulk by a buried dielectric layer 10, the method comprising:
Selectively epitaxially growing the semiconductor film in the high-voltage region to a second thickness (12,22) that is greater than the first thickness 12, the semiconductor film remaining at the first thickness in a region outside the high-voltage region 4 (see figs. 1a-1h and paragraphs 0032-0045).
Regarding dependent claim 2, note that Fagot et al. discloses epitaxially growing the carrier bulk in a localized monolithic region 2 of the silicon-on-insulator type bulk, wherein the epitaxially growing of the semiconductor film 22 in the high-voltage region is performed simultaneously with the epitaxially growing of the carrier bulk in the localized monolithic region (see, for example, fig. 1G).
As to dependent claim 5, note that Fagot discloses wherein epitaxially growing the semiconductor film comprises forming a dedicated hard mask 20 comprising an opening uncovering the semiconductor film in the high-voltage region, prior to the epitaxially growing of the semiconductor film in the high-voltage region (see, for example, figs. 1D-1F).
Concerning dependent claim 6, note that Fagot discloses forming a gate region of the high-voltage transistor on the semiconductor film having the second thickness of the high-voltage region; and forming conduction regions of the high-voltage transistor in the semiconductor film having the second thickness of the high-voltage region (note that inherently the high voltage region contains high voltage transistors which comprise source/drain conduction regions).
Regarding independent claim 21, Fargot discloses a method of manufacturing a semiconductor device in a silicon-on-insulator substrate that includes a semiconductor film electrically insulated from a carrier bulk by a buried dielectric layer 10, the method comprising:
Forming a low-voltage transistor at a surface of the semiconductor film in a low-voltage region 4 of the silicon-on-insulator substrate, the semiconductor film in the low-voltage region 12 having a first thickness; and forming a high-voltage transistor at the surface of the semiconductor film in a high-voltage region 6 of the silicon-on-insulator substrate, the semiconductor film in the high-voltage region having a second thickness (12,22) that is greater than the first thickness (see figs. 1A-1H and paragraphs 0033-0045).
With respect to dependent claim 22, note that Fargot discloses further comprising a further transistor laterally spaced from the low-voltage transistor and the high-voltage transistor and formed in region 2, the further transistor formed in a region of semiconductor without any underlying buried dielectric (see fig. 1H).
Concerning dependent claim 24, note that Fargot also discloses wherein forming the high-voltage transistor comprises forming a gate region over the semiconductor film in the high-voltage region and forming conduction regions in the semiconductor film in the high-voltage region (note that inherently the high voltage region contains high voltage transistors which comprise source/drain conduction regions).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 8-9 and 27-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fagot et al., US 2019/0057981.
Fagot et al. is applied as claimed but fails to expressly disclose wherein the second thickness is at least 13 nm greater than the first thickness and the claimed first and second thicknesses. However, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to determine through routine experimentation the optimum values of the first and second thicknesses depending upon a variety of factors including the particular voltage resistance of the transistors and such limitation would not lend patentability absent a showing of unexpected results.
Claim(s) 7 and 25-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fagot et al., US 2019/0057981 in view of Bryant et al., US 2009/0096026.
Fagot et al. shows the invention substantially as claimed but does not expressly disclose wherein the high voltage transistor is part of a fully depleted transistor. Bryant et al. discloses wherein the high voltage transistor is part of a fully depleted transistor (see abstract). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the method of Fagot et al. so as to configure the high voltage transistor to be a fully depleted transistor because in such a way a high voltage transistor with a large breakdown voltage can be provided.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fagot et al., US 2019/0057981 in view of Tigelaar, US 2006/0216898.
Fagot et al. is applied as above but does not expressly disclose wherein forming a further transistor comprises forming a bipolar junction transistor. Tigelaar discloses the formation of a fet based high voltage and low voltage transistor and the formation of additional bipolar transistors (see paragraph 0010). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the process of Fagot et al. so as to fabricate bipolar transistors because of many of their well-known benefits including rapid switching.
Allowable Subject Matter
Claims 3-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art, either singly or in combination, particularly Fagot et al., US 2019/0057981, fails to anticipate or render obvious, the claimed invention having the following limitations, in combination with the remaining claimed limitations: oxidizing the semiconductor film in the localized monolithic region at the first opening; and selectively etching to remove the oxidized semiconductor film and the buried dielectric layer in the localized monolithic region, as required by dependent claim 3.
Claims 10-12 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art, either singly or in combination, particularly Fagot et al., US 2019/0057981, fails to anticipate or render obvious, the claimed invention having the following limitations, in combination with the remaining claimed limitations: oxidizing the semiconductor film in the localized monolithic region; selectively etching to remove the oxidized semiconductor film and the buried dielectric layer in the localized monolithic region, and epitaxially growing the semiconductor film to a second thickness at the second opening in the high-voltage region, such that the second thickness is at least 13nm greater than the first thickness, as required by independent claim 10.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
February 10, 2026