DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I which corresponds to claims 1-15 in the reply filed on 11/24/2025 is acknowledged. Claims 16-20 are withdrawn from further consideration, pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Inventions or Species. Additionally, Claims 21-25 are added as new claims.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/17/2024 and 7/23/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Specifically, claim 11 recites that a “the power tap structure electrically coupling a front side power rail … to a further back side power rail “ but claim 11 only previously introduces “a plurality of back side power rails configured to carry a second power supply voltage different from the first power supply voltage”. And does not clearly establish whether the “further back side power rail” is (i) one of the recited back side power rails (and thus at the second power supply voltage) or (II) a different backside power rail configured to carry the first power supply voltage (as later recited in dependent claim 12). Accordingly, the scope of claim 11 is unclear and indefinite.
Claims 12-15 depends from claim 11 so they are rejected for the same reason.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 4-5 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Liebmann et. al. (US-20200135718-A1, hereinafter Liebmann),
Regarding Claim 1.
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Liebmann teaches in Fig.5 and in related text An integrated circuit (IC) device, comprising:
a complementary field-effect transistor (CFET) device, the CFET device comprising a local interconnect;
a power rail (#503a/#503b) at a first side of the CFET device; and
a conductor (#513) at a second side of the CFET device,
wherein
the first side is one of a front side or a back side of the CFET device,
the second side is the other of the front side or the back side of the CFET device, and
the local interconnect (#525/#527/#529/#531/#533/#535) of the CFET device electrically couples the power rail (#503a/#503b) to the conductor (#513). (See [0046-0050])
Regarding Claim 4.
Liebmann teaches The IC device of claim 1,
Liebmann also teaches wherein
the power rail, the conductor and the local interconnect (#525/#533/#529/#533) are elongated along a first direction. (N/S direction)
Regarding Claim 5.
Liebmann teaches The IC device of claim 1,
Liebmann also teaches wherein
the CFET device comprises a gate (Fig.2 #129 /Fig.6-8 #557 gate region) arranged in a plane that intersects the local interconnect (#525/#527/#529/#531/#533 /#535) , and
the gate (#557) is electrically isolated from the local interconnect (See [0055-0057]).
Claims 11-14 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Liebmann798 et. al. (US-20200135718-A1, hereinafter Liebmann798),
Regarding Claim 11.
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Liebmann798 teaches An integrated circuit (IC) device, comprising:
a plurality of front side power rails (Fig.1 #110 UML power deliver network) configured to carry a first power supply voltage (#Vss or #Vdd);
a plurality of back side power rails (Fig.1 #190 BPR power delivery network) configured to carry a second power supply voltage (#Vss or #Vdd) different from the first power supply voltage;
at least one functional circuit (Fig.1 Standard Cell Rows) arranged between the plurality of front side power rails and the plurality of back side power rails in a thickness direction of the IC device, the at least one functional circuit electrically coupled to and powered by one or more of the plurality of front side power rails and one or more of the plurality of back side power rails; and
a power tap structure(Fig.2 #221/#222/#223 power tap cell) in the at least one functional circuit, the power tap structure electrically coupling a front side power rail among the plurality of front side power rails to a further back side power rail. (See Liebmann798 Fig.1, Fig.2 [0029-0043] [0048-0058])
Regarding Claim 12.
Liebmann798 teaches The IC device of claim 11,
Liebmann798 further teaches further comprising:
a plurality of further back side power rails including the further back side power rail, the plurality of further back side power rails configured to carry the first power supply voltage. (#190 connected to both Vss and Vdd)
Regarding Claim 13.
Liebmann798 teaches The IC device of claim 12,
Liebmann798 further teaches wherein
the plurality of further back side power rails and the plurality of back side power rails are alternatingly arranged in a same metal layer. (#190 Vss and Vdd are arranged alternatives in the same layer)
Regarding Claim 14.
Liebmann798 teaches The IC device of claim 11,
Liebmann798 further teaches wherein
the at least one functional circuit (stand cells row) comprises a plurality of complementary field-effect transistor (CFET) devices, and
the power tap structure comprises a local interconnect (#250/#250 MLI rails) of a CFET device among the plurality of CFET devices. ([0043-0050])
Claims 21-23 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Liebmann et. al. (US-20200135718-A1, hereinafter Liebmann)
Regarding Claim 21.
Liebmann teaches in Fig 5-6 and in related text An integrated circuit (IC) device, comprising:
at least one first complementary field-effect transistor (CFET) device (transistor including #505N/#505P), comprising:
a first active region (Fig.6 SD region #505N/#505P) extending along a first direction (S/N direction);
and at least one first gate (Fig.6 #557) extending, across the first active region, along a second direction (thickness direction) transverse to the first direction;
at least one second CFET device (transistor including #507N/#507P), comprising:
a second active region (Fig.6 SD region #507N/#507P) spaced from the first active region (SD region #505N/#5075) along the second direction (thickness direction);
and at least one second gate #567) extending, across the second active region (Fig.6 SD region #507N/#507P), along the second direction (thickness direction);
and a local interconnect (#515/#517/#519/#521) common to both the at least one first CFET device (transistor including #505N/#505P) and the at least one second CFET device (transistor including #507N/#507P),
wherein the local interconnect extends along the first direction (S/N direction) and across both the at least one first gate (#557) and the at least one second gate (#567). (See [0046-0054])
Regarding Claim 22.
Liebmann teaches The IC device of claim 21, wherein along the second direction, the local interconnect (#515/#517/#519/#521) is between the at least one first gate (#557) and the at least one second gate. (#567)
Regarding Claim 23.
Liebmann teaches The IC device of claim 21, wherein the at least one first gate (#557) comprises multiple first gates (gates for #505P and for #505N), the at least one second gate (#567) comprises multiple second gates (gates for #507P and for #507N), and the local interconnect (#515/#517/#519/#521) extends along the first direction (S/N direction) and across both the multiple first gates and the multiple second gates.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Liebmann et. al. (US-20200135718-A1, hereinafter Liebmann)
Regarding Claim 2.
Liebmann teaches The IC device of claim 1, further comprising:
Liebmann disclose further comprising: a first vertical connection (#529) between and electrically coupling the local interconnect (#531) to the power rail (#503a); and
a second vertical connection (#533) between and electrically coupling the local interconnect (#527) to the conductor (#513b). It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to use vias for both connections, as vias are the standard method for electrically coupling conductors at different vertical levels in semiconductor fabrication.
Regarding Claim 3.
Liebmann teaches The IC device of claim 2,
Liebmann does not explicitly disclose further comprising:
a contact structure between and electrically coupling the local interconnect to the second via.
However, Liebmann discloses contact structure between different conductive layers//wiring and using vertical interconnect as a contact structure [0036-0038], [0042-0043] [0056-0057]). It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to use a contact structure between and electrically coupling the local interconnect, as contact structures are the standard method for connecting different conductive layers/wirings in semiconductor fabrication and it provide predictable benefits and results in the design.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Liebmann et. al. (US-20200135718-A1, hereinafter Liebmann) and in further view of Xie et. al. (US-20230042567A1, hereinafter Xie)
Regarding Claim 6.
Liebmann teaches The IC device of claim 5, further comprising:
Liebmann does not explicitly disclose low-k dielectric layer between and electrically isolating the gate and the local interconnect.
However, Xie teaches in Fig.6 that a low-k dielectric layer (#24) between and electrically isolating the gate (#36) and the local interconnect (#40 interconnect passthrough structure).
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Liebmann with the teachings of Xie, as identified above, because this modification yields the predictable result of further reducing parasitic capacitance while maintaining electrical isolation.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Liebmann798 et. al. (US-20200135718-A1, hereinafter Liebmann798),
Regarding Claim 15.
Liebmann798 teaches The IC device of claim 11,
Liebmann798 further teaches wherein
the at least one functional circuit (stand cells row) comprises a plurality of complementary field-effect transistor (CFET) devices, and
Liebmann798 also discloses the power tap local interconnect as being within dedicated power tap cells rathe than explicitly “between two immediately adjacent CFET devices. However, it would have been obvious to one of ordination skill in the art to position the power tap local interconnect between two immediately adjacent CFET devices, because this is a predictable layout variation that achieves the same power delivery function with reduced area consumption, and area efficiency is area efficiency is a fundamental objective in semiconductor design, that would motivate this routine design choice.
Allowable Subject Matter
Claims 7-10 and 24-25 are objected to as being dependent upon a rejected base claim (claim 4), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 7 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the device, wherein …the plurality of front side conductive patterns comprises: the power rail which is a front side power rail, and a first front side conductive pattern immediately adjacent to the front side power rail in a second direction transverse to the first direction, and the first front side conductive pattern overlaps the gate in a thickness direction transverse to both the first direction and the second direction. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 8-10 contain allowable subject matter because they depend from claim 7.
Claim 24 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the device, wherein … a dielectric layer between and electrically isolating the local interconnect from each of the at least one first gate and the at least one second gate. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 25 contains allowable subject matter because they depend from claim 24
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA W KAO whose telephone number is (703)756-4797. The examiner can normally be reached Monday-Friday 9am-5pm Pacific Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SOPHIA W KAO/Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817