DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, 5, 9, 10, and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Baek (U.S. Pub #2020/0373293).
With respect to claim 1, Baek teaches a method of manufacturing an integrated circuit (IC) device, the method comprising:
forming a metal oxide semiconductor (MOS) transistor comprising a first gate (Fig. 10, 292) and first and second source/drain (S/D) regions (Fig. 10, 251/252; Paragraph 99), the first and second S/D regions having a first doping type (p-type) and being formed in a substrate region having a second doping type (Fig. 10, 215; n-type; Paragraph 123) different from the first doping type;
forming a guard ring structure (Fig. 10-11, ring region of 215 encircling center region) surrounding the MOS transistor, the guard ring structure comprising a second gate (Fig. 10, 290) and first and second heavily doped regions (Fig. 10, 281/282 and Paragraph 102), the first and second heavily doped regions being formed in the substrate region and having the second doping type (Paragraph 102); and
constructing a first electrical connection (Fig. 10, Gate connections) between the first and second gates.
With respect to claim 2, Baek teaches that each of the forming the first and second S/D regions in the substrate region and the forming the first and second heavily doped regions in the substrate region comprises the substrate region being an n-well (Fig. 10, 215 and Paragraph 123).
With respect to claim 4, Baek teaches constructing a second electrical connection (Fig. 10, Drain connection extends to each drain region and Source connection extends to each source region) between each of the first and second S/D regions and each of the first and second heavily doped regions.
With respect to claim 5, Baek teaches that the forming the guard structure comprises forming the second gate (Fig. 10, 192) between the first and second heavily doped regions (Fig. 10, 181/182).
With respect to claim 6, Baek teaches that the forming the MOS transistor comprises forming a plurality of MOS transistors comprising the MOS transistor (Fig. 11, MOS transistors corresponding to gates 293), and
the forming the guard ring structure (Fig. 11, 215) surrounding the MOS transistor comprises forming the guard ring structure surrounding the plurality of MOS transistors.
With respect to claim 9, Baek teaches a method of manufacturing an integrated circuit (IC) device, the method comprising:
forming a metal oxide semiconductor (MOS) transistor comprising a first gate (Fig. 10, 292) and first and second source/drain (S/D) regions (Fig. 10, 251/252; Paragraph 99), the first and second S/D regions having a first doping type (p-type) and being formed in a substrate region having a second doping type (Fig. 10, 215; n-type; Paragraph 123) different from the first doping type;
forming a guard ring structure (Fig. 10-11, ring region of 215 encircling center region) surrounding the MOS transistor, the guard ring structure comprising a second gate (Fig. 10, 290) and first and second heavily doped regions (Fig. 10, 281/282 and Paragraph 102), the first and second heavily doped regions being formed in the substrate region and having the second doping type (Paragraph 102); and
constructing a first electrical connection (Fig. 10, Gate connections) between the first and second gates;
constructing a second electrical connection between each of the first and second S/D regions (Fig. 10, Source connections and Drain connections) and each of the first and second heavily doped regions.
With respect to claim 10, Baek teaches that the forming the MOS transistor comprises forming a p-type MOS transistor (Paragraph 122) in the substrate region being an n-well (Fig. 10, 215 and Paragraph 123).
With respect to claim 14, Baek teaches that the forming the MOS transistor comprises forming a plurality of MOS transistors comprising the MOS transistor (Fig. 11, MOS transistors corresponding to gates 293),
the forming the guard ring structure (Fig. 11, 215) surrounding the MOS transistor comprises forming the guard ring structure surrounding the plurality of MOS transistors,
the constructing the first electrical connection comprises constructing the first electrical connection between corresponding first gates of each MOS transistor of the plurality of MOS transistors (Fig. 10, the first electrical connection Gate extends to each gate 292), and the
constructing the second electrical connection comprises constructing the second electrical connection between corresponding first and second S/D regions of each MOS transistor of the plurality of MOS transistors (Fig. 10, the second electrical connection Source includes connections to each S/D region 261/262 between the gates 292).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Baek.
With respect to claims 3 and 11, Baek teaches that
the forming the guard ring structure comprises forming the gate (Fig. 10, 290) between the first and second heavily doped regions (Fig. 10 281/282), and the constructing the first electrical connection between the first and second gates comprises constructing the first electrical connection between the first gate and each gate of the plurality of gates (Fig. 10, the connection Gate extends to each gate).
Baek Fig.10 does not teach that the second gate is one gate of a plurality of gates of the guard ring structure,
forming each gate of the plurality of gates between the first and second heavily doped regions.
Fig. 14 of Baek teach that the second gate is one gate of a plurality of gates (Fig. 14, 190 and 290) of the guard ring structure,
forming each gate of the plurality of gates between the first and second heavily doped regions.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a plurality of gates in the guard ring region as taught by Fig. 14 of Baek in order to combine PMOS and NMOS devices within the guard ring (Paragraph 132).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Baek, in view of Tan (U.S. Patent #8492873).
With respect to claim 7, Baek teaches heavily doped regions, but does not teach forming first and second heavily doped regions comprises forming each of the first and second heavily doped regions having a doping concentration level of about 1*1016 per cubic centimeter cm-3 or greater.
Tan teaches that forming first and second heavily doped regions comprises forming each of the first and second heavily doped regions having a doping concentration level of about 1*1016 per cubic centimeter cm-3 or greater (Col 4 Ln 30-31).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to dope the region of Baek to a level of about 1*1016 per cubic centimeter cm-3 or greater as taught by Tan in order to achieve the predictable result of providing a heavily doped region.
Claim 8, 12, 15, 16, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Baek, in view of He et al (U.S. Patent #9793345).
With respect claim 8, Baek teaches that the forming the MOS transistor and the guard ring structure comprises forming the first and second gates aligned along a first direction (Fig. 10, laterally across the figure),
but does not teach that the constructing the first electrical connection comprises forming a metal segment extending in the first direction.
He teaches making a connection to a doped region by constructing a via on the doped region, and constructing a metal segment on the via.
It would have been obvious to one of ordinary skill in the art at the time the inveiotn was effectively filed to construct a metal via and metal segment on each of the corresponding doped region of Baek as taught by He in order to achieve the predictable result of making the Source and Drain electrical connections.
With respect to claim 12, Baek teaches that the forming the MOS transistor and the guard ring structure comprises forming the first and second gates aligned along a first direction (Figs. 10-11, left to right), and
each of the first electrical connection and the second electrical connection comprises extending in the first direction.
Baek does not teach that forming the first and second connections comprises forming a metal segment extending in the first direction.
He teaches making electrical connections by constructing extending metal segments (Fig. 8, 40,15b).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to form the first and second extending connection of Baek by forming the first and second connections comprises forming a metal segment extending in the first direction as taught by He in order to achieve the predictable of making connections between regions of the device.
With respect to claim 15, Baek teaches a method of manufacturing an integrated circuit (IC) device, the method comprising:
forming a metal oxide semiconductor (MOS) transistor comprising a first gate (Fig. 10, 292) and first and second source/drain (S/D) regions (Fig. 10, 251/252; Paragraph 99), the first and second S/D regions having a first doping type (p-type) and being formed in a substrate region having a second doping type (Fig. 10, 215; n-type; Paragraph 123) different from the first doping type;
forming a guard ring structure (Fig. 10-11, ring region of 215 encircling center region) surrounding the MOS transistor, the guard ring structure comprising a second gate (Fig. 10, 290) and first and second heavily doped regions (Fig. 10, 281/282 and Paragraph 102), the first and second heavily doped regions being formed in the substrate region and having the second doping type (Paragraph 102);
Baek does not teach
constructing a first via on the first gate; constructing a second via on the second gate; and constructing a first metal segment on each of the first and second vias.
He teaches making connections to gates, wherein the gates are connected together, comprising
constructing a first via (Fig. 8, 32b) on a first gate (Fig. 8, 32b); constructing a second via on a second gate; and constructing a first metal segment (Fig. 8, 40,15b) on each of the first and second vias.
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to construct vias and metal segments over the gates of Baek as taught by He in order to achieve the predictable result of making electrical connections to the first and second gates.
With respect to claim 16, Baek teach forming the second gate (Fig. 10, 291) between the first and second heavily doped regions (Fig. 10, 281/282).
With respect to claim 18, Baek does not teach constructing a third via on the first S/D region; constructing a fourth via on the second S/D region; constructing a fifth via on the first heavily doped region; constructing a sixth via on the second heavily doped region; and constructing a second metal segment on each of the third through sixth vias.
Baek does teaches that there is a connection to each of the S/D region and heavily doped regions.
He teaches making a connection to a doped region by constructing a via on the doped region, and constructing a metal segment on the via.
It would have been obvious to one of ordinary skill in the art at the time the inveiotn was effectively filed to construct a metal via and metal segment on each of the corresponding doped region of Baek as taught by He in order to achieve the predictable result of making the Source and Drain electrical connections.
With respect to claim 19, Baek teaches that the Drain connection being formed by the second metal segment extends from the left outer portion 182 to the right outer portion 182, hence the combination of Baek and He teaches constructing the second metal segment comprises constructing the second metal segment overlying each of the first and second gates.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Baek and He, in view of Tan (U.S. Patent #8492873).
With respect to claim 20, Baek teaches heavily doped regions, but does not teach forming first and second heavily doped regions comprises forming each of the first and second heavily doped regions having a doping concentration level of about 1*1016 per cubic centimeter cm-3 or greater.
Tan teaches that forming first and second heavily doped regions comprises forming each of the first and second heavily doped regions having a doping concentration level of about 1*1016 per cubic centimeter cm-3 or greater (Col 4 Ln 30-31).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to dope the region of Baek to a level of about 1*1016 per cubic centimeter cm-3 or greater as taught by Tan in order to achieve the predictable result of providing a heavily doped region.
Allowable Subject Matter
Claims 13 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN P SANDVIK whose telephone number is (571)272-8446. The examiner can normally be reached M-F: 10-6.
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/BENJAMIN P SANDVIK/Primary Examiner, Art Unit 2812