DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 7-9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Otake et al., US Pub. No. 2023/0420517 A1.
Re claim 1, Otake et al. disclose a semiconductor device, comprising: a substrate 2 (e.g., fig. 2E or fig. 25); a buffer layer 3 (e.g., fig. 2E or fig. 25) located on the substrate; a channel layer 4 (e.g., fig. 2E or fig. 25) located on the buffer layer; a barrier layer 5/62(62A/62B)/63(63A/63B) (fig. 2E, e.g., the combination of element 5 and a lower portion of element 6, see below figure) located on the channel layer; and a gate structure 6/7/73/74 (e.g., an upper portion of element 6 with elements 7/73/74, fig. 2E) disposed on the barrier layer, wherein the gate structure comprises: a gate layer 6 (e.g., an upper portion of element 6 fig. 2E); a gate electrode layer 7 (e.g., fig. 2E) partially covering the gate layer 6; a first protection pattern layer 73 (e.g., fig. 2E) completely covering a first top surface of the gate electrode layer 7; and second protection spacers 74 covering first side surfaces of the gate electrode layer 7, second side surfaces of the first protection pattern layer 73 (e.g., fig. 2E), and a portion of the gate layer 6 not covered by the gate electrode layer 7 (e.g., fig. 2E), wherein first interfaces between the second protection spacers 74 (fig. 2E) and the gate layer 6 are coplanar with a second interface (e.g., fig. 2E), which is between the gate electrode layer 7 and the gate layer 6 (e.g., fig. 2E), wherein the gate layer 6 has third side surfaces (e.g., fig. 2E), and the second protection spacers 74 have outer side surfaces away from the gate electrode layer 7, wherein each of the third side surfaces is a plane extending from a second top surface of the gate layer 6 (e.g., the upper portion of element 6 fig. 2E) to the barrier layer 5/62(62A/62B)/63(63A/63B) (fig. 2E, e.g., the combination of element 5 and a lower portion of element 6), and portions of the third side surfaces connecting to the barrier layer are aligned with the corresponding outer side surfaces, see figs. 1-27 and pages 1-19 for more details.
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Re claim 2. The semiconductor device as claimed in claim 1, wherein each of the first interfaces (e.g., between elements 74 and 6) is a planar surface (e.g., fig. 2E).
Re claim 3. The semiconductor device as claimed in claim 1, wherein the first interfaces (e.g., fig. 2E; between elements 74 and 6) are adjacent to the second interface e.g., fig. 2E; between elements 7 and 6).
Re claim 4. The semiconductor device as claimed in claim 1, wherein the gate electrode layer 7 and the second protection spacers 74 (fig. 2E) are in contact with different portions of the second top surface (e.g., fig. 2E).
Re claim 5. The semiconductor device as claimed in claim 1, the third side surfaces of the gate layer are connected to the second top surface and the barrier layer 5 (e.g., fig. 2E).
Re claim 7. The semiconductor device as claimed in claim 5, wherein there is a remaining portion of the gate layer 6 (e.g., both sidewalls) on the barrier layer not covered by the first protection pattern layer 73 and the second protection spacers 74 (e.g., fig. 2E).
Re claim 8. The semiconductor device as claimed in claim 7, wherein a thickness of the remaining portion of the gate layer is greater than 0 nm and less than 15 nm (e.g., see paragraphs 27-29; 105 etc.).
Re claim 9. The semiconductor device as claimed in claim 1, wherein the first side surfaces of the gate electrode layer 7 are aligned with the corresponding second side surfaces of the first protection pattern layer 73 (e.g., fig. 2E).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Otake et al., US Pub. No. 2023/0420517 A1 in view of Du Yang et al., TW202230799 A from IDS.
Otake et al. disclosed above and Fig. 2E and paragraphs 136 and 137 further shows that the first protection pattern 73 layer and the second protection spacers 74 are formed of a first dielectric material (e.g., SiO2 Re claim 12); however, Otake et al. does not further show instant claim 10.
Du Yang et al. teach a similar semiconductor device, which comprises a substrate 102 (fig. 1); a buffer layer 104 (fig. 1) located on the substrate; a channel layer 106 (fig. 1) located on the buffer layer; a barrier layer 108 (fig. 1) located on the channel layer; and a gate structure 110/120/121 (fig. 1) disposed on the barrier layer, further comprising: a first interlayer dielectric 162 (fig. 1; e.g., Si3N4, AlN, Al2O3 Re claim 12) layer disposed on the barrier layer 108 and completely covering the gate structure; a conductive pattern 133 (fig. 1) disposed on a portion of the first interlayer dielectric layer and completely covering the gate structure; a second interlayer dielectric layer 164 (fig. 1) covering the first interlayer dielectric layer and the conductive pattern; and a source feature 130/134 (fig. 1) and a drain feature 140 (fig. 1) disposed on the second interlayer dielectric layer and located on opposite sides of the gate structure, wherein the source feature and the drain feature respectively pass through the second interlayer dielectric layer 164 , the first interlayer dielectric layer 162 and the barrier layer 108 and are in contact with the channel layer 106 (fig. 1).
Therefore, the subject matter as a whole would have been obvious to one having ordinary skill in the art before the invention was made to further form the S/D features as taught by Du Yang et al. in the device of Otake et al. in order to improve the performance of the device by providing excellent S/D contacts etc.
Re claim 11. The semiconductor device as claimed in claim 10, wherein the source feature 134 further passes through the conductive pattern 133 (fig. 1), wherein the drain feature 140 and the conductive pattern 133 are separated from each other by the second interlayer dielectric layer 164 (fig. 1).
Response to Arguments
Applicant's arguments filed 4/24/2026 have been fully considered but they are not persuasive for reasons herein above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK CHEN whose telephone number is (571)272-1689. The examiner can normally be reached Monday to Friday, 8am to 4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACK S CHEN/Primary Examiner, Art Unit 2893
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