DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I and Species I in the reply filed on 1/26/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 7-9, 21 and 25-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (US 2022/0336612 A1).
Re Claim 7, Chang teaches a device comprising:
a stack of nanostructures (stack of 107, Fig. 2P, para [0019]);
a gate structure (188, Fig. 2P, para [0079]) that wraps around the nanostructures (stack of 107);
an isolation region (165, Fig. 2O, para [0064], also see Fig. 2I where the layer is marked) between the stack of nanostructures and another stack of nanostructures adjacent thereto along a first direction (compare Figs. 2H, 2I and 2O, where the first direction is the horizontal axis in Figs. Figs. 2I and 2O);
a source/drain region (S/D 110, Fig. 2P, para [0019]) that abuts at least one of the nanostructures (see Fig. 2P); and
a spacer layer (184, Figs. 2O and 2P, para [0076]) that is on sidewalls of the gate structure (188, see Fig. 2P) and on sidewalls of the source/drain region (110, see Fig. 2O), the spacer layer (184) covering an area between the source/drain region and a neighboring source/drain region of another transistor along the first direction (see Fig. 2O).
Re Claim 8, Chang teaches the device of claim 7, wherein the spacer layer (184, Fig. 2O) entirely covers an upper surface of the isolation region (upper surface of 165, see Figs. 2I and 2O).
Re Claim 9, Chang teaches the device of claim 7, further comprising:
a fin (166, Fig. 2O, para [0065]); and
a bottom dielectric layer (112, Figs. 2O and 2P, para [0020]) between the fin (166) and the source/drain region (110).
Re Claim 21, Chang teaches a device, comprising:
a semiconductor fin (166, Fig. 2O, para [0065]);
an isolation region (165, Fig. 2O, para [0064], also see Fig. 2I where the layer is marked) adjacent the semiconductor fin (166);
a stack of nanostructures (stack of 107, Fig. 2P, para [0019]) over the semiconductor fin (166, compare Figs. 2O and 2P);
a gate structure (188, Fig. 2P, para [0079]) wrapping around the nanostructures (stack of 107, Fig. 2P); a source/drain region (S/D 110, Fig. 2P, para [0019]) abutting the stack (see Fig. 2P); and
a spacer layer (184, Figs. 2O and 2P, pare [0076]) on a sidewall of the gate structure (188, see Fig. 2P) and extending over an upper surface of the isolation region (upper surface of 165, see Fig. 2O), wherein the spacer layer (184) is positioned (see Fig. 2O) between the isolation region (165) and an interlayer dielectric layer (192, Fig. 2P, para [0077], also annotated in Fig. 2Q of Chang below).
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Re Claim 25, Chang teaches the device of claim 21, further comprising a bottom dielectric layer (112, Figs. 2O and 2P, para [0020]) positioned between the source/drain region (110) and the semiconductor fin (166) to prevent mesa leakage current (see para [0021]).
Re Claim 26, Chang teaches the device of claim 25, wherein the bottom dielectric layer (112) comprises at least one of SiN, SiOC, SiOCN, or SiCN (112 is made from the dielectric layer 156, para [0057], where dielectric layer 156 can be made of silicon nitride, para [0051]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-6, 13 and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2022/0336612 A1), and further in view of Lin et al. (US 2023/0028900 A1).
Re Claim 1, Chang teaches a device, comprising:
a first circuit region including (marked “1st circuit” in annotated Fig. 2P below):
a first stack of first nanostructures (stack of 107 in “1st circuit”, Fig. 2P, para [0019]);
an isolation region (165, Fig. 2O, para [0064], also see Fig. 2I where the layer is marked) abutting the first stack (stack of 107 in “1st circuit”, compare Figs. 2H, 2O and 2P) and positioned between the first stack and another stack of nanostructures that neighbors the first stack (compare Figs. 2H, 2O and 2P);
a spacer layer (170+184, Figs. 2I and 2O, paras [0062] and [0076]) on the isolation region (165), the spacer layer covering a peripheral portion of an upper surface of the isolation region and a central portion of the upper surface (see Fig. 2O);
a first gate structure (188 within “1st circuit”, Fig. 2P, para [0079]) wrapping around the first nanostructures (stack of 107 in “1st circuit”, Fig. 2P);
a second epitaxial layer (152 within “1st circuit”, Fig. 2P, para [0052]) abutting one of the first nanostructures (stack of 107 in “1st circuit”); and
a first source/drain region (S/D 110 in “1st circuit”, Fig. 2P, para [0019]) and is in contact with the first nanostructures (see Fig. 2P)
a second circuit region (marked “2nd circuit” in annotated Fig. 2P below) offset from the first circuit region (“1st circuit”), and including:
a second stack of second nanostructures (stack of 107 in “2nd circuit”, Fig. 2P) having a same number of second nanostructures as that of the first nanostructures of the first stack (see Fig. 2P);
a second gate structure (188 within “2nd circuit”, Fig. 2P, para [0079]) wrapping around the second nanostructures (stack of 107 in “2nd circuit”); and
a second source/drain region (S/D 110 in “2nd circuit”, Fig. 2P) that is in contact with a number of the second nanostructures (see Fig. 2P).
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Chang does not disclose the following:
the first source/drain region that is isolated physically and electrically from the one of the first nanostructures by the second epitaxial layer; and
a second source/drain region that is in contact with a number of the second nanostructures that exceeds a number of the first nanostructures that the first source/drain region is in contact with.
In a related field of endeavor, Lin teaches a device, where the device can have multiple transistor regions like 104a and 104d (Fig. 1A), where the effective number of channels within the transistor is different, which enables formation of transistors or groups of transistors with specific characteristics. For example, lower power devices can be formed by reducing the number of channels connected to the source/drain regions, and higher speed devices can be formed by connecting a larger number of channels to the source/drain regions (para [0016]). This can be done simply by increasing the vertical size of the semiconductor layer 118 (para [0070], Fig. 1A), which is made of undoped semiconductor material like silicon (similar to the undoped semiconductor layer 152 of Chang), thus reducing the number of effective channels, for example compare regions 104a an and 104d where the effective number of channels are three and two respectively, as the larger 118d undoped semiconductor layer electrically isolates one of the channels from S/D 110d (see Fig. 1A).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the device of Chang as taught by Lin, such that the device can have multiple transistor regions with different number of effective channel in each corresponding regions, performing varied functions within the same device (para [0016], Lin). This can be done simply by varying the vertical size of the layer 152 of Chang (similar to layer 118 of Lin), which will control the effective number of channels within a transistor region.
Thus, Chang modified by Lin teaches,
the first source/drain region (110d of region 104d, Fig. 1A, para [0047] of Lin, equivalent to S/D 110 in “1st circuit” of Chang) that is isolated physically and electrically from the one of the first nanostructures (lowest nanolayer of 106d, Fig. 1A, para [0047] Lin) by the second epitaxial layer (118d of region 104d, Fig. 1A, para [0045] of Lin, similar to the layer 152 of Chang); and
a second source/drain region (110a of region 104a, Fig. 1A, para [0023] of Lin, equivalent to S/D 110 in “2nd circuit” of Chang) that is in contact with a number of the second nanostructures that exceeds a number of the first nanostructures that the first source/drain region is in contact with (110a is in contact with three 106a nanochannels while 110d is in contact with two 106a nanochannels, see Fig. 1A of Lin).
Re Claim 2, Chang modified by Lin teaches the device of claim 1, further comprising:
a first bottom dielectric layer (120d of region 104d, Fig. 1A, para [0047] of Lin, equivalent to layer 112 in “1st circuit”, Fig. 2P, para [0020] of Chang) that is positioned between the first source/drain region (110d of region 104d, Fig. 1A, Lin) and the second epitaxial layer (118d of region 104d, Fig. 1A, Lin); and
a second bottom dielectric layer (120a of region 104a, Fig. 1A, para [0032] of Lin, equivalent to layer 112 in “2nd circuit”, Fig. 2P, para [0020] of Chang) that is positioned between the second source/drain region (110a of region 104a, Fig. 1A, Lin) and a first epitaxial layer (118a of region 104a, Fig. 1A, Lin), the second bottom dielectric layer being at a level that is lower than that of the first bottom dielectric layer (120a is at a level lower than 120d, see Fig. 1A of Lin).
Re Claim 3, Chang modified by Lin teaches the device of claim 1, wherein the spacer layer includes:
a first spacer layer (170, Figs. 2I and 2O, Chang) in contact with the isolation region (165, Figs. 2I and 2O, Chang); and
a second spacer layer (184, Fig. 2O, Chang) on the first spacer layer (170).
Re Claim 5, Chang modified by Lin teaches the device of claim 1, further comprising an interlayer dielectric layer (192, Fig. 2P, para [0077], also annotated in Fig. 2Q of Chang below) on the isolation region (165, Chang), the interlayer dielectric layer (192) being separated from the isolation region (165) by the spacer layer (170+184).
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Re Claim 6, Chang modified by Lin teaches the device of claim 1, wherein thickness of the spacer layer (170+184, Fig. 2O, Chang) on sidewalls of the first source/drain region (110, Fig. 2O, Chang) is less (see Fig. 2O, Chang) than thickness of the spacer layer on the central portion of the upper surface of the isolation region (165, Fig. 2O, Chang).
Re Claim 13, Chang teaches the device of claim 7, further comprising an undoped silicon layer (152, Fig. 2P, para [0052], 152 can be of the same material as substrate 102, but undoped, where 102 can be silicon, paras [0034] and [0052]) that abuts at least another one of the nanostructures (stack of 107, Fig. 2P).
Chang does not disclose that the undoped silicon layer isolating the at least another one nanostructure from the source/drain region.
In a related field of endeavor, Lin teaches a device, where the device can have multiple transistor regions like 104a and 104d (Fig. 1A), where the effective number of channels within the transistor is different, which enables formation of transistors or groups of transistors with specific characteristics. For example, lower power devices can be formed by reducing the number of channels connected to the source/drain regions, and higher speed devices can be formed by connecting a larger number of channels to the source/drain regions (para [0016]). This can be done simply by increasing the vertical size of the semiconductor layer 118 (para [0070], Fig. 1A), which is made of undoped semiconductor material like silicon (similar to the undoped semiconductor layer 152 of Chang), thus reducing the number of effective channels, for example compare regions 104a an and 104d where the effective number of channels are three and two respectively, as the larger 118d undoped semiconductor layer electrically isolates one of the channels from S/D 110d (see Fig. 1A).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the device of Chang as taught by Lin, such that the device can have multiple transistor regions with different number of effective channel in each corresponding regions, performing varied functions within the same device (para [0016], Lin). This can be done simply by varying the vertical size of the layer 152 of Chang (similar to layer 118 of Lin), which will control the effective number of channels within a transistor region.
Thus, Chang modified by Lin, teaches a first source/drain region (110d of region 104d, Fig. 1A, para [0047] of Lin, equivalent to S/D 110 in of Chang) that is isolated physically and electrically from the one of the first nanostructures (lowest nanolayer of 106d, Fig. 1A, para [0047] Lin) by the undoped silicon layer (118d of region 104d, Fig. 1A, para [0070] of Lin, similar to the undoped silicon layer 152 of Chang).
Re Claim 23, Chang teaches the device of claim 21, wherein the stack of nanostructures is a first stack (marked “1st stack of 107” in annotated Fig. 2P below, para [0019]), and the device further comprises a second stack of nanostructures (marked “2nd stack of 107” in annotated Fig. 2P below), wherein a first number of nanostructures in the first stack (“1st stack of 107”) are in contact with the source/drain region (S/D 110, Fig. 2P), and a second number of nanostructures in the second stack (“2nd stack of 107”) are in contact with a second source/drain region (2nd S/D 110, Fig. 2P).
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Chang does not disclose that the first number of nanostructures in contact with first source/drain is different than the second number of nanostructures in contact with second source/drain.
In a related field of endeavor, Lin teaches a device, where the device can have multiple transistor regions like 104a and 104d (Fig. 1A), where the effective number of channels within the transistor is different, which enables formation of transistors or groups of transistors with specific characteristics. For example, lower power devices can be formed by reducing the number of channels connected to the source/drain regions, and higher speed devices can be formed by connecting a larger number of channels to the source/drain regions (para [0016]). This can be done simply by increasing the vertical size of the semiconductor layer 118 (para [0070], Fig. 1A), which is made of undoped semiconductor material like silicon (similar to the undoped semiconductor layer 152 of Chang), thus reducing the number of effective channels, for example compare regions 104a an and 104d where the effective number of channels are three and two respectively, as the larger 118d undoped semiconductor layer electrically isolates one of the channels from S/D 110d (see Fig. 1A).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the device of Chang as taught by Lin, such that the device can have multiple transistor regions with different number of effective channel in each corresponding regions, performing varied functions within the same device (para [0016], Lin). This can be done simply by varying the vertical size of the layer 152 of Chang (similar to layer 118 of Lin), which will control the effective number of channels within a transistor region.
Re Claim 24, Chang modified by Lin teaches the device of claim 23, further comprising an undoped semiconductor layer (undoped silicon layer 118d of region 104d, Fig. 1A, para [0070] of Lin, similar to the undoped semiconductor layer 152 of Chang) that isolates at least one nanostructure in the second stack (lowest nanolayer of 106d, Fig. 1A, para [0047] Lin) from the second source/drain region (110d of region 104d, Fig. 1A, para [0047] of Lin, equivalent to “1st S/D 110” of Chang) to provide a hybrid effective width (vertical size of undoped silicon layer 118 determines the effective number of channels, Fig. 1A, Lin).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2022/0336612 A1) as applied to claim 9 above, and further in view of Xie et al. (US 2024/0203990 A1).
Re Claim 10, Chang teaches the device of claim 9, but does not disclose a source/drain contact that extends through the bottom dielectric layer and contacts the source/drain region.
One of ordinary skill would look into related arts to teach the formation of S/D contacts. Related art, Xie teaches both a front side and backside contacts to a S/D region. For example, in Fig. 13A, a top contact 182 is formed on the S/D 134 (para [0143]). In the same Fig. 13A, Xie also teaches a backside contact 186 extending through a dielectric layer 31 and contacts the S/D region 132 (para [0143]), similar to the claimed limitation. One of ordinary skill in the art would realize that there are only two predictable outcomes – either a top contact or a backside contact. Therefore, a person of ordinary skill has good reason to pursue the known options and reach the claimed limitation with anticipated success, see KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Thus, Chang modified by Xie teaches source/drain contact (186, Fig. 13A, Xie) that extends through the bottom dielectric layer (112, Fig. 2P of Chang, similar to dielectric layer 31 in Fig. 13A of Xie) and contacts the source/drain region (S/D 110, Fig. 2P of Chang, similar to S/D 132 in Fig. 13A of Xie).
Rejection 2
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included here can be found earlier in the Office action.
Claims 7, 11, 21 and 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 2021/0098605 A1).
Re Claim 7 Wang teaches a device comprising:
a stack of nanostructures (stack of channels 208 in 10AN region, Fig. 20A, para [0018]);
a gate structure (250, Fig. 20A, para [0051]) that wraps around the nanostructures (stack of channels 208);
an isolation region (212, Fig. 20A, para [0022]) between the stack of nanostructures (stack of channels 208 in 10AN region) and another stack of nanostructures adjacent thereto along a first direction (see Fig. 20A, where the first direction is the horizontal axis in Fig. 20A);
a source/drain region (S/D 244N, Fig. 20A, para [0039]) that abuts at least one of the nanostructures (see Fig. 20A); and
a spacer layer (234/235, compare Figs. 3A and 20A, paras [0028] and [0051], where 235 consists of the remaining gate spacer 234 defining the fin sidewall of the S/D trench, see Fig. 3A, para [0028]) that is on sidewalls of the gate structure (spacer 234 on sidewalls of gate structure 250, compare Figs. 3A and 20A) and on sidewalls of the source/drain region (spacer 235 on sidewalls of S/D 244N, compare Figs. 3A and 20A), the spacer layer covering an area between the source/drain region and a neighboring source/drain region of another transistor along the first direction (see Fig. 20A, rightmost figure).
Re Claim 11 Wang teaches the device of claim 7, further comprising an etch stop layer (246, Fig. 20A, para [0051]), the spacer layer (235) being between the etch stop layer (246) and the isolation region (212).
Re Claim 21 Wang teaches a device, comprising:
a semiconductor fin (210A, compare Figs. 2A and 20A, para [0015]);
an isolation region (212, Fig. 20A, para [0022]) adjacent the semiconductor fin (210A);
a stack of nanostructures (stack of channels 208 in 10AN region, compare Figs. 2A and 20A) over the semiconductor fin (210A);
a gate structure (250, Fig. 20A, para [0051) wrapping around the nanostructures (stack of channels 208);
a source/drain region (S/D 244N, Fig. 20A, para [0039]) abutting the stack (stack of channels 208); and
a spacer layer (234/235, compare Figs. 3A and 20A, paras [0028] and [0051], where 235 consists of the remaining gate spacer 234 defining the fin sidewall of the S/D trench, see Fig. 3A, para [0028]) on a sidewall of the gate structure (spacer 234 on sidewalls of gate structure 250, compare Figs. 3A and 20A) and extending over an upper surface of the isolation region (spacer 235 on an upper surface of isolation structure 212, compare Figs. 3A and 20A), wherein the spacer layer (235) is positioned between the isolation region (212) and an interlayer dielectric layer (248, Fig. 20A, para [0051]).
Re Claim 27 Wang teaches the device of claim 21, wherein the spacer layer (234/235, note that 235 consists of 234-1 + 234-2 + 234-3, which is the remaining gate spacer 234 defining the fin sidewall of the S/D trench, see Figs. 3A and 20A, and claim 21 above, also see annotated Fig. 3A below) comprises a first spacer layer (234-1, compare Figs. 3A and 20A) in contact with the isolation region (212) and a second spacer layer (234-2, compare Figs. 3A and 20A) on the first spacer layer (234-1), the second spacer layer (234-2) having an opening that overlaps the isolation region (212, compare Figs. 3A and 20A).
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Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included here can be found earlier in the Office action.
Claims 1 and 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2021/0098605 A1), and further in view of Lee et al. (US 2022/0238678 A1).
Re Claim 1, Wang teaches a device, comprising:
a first circuit region (marked “1st circuit” in 10AN region, in annotated Fig. 20A below, para [0034]) including:
a first stack of first nanostructures (stack of channels 208 in “1st circuit”, Fig. 20A, para [0018]);
an isolation region (212, Fig. 20A, para [0022]) abutting the first stack (stack of 208 in “1st circuit”) and positioned between the first stack and another stack of nanostructures that neighbors the first stack (see Fig. 20A);
a spacer layer (235+246, Fig. 20A, paras [0028] and [0051], where 235 consists of 234-1 + 234-2 + 234-3, which is the remaining gate spacer 234 defining the fin sidewall of the S/D trench, see Fig. 3A, para [0028]) on the isolation region (212), the spacer layer covering a peripheral portion of an upper surface of the isolation region (212, see Fig. 20A) and a central portion of the upper surface (see Fig. 20A);
a first gate structure (250 within “1st circuit”, Fig. 20A, para [0051]) wrapping around the first nanostructures (stack of 208 in “1st circuit”);
a first source/drain region (S/D 244N in “1st circuit”, Fig. 20A, para [0039]) that is in contact with others of the first nanostructures (stack of 208 in “1st circuit”); and
a second circuit region (marked “2nd circuit” in 10AN region, in annotated Fig. 20A below) offset from the first circuit region (“1st circuit”), and including:
a second stack of second nanostructures (stack of channels 208 in “2nd circuit”, Figs. 20A) having a same number of second nanostructures as that of the first nanostructures of the first stack (see Fig. 20A);
a second gate structure (250 within “2nd circuit”, Fig. 20A, para [0051]) wrapping around the second nanostructures; and
a second source/drain region (S/D 244N in “2nd circuit”, Fig. 20A) that is in contact with a number of the second nanostructures (see Fig. 20A).
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Wang does not disclose:
a second epitaxial layer abutting one of the first nanostructures; and
a first source/drain region that is isolated physically and electrically from the one of the first nanostructures by the second epitaxial layer; and
a second source/drain region that is in contact with a number of the second nanostructures that exceeds a number of the first nanostructures that the first source/drain region is in contact with.
In a related field of endeavor, Lee teaches a device, where the device can have multiple transistor regions like Figs. 6J and 6K, where the effective number of channels within the transistor is different, which enables formation of transistors or groups of transistors with specific characteristics. For example, devices having a greater number of channel regions provides for a high-performance application in a circuit, such as a high-speed device, while devices having a lower number of channel regions provides for a low power application in a circuit, such as a low standby leak circuit design, para [0022].This can be done simply by introducing an undoped semiconductor layer (606, Fig. 6K, para [0086]), which reduces the vertical height of the S/D regions (608, Fig. 6K, para [0088]), thus reducing the number of effective channels, for example the device in Fig. 6J has three effective channels while the device in Fig. 6K has two effective channels.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the device of Wang as taught by Lee, such that the device can have multiple transistor regions with different number of channel widths in each corresponding regions, performing varied functions within the same device (para [0022], Lee). This can be done simply by introducing an undoped semiconductor layer within the S/D recess, thus reducing the vertical height of the S/D regions, thereby reducing the number of effective channels.
Thus, Wang modified by Lee teaches,
a second epitaxial layer (606, Fig. 6K, para [0086], Lee) abutting one of the first nanostructures (nanochannels 206 in Fig. 6K, Lee, similar to stack of 208 in “1st circuit” of Wang); and
a first source/drain region (608, Fig. 6K, para [0088], Lee, similar to S/D region in “1st circuit” of Wang) that is isolated physically and electrically from the one of the first nanostructures (lowest 208 layer, Fig. 6K, Lee) by the second epitaxial layer (606, Fig. 6K, Lee); and
a second source/drain region (608, Fig. 6J, para [0088], Lee, similar to S/D region in “2nd circuit” of Wang) that is in contact with a number of the second nanostructures (nanochannels 206 in Fig. 6J, Lee) that exceeds a number of the first nanostructures that the first source/drain region is in contact with (608 in Fig. 6J is in contact with three nanochannels while 608 in Fig. 6K is in contact with two nanochannels, Lee).
Re Claim 3, Wang modified by Lee teaches the device of claim 1, wherein the spacer layer (235+246, where 235 consists of 234-1 + 234-2 + 234-3, see Figs. 3A and 20A, and claim 1 above, also see annotated Fig. 3A below) includes:
a first spacer layer (234-1, compare Figs. 3A and 20A) in contact with the isolation region (212); and
a second spacer layer (234-2, compare Figs. 3A and 20A) on the first spacer layer (234-1).
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Re Claim 4, Wang modified by Lee teaches the device of claim 3, wherein the second spacer layer (234-2) has an opening that overlaps the isolation region (212, compare Figs. 3A and 20A).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2021/0098605 A1) as applied to claim 7 above, and further in view of Ching et al. (US 2016/0240652 A1).
Re Claim 12, Wang teaches the device of claim 7, but does not explicitly disclose that the thickness of the spacer layer on the sidewalls of the source/drain region is in a range of about 5 nanometers (nm) to about 20 nm and thickness of the spacer layer on the upper surface of the isolation region is in a range of about 2 nm to about 8 nm.
However, in a related semiconductor art, Ching teaches that the thickness of the gate spacers 132/140 in Figs. 37A/37B (similar to spacer 234/235 of Wang) is between 3 nm and 10 nm (para [0073]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to use the known spacer widths of Ching and apply it on the device of Wang. Thus, spacer layer (235, Fig. 20A, Wang, see claim 7 above) on the sidewalls of the S/D region (S/D 244N, Fig. 20A) and on the upper surface of the isolation region (212, Fig. 20A), can be in the range 3 nm and 10 nm, as disclosed by Ching, overlapping the claimed range. The claimed ranges would have been obvious to optimize and ascertainable through routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2021/0098605 A1) as applied to claim 21 above, and further in view of Tsai et al. (US 2021/0407858 A1).
Re Claim 22, Wang teaches the device of claim 21, wherein it teaches a spacer layer (235, Figs. 3A and 20A) that partly covers the upper surface of the isolation structure (212, compare Figs. 3A and 20A) but does not disclose that the spacer layer entirely covers the upper surface of the isolation region to protect the isolation region from etching during formation of the source/drain region.
However, in a related field of endeavor, Tsai teaches that spacer layer 140 (Fig. 1C-2, para [0062]) can cover the entire upper surface of the isolation layer 120, as it completely protects the isolation structure from etching during the S/D formation and also avoids any bridging between neighboring S/D structures (para [0076]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to use the teachings of Tsai, and cover the entire upper surface of the isolation structure (212, Fig. 20A) of Wang by the spacer layer (234/235, Fig. 20A), as it completely protects the isolation structure from etching during the S/D formation and also avoids any bridging between neighboring S/D structures (para [0076], Tsai).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINAKI DAS whose telephone number is (703)756-5641. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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