DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites “wherein the encapsulant is entirely covered by the package bonding layer.” However, it is unclear how this is possible because the package bonding layer is taught to be formed prior to singulation and therefore cannot cover the sides of the encapsulant. Additionally, Applicant’s Figures and Specification do not teach any method by which the package bonding layer covers the sides or top of the encapsulant, and therefore do not teach a method by which the encapsulant can be “entirely covered” by the package bonding layer. It is unclear if Applicant intends for “entirely covered” to refer only to the top surface in order to have basis in the Application, or instead intends for it to have its plain meaning of “covers the entirety of the encapsulant”, which has no basis in the Application. Claims 8-9 depend from claim 7 and inherit the deficiencies of claim 7.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 10-13, 16 and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kurita et al. (U.S. Publication No. 2025/0015002).
Regarding claim 1, Kurita teaches a semiconductor package, comprising:
a first device die (Fig. 28, first die 411) and a second device die (second die 421);
an encapsulant (encapsulant 45), laterally encapsulating the first and second device dies (Fig. 28 and 6);
a bridge die (bridge die 431), electrically connected to the first and second device dies (Fig. 28) and establishing communication between the first and second device dies (Fig. 28 and known definition of a bridge); and
bonding layers, between the first and second device dies and the bridge die, and comprising a first die bonding layer (first bonding layer 82) and a second die bonding layer (second bonding layer 83) respectively disposed upon the first device die and the second device die (Fig. 28), and a third die bonding layer (third bonding layer 84) disposed upon the bridge die (Fig. 28), wherein each of the bonding layers comprises a polymer layer and metallic features embedded in the polymer layer (paragraph [0182]; and Fig. 28, metallic features 417/427/436).
Regarding claim 2, Kurita teaches the semiconductor package according to claim 1, wherein the metallic features in the bonding layers are arranged to form vertical conduction paths (Fig. 28), and the device dies are electrically connected to the bridge die by a first group of the vertical conduction paths (Fig. 28).
Regarding claim 3, Kurita teaches the semiconductor package according to claim 2, wherein the metallic features in each vertical conduction path in the first group comprise a stack of contact metals in vertical alignment with one another, and a solder cap sandwiched there-between (Fig. 28, solder cap 473/483).
Regarding claim 10, Kurita teaches a semiconductor package, comprising:
device dies (Fig. 28, dies 411 and 421) having first die bonding layers (layers 82 and 83) respectively covering active sides of the device dies (Fig. 28);
an encapsulant (encapsulant 45), laterally surrounding and in lateral contact with the device dies and the first die bonding layers (Fig. 6 and 28);
a first package bonding layer (package bonding layer 81), covering the encapsulant (covers bottom side, Fig. 28) and the first die bonding layers (Fig. 28);
a bridge die (bridge die 431), electrically communicating the device dies (Fig. 28);
electrical connectors (electrical connectors 401), separated from the first die bonding layers via the first package bonding layer (Fig. 28); and
a second die bonding layer (second die bonding layer 84), between the bridge die and the first package bonding layer (Fig. 28), wherein each layer of the first die bonding layers, the first package bonding layer and the second die bonding layer comprises a polymer layer (paragraphs [0182] and [0203]) metallic features (metallic features 417/427/436/472) embedded in the polymer layer (Fig. 28).
Regarding claim 11, Kurita teaches the semiconductor package according to claim 10, wherein the bridge die is electrically connected to the device dies via first vertical conduction paths (vertical conduction paths 417/47/436) including first stacks of the metallic features in the first die bonding layers (metallic features 417/427), the first package bonding layer (47) and the second die bonding layer (436), and the electrical connectors are electrically connected to the device dies via second vertical conduction paths (second path 416/49) including second stacks of the metallic features in the first package bonding layer (416) and the first die bonding layers (49).
Regarding claim 12, Kurita teaches the semiconductor package according to claim 11, wherein the first vertical conduction paths each having a first width are arranged with a first pitch (see Fig. 28), the second vertical conduction paths each having a second width are arranged with a second pitch (Fig. 28), the first width is shorter than the second width (see Fig. 28), and the first pitch is smaller than the second pitch (see Fig. 57, which shows view with multiple of each conduction path).
Regarding claim 13, Kurita teaches the semiconductor package according to claim 12, wherein the first vertical conduction paths are longer than the second vertical conduction paths (see Fig. 28, first path includes portion 436 as well).
Regarding claim 16, Kurita teaches a method for manufacturing a semiconductor package, comprising:
forming first die bonding layers (Fig. 28, first bonding layers 82, 83) on device dies (dies 411, 421), respectively;
forming a second die bonding layer (second layer 84) on a bridge die (bridge die 431);
providing a package bonding layer (package bonding layer 81);
laterally encapsulating the device dies and the first die bonding layers by an encapsulant (encapsulant 45); and
bonding the second die bonding layer to the package bonding layer (Fig. 28), such that the device dies are electrically connected to the bridge die via conduction paths (paths 417/47/436) extending through polymer layers of the first die bonding layers (Fig. 28), the package bonding layer and the second die bonding layer (Fig. 28), and the polymer layer of second die bonding layer is bonded to the polymer layer of the package bonding layer (Fig. 28).
Regarding claim 19, Kurita teaches the method for manufacturing the semiconductor package according to claim 16, wherein the package bonding layer is provided on the encapsulant and the first die bonding layers (Fig. 28).
Regarding claim 20, Kurita teaches the method for manufacturing the semiconductor package according to claim 16, further comprising:
performing a singulation process to cut through the polymer layer of the package bonding layer and the encapsulant (Fig. 59-60).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kurita in view of Hsieh et al. (U.S. Publication No. 2021/0202389).
Regarding claim 4, Kurita teaches the semiconductor package according to claim 2, further comprising:
electrical connectors (Fig. 28, electrical connectors 49), but does not teach a passive die, connected to the device dies via a second group of the vertical conduction paths.
However, Hsieh teaches a similar package in which passive devices are connected to a second group of vertical conduction paths (see Hsieh Fig. 1G, passive devices C1-C4 connected through vertical paths at B1). It would have been obvious to a person of skill in the art at the time of the effective filing date that the package of Kurita could have had passive devices also connected to the dies because this allows for integrated capacitors, which can be used for decoupling or other functions without the need for external devices.
Regarding claim 5, Kurita in view of Hsieh teaches the semiconductor package according to claim 4, wherein the first and second groups of the vertical conduction paths are distributed within regions overlapped with the device dies (see Hsieh Fig. 1G and Kurita Fig. 28).
Regarding claim 6, Kurita teaches the semiconductor package according to claim 1, wherein the third die bonding layer is in contact with the first and second die bonding layers via polymer bonding and metallic bonding (see Fig. 28 and paragraph [0159] and [0182]).
Kruita does not teach that the contact is direct. However, Hsieh teaches that the third bonding layer can be in direct contact with the first and second bonding layers (see Hsieh Fig. 8-9, intervening RDL can be present or not present). It would have been obvious to a person of skill in the art at the time of the effective filing date that the bonding layers could have been directly contacting because it would have been a simple substitution of one known layout for another, as taught by Hsieh, with predictable results.
Claims 14-15 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kurita in view of Yu et al. (U.S. Publication No. 2019/0139925)
Regarding claim 14, Kurita teaches the semiconductor package according to claim 11, but does not teach further comprising:
a second package bonding layer, lying between the first package bonding layer and the first die bonding layer, and comprising a polymer layer and metallic features embedded in the polymer layer, wherein the first vertical conduction paths and the second vertical conduction paths further comprise the metallic features of the second package bonding layer.
However, Yu teaches a similar package in which the package bonding layer can include multiple layers made of polymer with metallic features (see Yu Fig. 4G, paragraph [0041], bonding layers DI). It would have been obvious to a person of skill in the art at the time of the effective filing date that the package bonding layer could have had multiple layers because this allows for more complex routing of signals.
Regarding claim 15, Kurita in view of Yu teaches the semiconductor package according to claim 14, wherein the polymer layers of the first die bonding layers are directly bonded with the polymer layer of the second package bonding layer (see Yu Fig. 4G).
Regarding claim 17, Kurita teaches the method for manufacturing the semiconductor package according to claim 16, but does not teach further comprising:
bonding the first die bonding layers to the additional package bonding layer before laterally encapsulating the device die and the first die bonding layers with the encapsulant (see Fig. 33-36, encapsulant occurs after bonding to package bonding layer)
Kurita does not teach providing an additional package bonding layer, wherein the polymer layers of the first die bonding layers are bonded to a polymer layer of the additional package bonding layer. However, Yu teaches a similar package in which the package bonding layer can include multiple layers made of polymer with metallic features (see Yu Fig. 4G, paragraph [0041], bonding layers DI). It would have been obvious to a person of skill in the art at the time of the effective filing date that the package bonding layer could have had multiple layers because this allows for more complex routing of signals.
Regarding claim 18, Kurita in view of Yu teaches the method for manufacturing the semiconductor package according to claim 17, wherein the package bonding layer is provided on the additional package bonding layer after laterally encapsulating the device die and the first die bonding layers with the encapsulant (see Yu Fig. 4G, the two package bonding layers are provided together after the encapsulant is in place – Examiner notes that “provided on” is not interpreted to be the same as “bonded to” or “formed on” or any other implication of actual method steps, but instead only that the two exist together after the encapsulation occurs, regardless of whether they also existed together prior to encapsulation).
Conclusion
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/EVAN G CLINTON/ Primary Examiner, Art Unit 2899