Prosecution Insights
Last updated: April 18, 2026
Application No. 18/343,801

PACKAGE STRUCTURE INCLUDING RING STRUCTURE AND METHODS OF FORMING THE SAME

Final Rejection §103§112
Filed
Jun 29, 2023
Examiner
PALANISWAMY, KRISHNA JAYANTHI
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Limited
OA Round
2 (Final)
58%
Grant Probability
Moderate
3-4
OA Rounds
3y 6m
To Grant
99%
With Interview

Examiner Intelligence

Grants 58% of resolved cases
58%
Career Allow Rate
7 granted / 12 resolved
-9.7% vs TC avg
Strong +50% interview lift
Without
With
+50.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
23 currently pending
Career history
35
Total Applications
across all art units

Statute-Specific Performance

§103
54.1%
+14.1% vs TC avg
§102
18.1%
-21.9% vs TC avg
§112
27.8%
-12.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 12 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s amendments to the claims 1 - 4, 6, 9, 16 and 20 have been fully considered. Based on the cited prior arts Kong, Sathe, Loo, Leung, Chiu, Zheng, and Wang and new grounds of rejections from Kang, Kwon, and Lin the claims 1-20 are rejected. Response to Amendment Applicant’s amendments to the specification, filed on 02/03/2026 have been fully considered and resolve the informalities of specification objections. The objection to the specification has been withdrawn. Applicant’s amendments to the drawings, filed on 02/03/2026 have been fully considered and resolve the informalities of drawing objections. The objection to the specification has been withdrawn. Applicant’s amendments to the claim 16, filed on 02/03/2026 have been fully considered and resolve the informalities of claim objections. The objection to the specification has been withdrawn. Applicant’s amendments with respect to claims 6 and 9 filed on 02/03/2026 have been fully considered and resolve the issues of indefiniteness and lack of written description. The 35 U.S.C. 112(b) rejections of claims 6 and 9 have been withdrawn. Claim Objections Claim 3 is objected to because of the following informalities: Claim 3 recites “the second adhesive has a Young's modulus less than a Young's modulus of the first adhesive.” This should be written as “the Young’s modulus of the second adhesive is less than the Young's modulus of the first adhesive.” Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 2 recites “the first CTE of the outer ring is greater than a CTE of the package substrate and the second CTE of the inner ring is less than the CTE of the package substrate.” Claim 2 is indefinite because it depends on claim 1 and contradicts the claim 1 limitation “the outer ring has a first coefficient of thermal expansion (CTE) and the inner ring has a second CTE greater than the first CTE.” Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kong et al. (US20190259704A1; hereinafter Kong) in view of Kang et al. (US20230207487A1; hereinafter Kang). Regarding Claim 1 (Currently Amended), Kong discloses a package structure (semiconductor package stiffeners, [0002]) comprising: a package substrate (semiconductor package substrate 110, FIG. 1C reproduced below, [0018]); a semiconductor die module on the package substrate (first die 10 disposed on the die side 111 and forms electronic coupling between the first die and the semiconductor package substrate 110, FIG. 1C, [0021]); a first adhesive (electrically conductive adhesive film 144) and a second adhesive (electrically conductive adhesive film 146) on the package substrate (110), wherein the second adhesive (146) is between the first adhesive (144) and the semiconductor die module (10), FIG. 1C, [0031]; and a ring structure (ring stiffeners 112, 114 and 116) on the package substrate (110) around the semiconductor die module (10), wherein the ring structure comprises an outer ring (outer ring structure 116) attached to the package substrate (110) by the first adhesive (144), and an inner ring (112) attached to the package substrate (110) by the second adhesive (146) between the semiconductor die module (12) and the outer ring (116), FIG. 1C, [0031]. PNG media_image1.png 259 533 media_image1.png Greyscale Kong: FIG. 1C Kong does not disclose “the outer ring has a first coefficient of thermal expansion (CTE) and the inner ring has a second CTE greater than the first CTE.” In a similar art, Kang discloses a semiconductor package including logic chips and stiffeners 121 and 122 spaced apart from each other and attached to the substrate 10 with an adhesive member 110, FIG. 2, [0023], [0048]. Kang discloses: the outer ring (121) has a first coefficient of thermal expansion (CTE) and the inner ring (122) has a second CTE greater than the first CTE, FIG. 2, [0050]. Kang [0050] discloses each CTE of the first stiffener 121 and the second stiffener 122 may be greater than the CTE of the substrate 10, and the CTEs of the first stiffener 121 and the second stiffener 122 may be different from each other. This indicates the second coefficient of thermal expansion of the inner ring 122 may be greater than the first coefficient of thermal expansion of the outer ring 121. Kang discloses that the package structure as taught balances external physical forces and minimizes package warpage [0050]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong’s structure in order to minimize the package warpage as disclosed by Kang [0050]. Regarding Claim 16 (Currently amended), Kong discloses a method of making a package structure (method of assembling a stiffener to a semiconductor package substrate, [0099]), the method comprising: attaching a semiconductor die module on a package substrate (first die 10 disposed on the die side 111 and forms electronic coupling between the first die and the semiconductor package substrate 110, FIG. 1C, [0021]); forming a first adhesive (electrically conductive adhesive film 144) and a second adhesive (electrically conductive adhesive film 146) on the package substrate (110), wherein the second adhesive (146) is between the first adhesive (144) and the semiconductor die module (10), FIG. 1C, [0031]; and attaching a ring structure (ring stiffeners 112, 114 and 116) to the package substrate (110) around the semiconductor die module (10) such that an outer ring (outer ring 116) of the ring structure is attached to the package substrate (110) by the first adhesive (144), and an inner ring (112) of the ring structure is attached to the package substrate (110) by the second adhesive (146) between the semiconductor die module (12) and the outer ring (116), FIG. 1C, [0031]. Kong does not disclose “the outer ring has a first coefficient of thermal expansion (CTE) and the inner ring has a second CTE greater than the first CTE.” In a similar art, Kang discloses a semiconductor package including logic chips and stiffeners 121 and 122 spaced apart from each other and attached to the substrate 10 with an adhesive member 110, FIG. 2, [0023], [0048]. Kang discloses: and the outer ring (121) has a first coefficient of thermal expansion (CTE) and the inner ring (122) has a second CTE greater than the first CTE, FIG. 2, [0050]. Kang [0050] discloses each CTE of the first stiffener 121 and the second stiffener 122 may be greater than the CTE of the substrate 10, and the CTEs of the first stiffener 121 and the second stiffener 122 may be different from each other. This indicates the second coefficient of thermal expansion of the inner ring 122 may be greater than the first coefficient of thermal expansion of the outer ring 121. Kang discloses that the package structure as taught balances external physical forces and minimizes package warpage [0050]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong’s structure in order to minimize the package warpage as disclosed by Kang [0050]. Claims 7 - 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kong in view of Kang, further in view of Sathe et al. (US20090152738A1; hereinafter Sathe). Regarding Claim 7, The combination of Kong and Kang discloses the package structure of claim 1. The combination of Kong and Kang does not disclose “wherein the outer ring has a first side having a first width and a second side having a second width greater than the first width, and the inner ring has a third side having a third width and a fourth side having a fourth width greater than the third width.” The combination of Kong and Sathe discloses: wherein the outer ring (Kong: 116) has a first side having a first width (Sathe: W2, FIG. 1A, [0021]) and a second side having a second width (Sathe: W1) greater than the first width, and the inner ring (Kong: 112) has a third side having a third width (Sathe: W2) and a fourth side having a fourth width (Sathe: W1) greater than the third width. Sathe (FIG. 1A, [0026]) discloses the two opposing lengths 191 a, 191 b of the frame-shaped stiffener 190 have a width W1 that is greater than a width W2 of the other two opposing sides 191 c, 191 d of the stiffener. Sathe discloses that the package structure as taught minimized the package warpage [0027]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong and Kang’s structure in order to minimize the package warpage as disclosed by Sathe [0027]. Regarding Claim 8, The combination of Kong, Kang, and Sathe discloses the package structure of claim 7. Kong further discloses: wherein the first side of the outer ring (Kong: 116) is located on the third side of the inner ring (Kong: 112), and the second side of the outer ring (116) is located on the fourth side of the inner ring (112). Kong [0018], [0019], FIG.1 discloses the ring stiffeners are rectangular and the outer ring stiffener 116 in included with the inner ring stiffener 112 and sandwich the subsequent ring stiffener 114, indicating the first side of the outer ring is located on the third side of the inner ring, and the second side of the outer ring is located on the fourth side of the inner ring. Regarding Claim 9 (Currently amended), The combination of Kong, Kang, and Sathe discloses the package structure of claim 8. Kong further discloses: wherein the first side of the outer ring (116) is separated from the third side of the inner ring (112, 114) by a first middle distance and the second side of the outer ring (116) is separated from the fourth side of the inner ring (112, 114) by a second middle distance the same as the first middle distance. Kong [0022], [0023] disclose passive devices such as capacitors are supplied between the inner ring stiffener 112 and the subsequent ring stiffener 114 and the outer ring 116, indicating the same size and count of the passive devices can be placed on the opposite sides of the rings and the first and the second middle distances can be substantially the same. Regarding Claim 20 (Currently amended), Kong discloses a package structure (semiconductor package stiffeners, [0002]), comprising: a first adhesive (electrically conductive adhesive film 144) and a second adhesive (electrically conductive adhesive film 146) on the package substrate (110), wherein the second adhesive (146) is between the first adhesive (144) and the semiconductor die module (10), FIG. 1C, [0031]. Kong does not explicitly disclose “a package substrate having a first package substrate length in a first direction and a second package substrate length in a second direction perpendicular to the first direction, and having a package substrate length ratio of the first package substrate length to the second package substrate length; a semiconductor die module having a first semiconductor die module length in the first direction and a second semiconductor die module length in the second direction, and having a semiconductor die module length ratio of the first semiconductor die module length to the second semiconductor die module length greater than the package substrate length ratio.” Sathe discloses a package substrate (substrate 120, [0011]) having a first package substrate length in a first direction and a second package substrate length in a second direction perpendicular to the first direction (substrate having dimensions of 14 mm by 13 mm, [0027]) and having a package substrate length ratio of the first package substrate length to the second package substrate length (package length ratio = 14/13 = 1.08); a semiconductor die module (integrated circuit die 110, [0011]) having a first semiconductor die module length in the first direction and a second semiconductor die module length in the second direction (a die having dimensions of 8 mm by 3 mm, [0027]) and having a semiconductor die module length ratio of the first semiconductor die module length to the second semiconductor die module length (semiconductor die module length ratio = 8/3 = 2.67) greater than the package substrate length ratio (1.08); The combination of Kong and Sathe discloses: a ring structure attached to the package substrate (Kong: ring stiffeners 112, 114 and 116 attached to substrate 110, FIG. 1A, [0032]) around the semiconductor die module (10), wherein the ring structure comprises: an outer ring attached to the package substrate by the first adhesive (Kong: outer ring 116 attached to substrate 110 by adhesive 144, FIG. 1C, [0031]) and having a first width in the first direction and a second width greater than the first width in the second direction (Sathe: ring stiffener 190 with widths W1 = 428 microns and W2 = 352 microns, FIG. 1A, [0027]); and Sathe [0021] discloses two opposing lengths 191 a, 191 b of the frame-shaped stiffener 190 have a width W1 that is greater than a width W2 of the other two opposing sides 191 c, 191 d of the stiffener. an inner ring attached to the package substrate by the second adhesive (Kong: inner ring 112 attached to substrate 110 by adhesive 146, FIG. 1C, [0031]) and having a third width in the first direction and a fourth width greater than the third width in the second direction (Sathe: ring stiffener 190 with widths W1 = 428 microns and W2 = 352 microns, FIG. 1A, [0027]); and Sathe [0021] discloses two opposing lengths 191 a, 191 b of the frame-shaped stiffener 190 have a width W1 that is greater than a width W2 of the other two opposing sides 191 c, 191 d of the stiffener. Sathe discloses that the package structure as taught minimized the package warpage [0027]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong’s structure in order to minimize the package warpage as disclosed by Sathe [0027]. The combination of Kong and Sathe does not disclose “the outer ring has a first coefficient of thermal expansion (CTE) and the inner ring has a second CTE greater than the first CTE.” In a similar art, Kang discloses a semiconductor package including logic chips and stiffeners 121 and 122 spaced apart from each other and attached to the substrate 10 with an adhesive member 110, FIG. 2, [0023], [0048]. Kang discloses: and the outer ring (121) has a first coefficient of thermal expansion (CTE) and the inner ring (122) has a second CTE greater than the first CTE, FIG. 2, [0050]. Kang [0050] discloses each CTE of the first stiffener 121 and the second stiffener 122 may be greater than the CTE of the substrate 10, and the CTEs of the first stiffener 121 and the second stiffener 122 may be different from each other. This indicates the second coefficient of thermal expansion of the inner ring 122 may be greater than the first coefficient of thermal expansion of the outer ring 121. Kang discloses that the package structure as taught balances external physical forces and minimizes package warpage [0050]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong and Sathe’s structure in order to minimize the package warpage as disclosed by Kang [0050]. Claims 5, 14, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kong in view of Kang, further in view of Leung et al. (US20160073493A1; hereinafter Leung). Regarding Claim 5, The combination of Kong and Kang discloses the package structure of claim 1. The combination of Kong and Kang does not disclose “wherein the outer ring is located around an outer periphery of the package substrate and an outer distance between the outer ring and an edge of the package substrate is greater than a middle distance between the outer ring and the inner ring.” In a similar art, Leung discloses semiconductor processing of circuit boards with stiffener rings [0002]. The combination of Kong and Leung discloses: wherein the outer ring is located around an outer periphery of the package substrate (Leung: stiffener 20 with peripheral walls 31 and 35 are around the periphery of the circuit board 15, FIG. 1, [0029]) and an outer distance between the outer ring and an edge of the package substrate (Leung: a lateral gap 65 exists between the peripheral wall 35 of the ring 20 and the external peripheral wall 36 of the circuit board 15, FIG. 3, [0031]) is greater than a middle distance between the outer ring and the inner ring (Kong: FIG. 1, [0027]). Kong [0027], [0036] discloses the passive components with a minimum pole-to-pole length of approximately 0.4 mm between the outer stiffener and inner stiffener. Leung [0031] discloses the gap 65 between the ring 20 and the outer periphery of the circuit board 15 is a fraction of millimeter, indicating the gap can be approximately 0.9 mm. The outer distance between the outer ring and the edge of the package substrate (Leung: gap 65 can be approximately 0.9 mm) is greater than the middle distance between the outer ring and the inner ring (Kong: middle distance is the minimum pole to pole length of the passive component of approximately 0.4 mm). Leung discloses that a structure as taught reduces substrate warpage [0009]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong and Kang’s package structure to reduce substrate warpage as disclosed by Leung [0009]. Regarding Claim 14, The combination of Kong and Kang discloses the package structure of claim 1. The combination of Kong and Kang does not disclose “wherein the inner ring includes a conditioned surface including a plurality of fins.” The combination of Kong and Leung discloses: wherein the inner ring (Kong: 112) includes a conditioned surface including a plurality of fins (Leung: plural bumps 249 on ring portion 227, FIG. 6, [0035]). Leung discloses that a structure as taught eliminates the need for an adhesive while still providing significant structural engagement to limit the warpage of the substrate [0035]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong and Kang’s package structure to improve ring to substrate engagement and reduce substrate warpage as disclosed by Leung [0035]. Regarding Claim 17, The combination of Kong and Kang discloses the method of claim 16. The combination of Kong and Kang does not disclose “wherein the attaching of the ring structure to the package substrate comprises attaching the inner ring to the package substrate such that an outer distance between the outer ring and an edge of the package substrate is greater than a middle distance between the outer ring and the inner ring.” The combination of Kong and Leung discloses: wherein the attaching of the ring structure to the package substrate (Kong: ring stiffeners 112, 114, 116 attached to substrate 110, FIG. 1A, [0032]) comprises attaching the inner ring to the package substrate (Kong: inner ring stiffener 112 attached to substrate 110 FIG. 1A, [0032]) such that an outer distance between the outer ring and an edge of the package substrate (Leung: a lateral gap 65 exists between the peripheral wall 35 of the ring 20 and the external peripheral wall 36 of the circuit board 15, FIG. 3, [0031]) is greater than a middle distance between the outer ring and the inner ring (Kong: FIG. 1, [0027]). Kong [0027], [0036] discloses the passive components with a minimum pole-to-pole length of approximately 0.4 mm between the outer stiffener and inner stiffener. Leung [0031] discloses the gap 65 between the ring 20 and the outer periphery of the circuit board 15 is a fraction of millimeter, indicating the gap can be approximately 0.9 mm. The outer distance between the outer ring and the edge of the package substrate (Leung: gap 65 can be approximately 0.9 mm) is greater than the middle distance between the outer ring and the inner ring (Kong: middle distance is minimum pole to pole length of the passive component of approximately 0.4 mm). Leung discloses that a structure as taught reduces substrate warpage [0009]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong and Kang’s package structure to reduce substrate warpage as disclosed by Leung [0009]. Claims 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kong in view of Kang, further in view of Loo et al. (US20110018125A1; hereinafter Loo). Regarding Claim 12, The combination of Kong and Kang discloses the package structure of claim 1. The combination of Kong and Kang does not disclose “further comprising: a package lid mounted on the outer ring and covering the semiconductor die module; and a thermal interface material (TIM) layer between the package lid and the semiconductor die module.” In a similar art, Loo discloses semiconductor package with stiffeners [0004]. Loo discloses: further comprising: a package lid (heat spreader 18) mounted on the outer ring (104) and covering the semiconductor die module (12), FIG. 15, [0035]; and a thermal interface material (TIM) layer (thermally conductive material or thermal interface material 20), between the package lid (18) and the semiconductor die module (12), FIG. 15 reproduced below, [0035]. PNG media_image2.png 388 928 media_image2.png Greyscale Loo: FIG. 15 Loo discloses that a method as taught improves package rigidity, warpage and stress performance during temperature cycling [0031]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong and Kang’s package structure in order to improve rigidity, warpage and stress performance during temperature cycling as disclosed by Loo [0031]. Regarding Claim 19, The combination of Kong and Kang discloses the method of claim 16. The combination of Kong and Kang does not disclose “further comprising: forming a thermal interface material (TIM) layer on the semiconductor die module; and attaching a package lid to the outer ring and on the TIM layer.” Loo further discloses: further comprising: forming a thermal interface material (TIM) layer (20) on the semiconductor die module (12); and attaching a package lid (18) to the outer ring (104) and on the TIM layer (20), FIG. 15, [0035]. Loo discloses that a method as taught improves package rigidity, warpage and stress performance during temperature cycling [0031]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong and Kang’s package structure in order to improve rigidity, warpage and stress performance during temperature cycling as disclosed by Loo [0031]. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kong in view of Kang, further in view of Zheng et al. (CN216793661U; hereinafter Zheng). Regarding Claim 15, The combination of Kong and Kang discloses the package structure of claim 1. The combination of Kong and Kang does not disclose “wherein the package substrate includes a recessed portion and the inner ring is attached to the package substrate in the recessed portion.” In a similar art, Zheng discloses a packaging substrate and packaging structure [0001]. Zheng discloses: wherein the package substrate (substrate body 120) includes a recessed portion (core layer 122) and the inner ring (anti-warping ring 110) is attached to the package substrate in the recessed portion (the anti-warping ring 110 is located in the core layer 122, [0037], FIG. 2). Zheng discloses that a package structure as taught can increase the space for arranging devices on the surface of the substrate body, and prevent the anti-warping ring from separating from the substrate body [0004]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong and Kang’s package structure to increase the space for arranging devices and preventing the anti-warping ring from separating from the substrate as disclosed by Zheng [0004]. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kong in view of Kang, further in view of Sathe, still further in view of Lin et al. (US20130119529A1; hereinafter Lin). Regarding Claim 3 (Currently amended), The combination of Kong and Kang discloses the package structure of claim 1. The combination of Kong and Kang does not disclose “wherein the outer ring has a first width and the inner ring has a second width greater than the first width and the second adhesive has a Young's modulus less than a Young's modulus of the first adhesive.” In a similar art, Sathe discloses a package substrate (assembly 100 including an integrated circuit (IC) package 105, [0010]). The combination of Kong and Sathe disclose: wherein the outer ring (Kong: 116) has a first width and the inner ring (Kong: 112) has a second width greater than the first width (Sathe: FIG. 1A, [0021]). Sathe [0021] discloses any of the lengths 191 a-d of the frame-shaped stiffener 190 may have a width that differs from the width of any one or more of the other lengths of the stiffener, indicating the ring stiffener can have sides with different widths and the inner ring with the second width can be greater than the outer ring with the first width. Sathe discloses that the package structure as taught minimized the package warpage [0027]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong and Kang’s structure in order to minimize the package warpage as disclosed by Sathe [0027]. The combination of Kong, Kang, and Sathe does not disclose “the second adhesive has a Young's modulus less than a Young's modulus of the first adhesive.” In a similar art, Lin discloses a semiconductor device 10 including a die 100 embedded on the first substrate 20, FIG. 1, [0010]. Lin discloses: the second adhesive (90) has a Young's modulus less than a Young's modulus of the first adhesive (30), [0014], [0016]. Lin [0014] discloses the stiffener 60 is mounted between the substrate 20 and the lid 70 by means of first adhesives 30, which may include epoxy, glue or the like. Lin [0016] discloses the enclosure barrier 80 may be attached to the first substrate 20 by means of an adhesive 90 which includes epoxy, glue, Thermoplastic Polyurethane (TPU) or the like. The enclosure barrier 80 is interpreted as the inner ring since it surrounds the die 100 and extends downward from top of the lid 70 and is attached to substrate 20, FIG. 1, [0015], [0016]. Lin discloses a material choice of epoxy for the first adhesive 30 for the outer ring 60 and a material choice of TPU for the second adhesive 90 for the inner ring 80 to attach the stiffeners to the substrate 20. It would be obvious to one having an ordinary skill in the art that the Thermoplastic Polyurethane has a lower Young’s modulus than the epoxy. Thus, the second adhesive 90 may have a Young’s modulus less than a Young’s modulus of the first adhesive 30. Lin discloses that the package structure as taught counter-balances the forces exerted by the thermal expansion mismatches and improves structural integrity of the package [0014]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong, Kang, and Sathe’s structure in order to improve structural integrity as disclosed by Lin [0014]. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kong in view Kang, further in view of Chen et al. (US20210305227A1; hereinafter Chen), further in view of Kwon et al. (US20220208624A1; hereinafter Kwon). Regarding Claim 4 (Currently amended), The combination of Kong and Kang discloses the package structure of claim 1. Kong does not disclose “wherein the outer ring includes a first material and the inner ring includes a second material different than the first material; and a height of an upper surface of the inner ring is at least 0.1 mm greater than a height of an upper surface of the semiconductor die module.” Kang discloses each of the first stiffener 121 and the second stiffener 122 may include a metal such as copper, stainless steel (e.g., SUS403) or the like, [0055], [0056], but does not explicitly disclose “wherein the outer ring includes a first material and the inner ring includes a second material different than the first material.” In a similar art, Chen discloses multiple chip modules with stiffener structures [0004]. Chen discloses: wherein the outer ring (210) includes a first material and the inner ring (220) includes a second material different than the first material. FIG. 1, [0048]. Chen discloses that a stiffener structure as taught facilitates tuning of stress and warpage of the module [0058]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong and Kang’s package structure to facilitate tuning of stress and warpage as disclosed by Chen [0058]. The combination of Kong, Kang, and Chen does not disclose “a height of an upper surface of the inner ring is at least 0.1 mm greater than a height of an upper surface of the semiconductor die module.” In a similar art, Kwon discloses a semiconductor package 1000h including stiffener 130 and stiffener 300 around the die 120, FIG. 4E, [0080]. Kwon discloses: a height (H1) of an upper surface of the inner ring (130) is at least 0.1 mm greater than a height (H0) of an upper surface of the semiconductor die module (120), FIG. 4E, [0080]. Kwon [0080] discloses the second height H1 of the upper surface of the stiffener 130 may be greater than the first height H0 of the upper surface of the semiconductor chip 120. It would be obvious to select the height of the upper surface of the inner ring 130 to be at least 0.1mm greater than the height of the upper surface of the semiconductor die 120 as a routine optimization to improve thermal contact. Kwon discloses that a stiffener structure as taught improves thermal contact and thermal characteristics of the package [0080]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong, Kang, and Chen’s package structure to improve thermal characteristics of the package as disclosed by Kwon [0080]. Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kong in view Kang, further in view of Sathe, still further in view of Chiu et al. (US20210217682A1; hereinafter Chiu). Regarding Claim 10, The combination of Kong, Kang, and Sathe discloses the package structure of claim 7. The combination of Kong, Kang, and Sathe does not disclose “wherein the second width of the second side of the outer ring is at least 50% greater than the first width of the first side of the outer ring, and the fourth width of the fourth side of the inner ring is at least twice the third width of the third side of the inner ring.” In a similar art, Chiu discloses a semiconductor device with stiffener ring [0005]. The combination of Kong and Chiu disclose: wherein the second of the second side width (Chiu: width W1 on side 210C, FIG. 2B, [0027]) of the outer ring (Kong: 116, FIG. 1A, [0019]) is at least 50% greater than the first width of the first side (Chiu: width W2 on side 210A) of the outer ring (Kong: 116), and the fourth width of the fourth side (Chiu: width W1 on side 210C) of the inner ring (Kong: 112, FIG. 1A, [0019]) is at least twice the third width of the third side (Chiu: width W2 on side 210A) of the inner ring (Kong: 112), (Chiu: the ratio W1:W2 may be in the range of between about 1:1 to about 6:1, [0030]). Chiu discloses that a method as taught reduces the warpage of the semiconductor device [0002]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong, Kang, and Sathe’s package structure in order to reduce warpage as disclosed by Chiu [0002]. Regarding Claim 11, The combination of Kong, Kang, and Sathe discloses the package structure of claim 7. The combination of Kong, Kang, and Sathe does not disclose “wherein the semiconductor die module has a long side and a short side having a length less than the long side, the short side of the semiconductor die module is adjacent to the third side of the inner ring, and the long side of the semiconductor die module is adjacent to the fourth side of the inner ring.” In a similar art, Chiu discloses a semiconductor device with stiffener ring [0005]. The combination of Kong and Chiu disclose: wherein the semiconductor die module has a long side and a short side having a length less than the long side (Chiu: chip package 106 with long side L1 and short side L2, FIG. 1A, [0019]), the short side of the semiconductor die module is adjacent to the third side (Chiu: short side L2 is adjacent to ring side 210A with width W2, FIG. 2B, [0019]) of the inner ring (Kong: 112, FIG. 1A, [0019]), and the long side of the semiconductor die module is adjacent to the fourth side (Chiu: long side L1 is adjacent to ring side 210C with width W1) of the inner ring (Kong: 112). Chiu discloses that a method as taught reduces the warpage of the semiconductor device [0002]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong, Kang, and Sathe’s package structure in order to reduce warpage as disclosed by Chiu [0002]. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kong in view of Kang, further in view of Loo, still further in view of Wang et al. (US20080042263A1; hereinafter Wang). Regarding Claim 13, The combination of Kong, Kang, and Loo discloses the package structure of claim 12. The combination of Kong, Kang, and Loo does not disclose “wherein an upper surface of the inner ring is separated from a bottom surface of the package lid.” In a similar art, Wang discloses a reinforced semiconductor package with a stiffener [0002]. Wang discloses: wherein an upper surface of the inner ring (410) is separated from a bottom surface of the package lid (the inner ring 410 is in no contact with the heat sink 530, FIG. 5 reproduced below, [0029]). PNG media_image3.png 248 605 media_image3.png Greyscale Wang: FIG. 5 Wang discloses that a structure as taught prevents interference to the juncture between the outer ring and the heat sink. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong, Kang, and Loo’s package structure in order to prevent interference to the juncture between the outer ring and the heat sink as disclosed by Wang [0029]. Claims 6 and 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kong in view of Kang, further in view of Leung, still further in view of Loo. Regarding Claim 6 (Currently amended), The combination of Kong, Kang, and Leung discloses the package structure of claim 5. The combination of Kong, Kang, and Leung does not disclose “wherein an inner distance between the inner ring and the semiconductor die module is greater than the outer distance between the outer ring and the edge of the package substrate.” In a similar art, Loo discloses semiconductor package with stiffeners [0004]. Loo discloses: wherein an inner distance between the inner ring (102) and the semiconductor die module (12) is greater than the outer distance between the outer ring (104) and the edge of the package substrate, FIG. 15, [0033], [0034]. Loo [0033] discloses the inner edge of the inner ring structure 102 is spaced away from an outer edge of the die 12; and [0034] discloses the outer ring structure 104 may have an outer perimeter edge coincident with an outer perimeter edge of organic substrate printed wire board 10, indicating the inner distance between the inner ring and the die is greater than the outer distance between the outer ring and the edge of the package substrate. Loo discloses that a method as taught improves warpage and stress performance during temperature cycling [0031]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong, Kang, and Leung’s structure in order to improve warpage and stress performance during temperature cycling as disclosed by Loo [0031]. Regarding Claim 18, The combination of Kong, Kang, and Leung discloses the method of claim 17. The combination of Kong, Kang, and Leung does not disclose “wherein the attaching of the ring structure to the package substrate comprises attaching the outer ring to the package substrate such that an inner distance between the inner ring and the semiconductor die module is greater than the outer distance between the outer ring and the edge of the package substrate.” In a similar art, Loo discloses semiconductor package with stiffeners [0004]. Loo discloses: wherein the attaching of the ring structure to the package substrate (10) comprises attaching the outer ring (104) to the package substrate (10) such that an inner distance between the inner ring (102) and the semiconductor die module (12) is greater than the outer distance between the outer ring (104) and the edge of the package substrate (10). FIG. 15, [0033], [0034]. Loo [0033] discloses the inner edge of the inner ring structure 102 is spaced away from an outer edge of the die 12; and [0034] discloses the outer ring structure 104 may have an outer perimeter edge coincident with an outer perimeter edge of organic substrate printed wire board 10, indicating an inner distance between the inner ring and the semiconductor die module is greater than the outer distance between the outer ring and the edge of the package substrate. Loo discloses that a method as taught improves warpage and stress performance during temperature cycling [0031]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kong, Kang, and Leung ’s package structure in order to improve warpage and stress performance during temperature cycling as disclosed by Loo [0031]. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Krishna J Palaniswamy whose telephone number is (571)272-6239. The examiner can normally be reached Monday - Friday 8:30AM - 5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-483-7639. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent- center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Krishna J Palaniswamy/ Examiner, Art Unit 2899 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

Jun 29, 2023
Application Filed
Oct 18, 2025
Non-Final Rejection — §103, §112
Feb 03, 2026
Response Filed
Mar 23, 2026
Final Rejection — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12521977
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING GAS BLOWING AGENT
2y 5m to grant Granted Jan 13, 2026
Study what changed to get past this examiner. Based on 1 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
58%
Grant Probability
99%
With Interview (+50.0%)
3y 6m
Median Time to Grant
Moderate
PTA Risk
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