Prosecution Insights
Last updated: April 19, 2026
Application No. 18/344,292

FLIP CHIP AND PRE-MOLDED CLIP POWER MODULES

Non-Final OA §103§112
Filed
Jun 29, 2023
Examiner
CHAMBLISS, ALONZO
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Components Industries LLC
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
65%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allow Rate
1050 granted / 1168 resolved
+21.9% vs TC avg
Minimal -25% lift
Without
With
+-25.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
24 currently pending
Career history
1192
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
35.5%
-4.5% vs TC avg
§102
36.2%
-3.8% vs TC avg
§112
14.8%
-25.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1168 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 6/29/2023 and 10/28/2024 were filed before the mailing date of the Non-final rejection on 3/12/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the a mounting bracket coupled to the DBM structure must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The disclosure is objected to because of the following informalities: since it is not clear from the specification what constitutes a mounting bracket. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 2 recites the limitation " the integrated metal routing layer " in line 2. There is insufficient antecedent basis for this limitation in the claim. In claim 2, the phrase “a mounting bracket” is vague and indefinite since it is not clear from the drawing or specification what constitute mounting bracket Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1, 3-6, 10, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yap et al. (US 2014/0008811 in view of Stella et al. (US 2021/0037674). With respect to Claims 1 and 16, Yap discloses a semiconductor die 106 and bonded to support structure 104 coupled to a first side of the semiconductor die 106. T support structure 104 configured to dissipate heat from the first side of the semiconductor die 106. A pre-molded clip assembly 126, 128 coupled to a second side of the semiconductor die. A molding compound at least partially encapsulating the semiconductor die, the top surface of the supporting structure and the pre-molded clip assembly 126, 128, to form a power module 102 (see paragraphs 15-21; Fig. 1). Yap fails to disclose a direct bonded metal (DBM) for supporting a chip and the DBM structure partially encapsulated by a molding compound. However, Stella discloses a direct bonded metal (DBM) 56 for supporting a chip 52 or 54 and the DBM structure 56 partially encapsulated by a molding compound 96 (see paragraphs 49-60; Fig. 9). Thus, Yap and Stella have substantially the same environment of a chip mounted on a supporting member, wherein the chip is encapsulated. Therefore, one skilled in the art before the effective filling date of the claimed invention substituting a DBM structure for the supporting member of Yap, since the DBM would facilitate in a reliable support while dissipating heat from the chip to the exterior of the device as taught by Stella. With respect to Claim 3, Yap discloses wherein the pre-molded clip assembly 126, 128 is an encapsulated modular unit (see Fig. 9). With respect to Claim 4, Yap discloses the pre-molded clip assembly includes an integrated metal routing layer 126 coupled to a terminal 122 of the semiconductor die (see Fig. 9). With respect to Claims 5 and 6, Stella discloses the semiconductor die is a silicon carbide (SiC) chip or an insulated gate bipolar transistor (IGBT) chip (see paragraph 2). With respect to Claim 10, Yap discloses is configured as an inverter for use in automobile or other vehicle (i.e. which can be an EV or HEV) (see paragraph 15). Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yap et al. (US 2014/0008811) and Stella et al. (US 2021/0037674) as applied to claim 1 above, and further in view of Bailley et al (US2022/0310476) and Privitera et al. (US 2016/0225699). With respect to Claim 7, Yap-Stella disclose the claimed invention except for the die is attached to both the DBM structure and the clip by an electrically conductive adhesive (see paragraph 54). Yap-Stella fail to disclose the conductive adhesive is a sintered silver. However, Bailley discloses a sintered silver which is a conductive adhesive used to attached a semiconductor device to a DBM structure and a clip (see paragraph 29). Thus, Yap-Stella and Bailley have substantially the same environment of attaching the top and bottom surfaces of a chip to other semiconductor structures in a package. Therefore, one skilled in the art before the effective filling date of the claimed invention incorporate a sintered silver as a conductive adhesive to attach the die to the clip and DBM of Yap, since the sinter silver material is a reliable material for attaching a chip to a DBC as taught by Bailley. With respect to Claims 8 and 9, Yap-Stella-Bailley disclose the claimed invention except for the die attached to the clip by PbSnAg). However, Privitera discloses attaching a chip to a clip by conductive adhesive made of PbSnAg (see paragraph 8). Thus, Yap-Stella-Bailley and Privitera have substantially the same environment of attaching a surface of a chip a clip and to another semiconductor structure. Therefore, one skilled in the art before the effective filling date of the claimed invention incorporate substituting a PbSnAg for sintered silver of Yap-Stella-Bailley, since the PbSnAg material is a reliable material for attaching a chip to a clip as taught by Privitera. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yap et al. (US 2014/0008811) and Stella et al. (US 2021/0037674) as applied to claim 1 above, and further in view of Yamada (CN 105103286). With respect to Claim 11, Yap-Stella disclose the claimed invention except for the DBM includes a Si3N4. However, Yamada discloses attaching a chip to a DBM made of Si3N4. Thus, Yap-Stella and Privitera have substantially the same environment of attaching a surface of a chip to heat dissipating structure in a semiconductor package. Therefore, one skilled in the art before the effective filling date of the claimed invention incorporate substituting a Si3N4 for the material of DBM structure of Yap-Stella, since the Si3N4 material would be a reliable material for supporting a chip in a semiconductor package as taught by Yamada. Allowable Subject Matter 13. Claims 12-15 are allowed. 14. Claims 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowance subject matter: none of the prior art of record teaches or suggest the combination of a metal routing layer centered within the encapsulant. A first metal clip coupled to a lower surface of the metal routing layer and extending through the encapsulant. A second metal clip coupled to the lower surface of the metal routing layer and extending through the encapsulant. The second metal clip spaced apart from the first metal clip by an insulating material in claim 12. Forming the pre-molded clip assembly includes forming an integrated metal routing layer therein in claim 17. The prior art made of record and not relied upon is cited primarily to show the product of the instant invention. Conclusion 15. Any inquiry concerning the communication or earlier communications from the examiner should be directed to Alonzo Chambliss whose telephone number is (571) 272-1927. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system Status information for published applications may be obtained from either Private PMR or Public PMR. Status information for unpublished applications is available through Private PMR only. For more information about the PMR system see hittp://pair-dkect.uspto gov. Should you have questions on access to the Private PMR system contact the Electronic Center (EBC) at 866-217-9197 (toll-free). AC/March 12, 2026 /Alonzo Chambliss/ Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jun 29, 2023
Application Filed
Mar 13, 2026
Non-Final Rejection — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Patent 12575079
SEMICONDUCTOR DEVICE HAVING CONCAVE LOWER SIDEWALL PORTION ON GATE STRUCTURE
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Patent 12575467
SEMICONDUCTOR PACKAGE HAVING REDUCED PARASITIC INDUCTANCE
2y 5m to grant Granted Mar 10, 2026
Patent 12575468
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2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
65%
With Interview (-25.2%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 1168 resolved cases by this examiner. Grant probability derived from career allow rate.

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