DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KWON (US 20150228747).
Regarding claim 9, KOWN discloses a semiconductor device, comprising:
a substrate (fig 12, 10, para 33) comprising a first channel region (region R2, see fig 1 and 12) and a second channel region (region R3, see fig 1 and 12);
a first gate structure (the gate in R2 comprising 50B, 60, 80B and 82B) on the first channel region, wherein the first gate structure comprises a first silicon oxide layer (silicon oxide layer 60, see fig 12, para 43) on the first channel region, a first high-k dielectric layer (high-k layer 80B, see fig 12, para 55) interfacing with the first silicon oxide layer (60 and 80B have an interface, see fig 12), and a first metal gate (gate 82B can be Cu, see fig 12, para 53 and 55) on the first high-k dielectric layer; and
a second gate structure (the gate structure comprising 50C, 60', 80C and 82C) on the second channel region, wherein the second gate structure comprises a second silicon oxide layer (50C and 60' can both be silicon oxide nitride, see fig 12, para 46 and 32) on the second channel region, a second high-k dielectric layer (80C, see fig 12, para 55) interfacing with the second silicon oxide layer (80C and 60' have an interface, see fig 12), and a second metal gate on the second high-k dielectric layer (82C, see fig 12, para 5 and 55), wherein the second silicon oxide layer is thicker than the first silicon oxide layer (the combination of 50C and 60; is thicker than 60, see fig 12, para , and a stoichiometry of O/SiOx of the first silicon oxide layer is higher than a stoichiometry of O/SiOx of a bottom portion of the second silicon oxide layer (50/60 can be stoichiometric SiO2, and the bottom portion 50C of 60' and 50C can be SiON and will thus have a smaller percentage of O in it, see fig 12, para 32 and 43).
Claim(s) 14 and 17-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SUNG (US 20170062613).
Regarding claim 14, SUNG discloses a semiconductor device, comprising:
a substrate (substrate 110, see fig 4, para 48) comprising a first semiconductor fin (the fin F1 in region I, see fig 4, para 117) and a second semiconductor fin (the fin F2 in region II, see fig 4, para 117);
an isolation region (isolation layer 112A and 112B, see fig 4, para 118 and 112A) in the substrate and laterally surrounding a lower portion of the first semiconductor fin and a lower portion of the second semiconductor fin (112A and B surround F1 and F2, see fig 4);
a liner (liner 134 and 144, see fig 4, para 51 and 118) between the isolation region and the first semiconductor fin and between the isolation region and the second semiconductor fin (134 is between 112A and F1, and 144 is between 112B and F2, see fig 2);
a first gate structure (the structure comprising 122A, 124A and 150A, see fig 4, para 96) over a first portion of the first semiconductor fin (122A is over F1, see fig 4), wherein the first gate structure comprises an interfacial layer on the first semiconductor fin (fig 4, 122A, para 96), a first high-k dielectric layer (fig 4, 124A, para 96) on the interfacial layer, and a first metal gate (fig 4, 150A, para 96) on the first high-k dielectric layer, wherein the interfacial layer has a thickness less than a thickness of the liner (the interfacial layer 122 can be 5 Angstroms thick, and the liner 134 can be 20 Angstroms thick, see para 67 and 61);
a first source/drain region over a second portion of the first semiconductor fin (the source/drain region 162A, see fig 3, para 115 and 117);
a second gate structure over a first portion of the second semiconductor fin, wherein the second gate structure comprises a gate oxide layer (fig 4, 142 and 122, para 67 and 108) on the second semiconductor fin, a second high-k dielectric layer (fig 4, 124B, para 109) on the gate oxide layer, and a second metal gate (fig 4, 150B, para 113) on the second high-k dielectric layer, wherein the gate oxide layer has a thickness greater than a thickness of the liner (142 can be 100 Ang thick and 144 can be at most 40 Ang thick, see fig 4, para 122); and
a second source/drain region over a second portion of the second semiconductor fin (the source/drain region 162B, see fig 3, para 115 and 117).
Regarding claim 17, SUNG discloses the semiconductor device of claim 14, wherein the isolation region is in contact with the gate oxide layer (112 and 142 are in direct contact, see fig 3).
Regarding claim 18, SUNG discloses the semiconductor device of claim 14, wherein the isolation region is spaced apart from the interfacial layer (112 is spaced apart from 122, see fig 3).
Regarding claim 19, SUNG discloses the semiconductor device of claim 14, wherein the liner is in contact with the first high-k dielectric layer (134 is in direct contact with 124A, see fig 3).
Regarding claim 20, SUNG discloses the semiconductor device of claim 14, wherein the liner is spaced apart from the second high-k dielectric layer (134 is spaced apart from 124B, see fig 3).
Regarding claim 21, SUNG discloses the semiconductor device of claim 14, wherein the interfacial layer interfaces with the first semiconductor fin and the first high-k dielectric layer (122A interfaces and is directly in contact with F1 and 124A, see fig 4), and
the gate oxide layer interfaces with the second semiconductor fin and the second high-k dielectric layer (122B interfaces and is directly in contact with F2 and 124B, see fig 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over LI (US 20170162383) in view of SUNG (US 20170062613).
Regarding claim 1, LI discloses a semiconductor device, comprising:
a first semiconductor fin comprising a first channel region (the left fin 201, see fig 5, para 30);
a second semiconductor fin comprising a second channel region (the right fin 201, see fig 5, para 30);
a first gate structure on the first channel region (a structure comprising the left portion of the gate structure comprising 207, 208, 209, 310, 311 and 312 in region 203, see fig 14, para 31, 55, 63, 104 and 115), wherein the first gate structure comprises a first silicon oxide layer (the oxide layer 207 and 208, see fig 14, 208, para 63) on the first channel region, a first high-k dielectric layer (fig 14, 209, para 70) on the first silicon oxide layer, and a first metal gate (fig 14, 312, para 118) on the first high-k dielectric layer; and
a second gate structure on the second channel region (a structure comprising the right portion of the gate structure comprising 207, 208, 209, 310, 311 and 312 in region 204, see fig 14, para 31, 55, 63, 104 and 115), wherein the second gate structure comprises a second silicon oxide layer (fig 14, 207, para 56) on the second channel region, a second high-k dielectric layer (fig 14, 209, para 70) on the second silicon oxide layer, and a second metal gate (fig 14, 312, para 118) on the second high-k dielectric layer,
wherein a stoichiometry of O/SiOx of the first silicon oxide layer is closer to two than a stoichiometry of O/SiOx of a bottom portion of the second silicon oxide layer (208 has a higher oxygen concentration than 207, see fig 14, para 63).
LI fails to explicitly disclose a device wherein a topmost surface of the second high-k dielectric layer is higher than a topmost surface of the first high-k dielectric layer.
SUNG teaches a device wherein a topmost surface of the second high-k dielectric layer is higher than a topmost surface of the first high-k dielectric layer (a top surface of first high-k layer 124A is higher than the top surface of second high-k layer 124B, see fig 3B, para 112).
LI and SUNG are analogous art because they both are directed towards finFET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LI with the hi-k dielectric thicknesses of SUNG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LI with the hi-k dielectric thicknesses of SUNG in order to improve performance (see SUNG para 71).
Regarding claim 2, LI and SUNG disclose the semiconductor device of claim 1.
LI further discloses a device, wherein a top surface of the first silicon oxide layer is in direct contact with the first high-k dielectric layer, and a top surface of the second silicon oxide layer is in direct contact with the second high-k dielectric layer (207 is in direct contact with 209 in both region 203 and 204, see fig 14).
Regarding claim 3, LI and SUNG disclose the semiconductor device of claim 1.
LI fails to explicitly disclose a device, wherein the second silicon oxide layer is thicker than the first silicon oxide layer.
SUNG teaches a device, wherein the second silicon oxide layer is thicker than the first silicon oxide layer (second silicon oxide layer 132 can be 100 Angstroms thick, see fig 3, para 60, and first oxide layer 122 can be 5 Angstroms thick, see fig 3, para 67).
LI and SUNG are analogous art because they both are directed towards finFET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LI with the oxide thicknesses of SUNG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LI with the oxide thicknesses of SUNG in order to improve performance (see SUNG para 71).
Regarding claim 4, LI and SUNG disclose the semiconductor device of claim 1.
LI fails to explicitly disclose a device, wherein the second silicon oxide layer is at least six times thicker than the first silicon oxide layer.
SUNG teaches a device, wherein the second silicon oxide layer is at least six times thicker than the first silicon oxide layer (second silicon oxide layer 132 can be 100 Angstroms thick, see fig 3, para 60, and first oxide layer 122 can be 5 Angstroms thick, see fig 3, para 67).
LI and SUNG are analogous art because they both are directed towards finFET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LI with the oxide thicknesses of SUNG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LI with the oxide thicknesses of SUNG in order to improve performance (see SUNG para 71).
Regarding claim 5, LI and SUNG disclose the semiconductor device of claim 1.
LI further discloses a device, wherein a top surface of the second silicon oxide layer is higher than a top surface of the first silicon oxide layer (a top surface of 207 is higher than the top surface of 208, see fig 14).
Regarding claim 6, LI and SUNG disclose the semiconductor device of claim 1.
LI fails to explicitly disclose a device, wherein a top surface of the second high-k dielectric layer is higher than a top surface of the first high-k dielectric layer.
SUNG teaches a device, wherein a top surface of the second high-k dielectric layer is higher than a top surface of the first high-k dielectric layer (top surface of second high-k dielectric layer 124A is higher than the top surface of second high-k dielectric layer 124B, see fig 3 and 5, para 68 and 111).
LI and SUNG are analogous art because they both are directed towards finFET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LI with the oxide thicknesses of SUNG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LI with the oxide thicknesses of SUNG in order to improve performance (see SUNG para 71).
Regarding claim 7, LI and SUNG disclose the semiconductor device of claim 1.
LI further discloses a device, wherein the first and second high-k dielectric layers comprise the same material (both parts of 209 can be formed of HfO2, see para 70).
Regarding claim 8, LI and SUNG disclose the semiconductor device of claim 1.
LI further discloses a device, wherein a top surface of the first metal gate is substantially coplanar with a top surface of the second metal gate (top surfaces of 312 are coplanar in 203 and 204, see fig 14, para 115).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over KWON (US 20150228747) in view of KU (US 6455405).
Regarding claim 10, KWON discloses the semiconductor device of claim 9.
KWON fails to explicitly disclose a device, wherein a Si4+ ion concentration of the first silicon oxide layer is higher than a Si4+ ion concentration of the bottom portion of the second silicon oxide layer.
KU teaches a device, wherein a Si4+ ion concentration of the first silicon oxide layer is higher than a Si4+ ion concentration of the bottom portion of the second silicon oxide layer (first, thicker oxide layer 30 has a higher Si4+ implanted concentration than thinner oxide layer 32, see fig 5, para 19).
KWON and KU are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KWON with the oxide properties of KU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KWON with the oxide properties of KU in order to simplify the process, reduce costs and form shallow junctions (see KU para 23).
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over KWON (US 20150228747) in view of SUNG ‘093 (US 6184093).
Regarding claim 12, KWON discloses the semiconductor device of claim 9.
KWON fails to explicitly disclose a device, wherein the first silicon oxide layer is substantially pin-hole free.
SUJNG ‘093 teaches a device, wherein the first silicon oxide layer is substantially pin-hole free (tunnel dielectric 1017 can be SiO or SiN and can be pinhole free, see fig 7, para 44).
KWON and SUNG ‘093 are analogous art because they both are directed towards transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KWON with the pinhole free layer of SUNG ‘093 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KWON with the pinhole free layer of SUNG ‘093 in order to make a device that can withstand numerous programming and erase cycles (see para 44).
Regarding claim 13, KWON discloses the semiconductor device of claim 9.
KWON fails to explicitly disclose a device, wherein the first high-k dielectric layer is substantially pin-hole free.
SUJNG ‘093 teaches a device, wherein the first high-k dielectric layer is substantially pin-hole free (tunnel dielectric 1017 can be SiO or SiN and can be pinhole free, see fig 7, para 44).
KWON and SUNG ‘093 are analogous art because they both are directed towards transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KWON with the pinhole free layer of SUNG ‘093 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KWON with the pinhole free layer of SUNG ‘093 in order to make a device that can withstand numerous programming and erase cycles (see para 44).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over SUNG (US 20170062613) in view of LI (US 20170162383).
Regarding claim 15, SUNG discloses the semiconductor device of claim 14.
SUNG fails to explicitly disclose a device, wherein a stoichiometry of O/SiOx of the gate oxide layer is higher than a stoichiometry of O/SiOX of the interfacial layer.
LI teaches a device, wherein a stoichiometry of O/SiOx of the gate oxide layer is higher than a stoichiometry of O/SiOX of the interfacial layer (first oxide layer 208 has a higher oxygen concentration than second oxide layer 207, see fig 14, para 63).
SUNG and LI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of SUNG with the oxide properties of LI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of SUNG with the oxide properties of LI in order to improve the finFET performance (see LI para 101).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over SUNG (US 20170062613) in view of KU (US 6455405).
Regarding claim 16, SUNG discloses the semiconductor device of claim 14.
SUNG fails to explicitly disclose a device, wherein a Si4+ ion concentration of the interfacial layer is higher than a Si4+ ion concentration of a bottom portion of the gate oxide layer.
KU teaches a device, wherein a Si4+ ion concentration of the interfacial layer is higher than a Si4+ ion concentration of a bottom portion of the gate oxide layer (first, thicker oxide layer 30 has a higher Si4+ implanted concentration than thinner oxide layer 32, see fig 5, para 19).
SUNG and KU are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of SUNG with the oxide properties of KU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of SUNG with the oxide properties of KU in order to simplify the process, reduce costs and form shallow junctions (see KU para 23).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 9 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 2/13/2026 with respect to claim 14 have been fully considered but they are not persuasive.
Regarding claim 14, the applicant argues that SUNG does not disclose a device comprising “a liner between the isolation region and the first semiconductor fin and between the isolation region and the second semiconductor fin;” because fig 3 of SUNG only discloses a liner 134 around fin F1 and not around the other fin F2. This is true, but SUNG also discloses, in another embodiment in fig 4, a device wherein there is a liner 134 and 144 around both fins F1 and F2. Thus, as fully described in the rejection above, SUNG does disclose a device comprising “a liner between the isolation region and the first semiconductor fin and between the isolation region and the second semiconductor fin;” and the applicant’s argument is unpersuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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