DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention II (method of making semiconductor device), reflected in claims 1-15, 21-25 in the reply filed on 10/23/2025 is acknowledged. Nonelected Claims 16-20 are cancelled.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-23 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 20220216340 A1, hereinafter Lin‘340).
Regarding independent claim 21, Lin‘340 teaches, “A method (fig. 1-20; ¶ [0013] - ¶ [0039]), comprising:
forming a first transistor over a substrate (202, see annotated fig. 20), the first transistor comprising:
first semiconductor sheets (2080);
a first gate structure (266P, 264, 262) surrounding each of the first semiconductor sheets (2080); and
first source/drain structures (228-2) on either side of each of the first semiconductor sheets (2080);
forming a second transistor over the first transistor, the second transistor comprising:
second semiconductor sheets (2080);
a second gate structure (266N, 264, 262) surrounding each of the second semiconductor sheets (2080); and
second source/drain structures (248-2) on either side of each of the second semiconductor sheets (2080); and
forming a source/drain contact (278) extending through one of the second source/drain structures (248-2) of the second transistor to one of the first source/drain structures (228-2) of the first transistor,
the source/drain contact (278) comprising:
a first profile (see annotation) having a first sidewall and a second sidewall opposing the first sidewall; and
a second profile (see annotation) over the first profile and having a third sidewall and a fourth sidewall opposing the third sidewall, wherein, at a boundary of the first profile and the second profile,
a width between the third sidewall and the fourth sidewall is greater than a width between the first sidewall and the second sidewall by a non-zero offset value.”
Note: Claim 21 can also be rejected using any of the below arts:
Zhang et al. (US 20190131396 A1, fig. 14), Cheng et al. (US 20230187551 A1, fig. 1) etc.
.
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Regarding claim 22, Lin‘340 further teaches, “The method of claim 21, further comprising: forming a silicide layer (274, fig. 17) over the one of the second source/drain structures (248-2), wherein the silicide layer (274) interfaces the second profile of the source/drain contact (248-2, see annotated fig. 20).
Regarding claim 23, Lin‘340 further teaches, “The method of claim 22, wherein the silicide layer (part of the silicide layer which is included in second profile) is spaced apart from the first profile of the source/drain contact”.
Regarding claim 25, Lin‘340 further teaches, “The method of claim 21, wherein along a vertical direction, a variation in the width between the first sidewall and the second sidewall of the first profile is different from a variation in the width between the third sidewall and the fourth sidewall of the second profile (second profile includes a step of silicide layer)”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-4 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20230307448 A1, hereinafter Lee‘448) in view of Xie et al. (US 20240304625 A1, hereinafter Xie‘625).
Regarding independent claim 1, Lee‘448 teaches, “A method (fig. 1-19; ¶ [0032] - ¶ [0149]), comprising:
forming a bottom-tier transistor (fig. 12A, 4A, NMOSFET/AR1, ¶ [0033]) comprising a first channel layer (CH1), a first gate structure (LGE) around the first channel layer (CH1), and a plurality of first source/drain regions (SD1) on opposite sides of the first channel layer (CH1);
forming a dielectric layer (110, fig. 12A, 10A) over the first source/drain regions (SD1) of the bottom-tier transistor (NMOSFET/AR1);
forming a top-tier transistor (PMOSFET/AR2) over the bottom-tier transistor (NMOSFET/AR1), the top-tier transistor (PMOSFET/AR2) comprising a second channel layer (CH2), a second gate structure (UGE) around the second channel layer (CH2), and a plurality of second source/drain regions (SD2) on opposite sides of the second channel layer (CH2) and over the dielectric layer (110);
etching a one of the second source/drain regions (SD2, fig. 13A) of the top-tier transistor and the dielectric layer (110) to form an opening (CTH1) exposing one of the first source/drain regions (SD1) of the bottom-tier transistor;
after forming the opening (CTH1, fig. 14A), laterally trimming the one of the second source/drain regions (SD2) of the top-tier transistor through the opening (CTH1);
((forming a metal silicide on the trimmed one of the second source/drain regions;)) and
forming a source/drain contact (AC1, fig. 16A) in the opening (CTH1)”.
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But Lee‘448 is silent upon the provision of wherein the method comprising the step of
forming a metal silicide on the trimmed one of the second source/drain regions;
However, Xie‘625 teaches a similar method of manufacturing stacked transistor comprising steps of forming contact (174, 176, fig. 8; ¶ [0091]) for source/drain (115, 114) ‘by depositing a silicide liner, such as Ni, NiPt or Ti, etc into the contact openings, depositing a metal adhesion liner, such as TiN, TaN, etc. upon the silicide liner, and by depositing a conductive metal fill, such as Al, Ru, W, Co, Cu, etc. upon the metal adhesion liner’.
Applying this step of Xie‘625 to Lee‘448, a silicide liner will be formed in the via CTH1 (fig. 14A, Lee‘448) before forming the contact AC1 shown in fig. 16A. The ‘silicide liner’ will be lining the sidewalls and bottom side of the contact via in fig. 14A. This meets the instant limitataion:
forming a metal silicide (silicide liner) on the trimmed one of the second source/drain regions (contact opening);
Lee‘448 and Xie‘715 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee‘448 with the features of Xie‘715 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Lee‘448 and Xie‘715 to include silicide liner in the contact via before forming the contact according to the teachings of Xie‘715, as this is a conventional way to reduce contact resistance, works as barrier layer to reduce metal diffusion to the S/D regions.
Regarding claim 3, Lee‘448 modified with Xie‘625 further teaches, “The method of claim 1, wherein after the laterally trimming (fig. 14A, Lee‘448), the one of the second source/drain regions (SD2) has a sidewall offset from a sidewall of the dielectric layer (110) in the opening (CTH1) by a non-zero distance”.
Regarding claim 4, Lee‘448 modified with Xie‘625 further teaches, “The method of claim 1, wherein the metal silicide is in (indirect contact) contact with a top surface of the dielectric layer (110, fig. 13A, Lee‘448) exposed from the trimmed one of the second source/drain regions”.
Regarding independent claim 11, Lee‘448 teaches, “A method (fig. 1-19; ¶ [0032] - ¶ [0149]), comprising:
forming a first semiconductive nanostructure (fig. 12A, CH1), and a second semiconductive nanostructure (CH2) vertically arranged with respect to the first semiconductive nanostructure (CH1);
forming a plurality of first epitaxial structures (SD1, ¶ [0051]) on opposite sides of the first semiconductive nanostructure (CH1), and a plurality of second epitaxial structures (SD2) on opposite sides of the second semiconductive nanostructure (CH2);
forming a dielectric layer (120, fig. 12A) over the second epitaxial structures (SD2);
forming a first gate (LGE, fig. 12A) wrapping around the first semiconductive nanostructure (CH1), and a second gate wrapping (UGE) around the second semiconductive nanostructure (CH2);
etching through the dielectric layer (110, fig. 13A) and one of the second epitaxial structures (SD2) to form an opening (CTH1) exposing the one of the first epitaxial structures (SD1);
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etching a sidewall of the one of the second epitaxial structures (SD2, fig. 14A) to create an offset from a sidewall of the dielectric layer (120) within the opening (CTH1);
((after creating the offset from the sidewall of the dielectric layer within the opening, forming a silicide on the sidewall of the one of the second epitaxial structures; )) and
filling a contact (AC1, fig. 16A) material in the opening (CTH1)”.
But Lee‘448 is silent upon the provision of wherein the method comprising the step of
after creating the offset from the sidewall of the dielectric layer within the opening, forming a silicide on the sidewall of the one of the second epitaxial structures;
However, Xie‘625 teaches a similar method of manufacturing stacked transistor comprising steps of forming contact (174, 176, fig. 8; ¶ [0091]) for source/drain (115, 114) ‘by depositing a silicide liner, such as Ni, NiPt or Ti, etc into the contact openings, depositing a metal adhesion liner, such as TiN, TaN, etc. upon the silicide liner, and by depositing a conductive metal fill, such as Al, Ru, W, Co, Cu, etc. upon the metal adhesion liner’.
Applying this step of Xie‘625 to Lee‘448, a silicide liner will be formed in the via CTH1 (fig. 14A, Lee‘448) before forming the contact AC1 shown in fig. 16A. The ‘silicide liner’ will be lining the sidewalls and bottom side of the contact via in fig. 14A. This meets the instant limitataion:
after creating the offset from the sidewall of the dielectric layer within the opening, forming a silicide (‘silicide liner’) on the sidewall of the one of the second epitaxial structures (SD2);
Lee‘448 and Xie‘715 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee‘448 with the features of Xie‘715 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Lee‘448 and Xie‘715 to include silicide liner in the contact via before forming the contact according to the teachings of Xie‘715, as this is conventional way to reduce contact resistance, works as barrier layer to reduce metal diffusion to the S/D regions.
Regarding claim 12, Lee‘448 modified with Xie‘625 further teaches, “The method of claim 11, wherein the silicide is in (indirect) contact with a bottom surface of the dielectric layer (120, fig. 12A, Lee‘448) exposed from the one of the second epitaxial structures (SD2)”.
Regarding claim 13, Lee‘448 modified with Xie‘625 further teaches, “The method of claim 11, wherein the contact material (AC1, fig. 16A, Lee‘448) is in (indirect) contact with a bottom surface of the dielectric layer (120) exposed from the one of the second epitaxial structures (SD2)”.
Regarding claim 14, Lee‘448 modified with Xie‘625 further teaches, “The method of claim 11, wherein creating the offset from the sidewall of the dielectric layer within the opening is performed ex-situ with etching through the dielectric layer and the one of the second epitaxial structures (fig. 13A, 14A, Lee‘448)”.
Claims 2, 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee‘448) and Xie‘625 as applied to claim 1 as above, and further in view of Chu et al. (US 20220262683 A1, hereinafter Chu‘683).
Regarding claim 2, Lee‘448 modified with Xie‘625 teaches all the limitations described in claim 1.
Lee‘448 further teach, wherein laterally trimming the one of the second source/drain regions (SD2, fig. 14A).
But Lee‘448 modified with Xie‘625 is silent upon the provision of wherein the trimming is performed by using a fluorine-based enchant or a chlorine-based enchant.
However, Chu‘683 teaches a lateral trimming (fig. 4; ¶ [0023]) done on similar semiconductor materials (130b) using a fluorine-based enchant or a chlorine-based enchant.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Lee‘448 modified with Xie‘625 and Chu‘683 to use dry etching to trim the semiconductor S/D regions according to the teachings of Chu‘683 with a general motivation of exploiting the advantages of this eching technique, e.g., improved control over etch profiles, reduced chemical usage/hazardous waste, and compatibility with advanced, clean, or delicate, structures etc.
Regarding claim 5, Lee‘448 modified with Xie‘625 and Chu‘683 further teaches, “The method of claim 1, wherein laterally trimming the one of the second source/drain regions is performed by an isotropic dry etching process (‘isotropic dry etching process’, Chu‘683, ¶ [0023])”.
Regarding claim 6, “The method of claim 1, wherein laterally trimming the one of the second source/drain regions is performed by a dry etching process with a bottom bias power lower than a bottom bias power used in etching the one of the second source/drain regions”, Lee‘448 modified with Xie‘625 and Chu‘683 teaches, etching and trimming the second source/drain regions using dry etching process (‘isotropic dry etching process’, ‘RF bias power’, Chu‘683, ¶ [0023]). Lee‘448 modified with Xie‘625 and Chu‘683 may not be explicitly mention the bottom bias power used in trimming process is lower than the bottom bias power used in etching the second source/drain regions. However, this is naturally recognized that the bottom bias power used in trimming process is lower than the bottom bias power used in etching the second source/drain regions as the volume of materials removed in the trimming process is smaller than the same in etching process of the second source/drain regions.
Regarding claim 7, “The method of claim 1, wherein laterally trimming the one of the second source/drain regions is performed by a dry etching process with a bottom bias power less than about 50 W/cm2”, Lee‘448 modified with Xie‘625 and Chu‘683 teaches, wherein laterally trimming the one of the second source/drain regions is performed by a dry etching process (‘isotropic dry etching process’, Chu‘683, ¶ [0023]). While the cited prior art does not explicitly disclose the particular claimed value, the teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization. The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Regarding claim 8, “The method of claim 1, wherein laterally trimming the one of the second source/drain regions is performed by introducing an oxygen precursor at a flow rate lower than a flow rate of an oxygen precursor used in etching the one of the second source/drain regions”, Lee‘448 modified with Xie‘625 and Chu‘683 teaches, etching and trimming the second source/drain regions are performed by introducing an oxygen precursor (‘oxygen-containing gas’, ¶ [0023]). Lee‘448 modified with Xie‘625 and Chu‘683 may not be explicitly mention the flow rate of oxygen precursor in the trimming process is less than the flow rate of oxygen precursor in the etching process. However, this is naturally recognized that flow rate of oxygen precursor used in trimming process is lower than the flow rate of oxygen precursor used in etching the second source/drain regions as the volume of materials removed in the trimming process is smaller than the same in etching process of the second source/drain regions.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee‘448 and Xie‘625 as applied to claim 1 as above, and further in view of Chien et al. (US 20220102274 A1, hereinafter Chien‘274).
Regarding claim 9, Lee‘448 modified with Xie‘625 teaches all the limitations described in claim 1.
Lee‘448 further teach, wherein laterally trimming the one of the second source/drain regions (SD2, fig. 14A).
But Lee‘448 modified with Xie‘625 is silent upon the provision of wherein the trimming is performed by introducing an oxygen-free precursor on the one of the second source/drain regions.
However, Chien‘274 teaches a lateral trimming (fig. 8; ¶ [0030]) done on similar semiconductor materials (130b) using dry etching without oxygen precursor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Lee‘448 modified with Xie‘625 and Chien‘274 to use dry etching to trim the semiconductor S/D regions according to the teachings of Chien‘274 with a general motivation of exploiting the advantages of oxygen-free precursor technique, e.g., prevention of unwanted oxidation of substrates, etc.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee‘448 and Xie‘625 as applied to claim 1 as above, and further in view of Zhu et al. (US 20120104466 A1, hereinafter Zhu‘466).
Regarding claim 10, Lee‘448 modified with Xie‘625 teaches all the limitations described in claim 1.
But Lee‘448 modified with Xie‘625 is silent upon the provision of wherein etching the one of the second source/drain regions and laterally trimming the one of the second source/drain regions are in-situ performed.
However, Zhu‘466 teaches a process of creating a contact for S/D (fig. 1-8), wherein etching the one of the second source/drain regions (fig. 4) and laterally trimming the one of the second source/drain regions (fig. 7) are in-situ performed (¶ [0044]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Lee‘448 modified with Xie‘625 and Zhu‘466 to use dry etching to trim the semiconductor S/D regions according to the teachings of Zhu‘466 with a general motivation of achieving reduced production costs, faster production, and improved material properties.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lee‘448 and Xie‘625 as applied to claim 1 as above, and further in view of Yamashita et al. (US 20010034138 A1, hereinafter Yamashita‘138).
Regarding claim 10, Lee‘448 modified with Xie‘625 teaches all the limitations described in claim 1.
But Lee‘448 modified with Xie‘625 is silent upon the provision of wherein creating the offset from the sidewall of the dielectric layer within the opening is performed by a dry etching process without a bias power.
However, Yamashita‘138 teaches a dry etching process without using a bias power (¶ [0059]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Lee‘448 modified with Xie‘625 and Yamashita‘138 to use dry etching without a bias power according to the teachings of Yamashita‘138 as this process ‘prevents the degradation of the electric characteristics of the semiconductor device induced by the damaged layer formed in the silicon-containing material during dry etching’. See Yamashita‘138, ¶ [0059]
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Lin‘340 as applied to claim 21 as above, and further in view of Wu et al. (US 20230420502 A1, hereinafter Wu‘502).
Regarding claim 24, Lin‘340 teaches all the limitations described in claim 21.
But Lin‘340 is silent upon the provision of wherein the source/drain contact further comprises a third profile over the second profile and having a fifth sidewall and a sixth sidewall opposing the fifth sidewall, and wherein, at a boundary of the third profile and the second profile, a width between the fifth sidewall and the sixth sidewall is less than the width between the third sidewall and the fourth sidewall.
However, Wu‘502 teaches a similar device (fig. 22), wherein the source/drain contact (192) further comprises a third profile (top portion of contact 192) over the second profile (bottom or middle portion of contact 192) and having a fifth sidewall and a sixth sidewall opposing the fifth sidewall, and wherein, at a boundary of the third profile and the second profile, a width between the fifth sidewall and the sixth sidewall (of the top portion of contact 192) is less than the width between the third sidewall and the fourth sidewall (bottom or middle portion of contact 192).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Lee‘448 and Wu‘502 to form the S/D contact of claimed shape according to the teachings of Wu‘502 with a motivation of reducing contact resistance as described by Wu‘502 in ¶ [0025] - ¶ [0029].
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817