Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because “probability” in steps 208, 214, 216 [FIG. 2] may be “prediction” and “probability” in step 210 may be “predictor” [see FIG. 1] (see, also, the following objection).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “108” has been used to designate both “prediction and gating circuitry” and “probability and gating circuitry” (see, also, the objections to the specification).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, requires the specification to be written in “full, clear, concise, and exact terms.” The specification is replete with terms which are not clear, concise and exact. The specification should be revised carefully in order to comply with 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112. Examples of some unclear, inexact or verbose terms used in the specification are: it is not clear if or how “probability” (see, for example, paragraphs [0024, 0026, 0028, 0030]) was changed from “prediction and gating circuitry 108” as depicted in FIG. 1 to “probability and gating circuitry 108” beginning at paragraph [0045] for reference character “108” and in FIG. 2 (for example, steps 208, 210, 214, 216). See, also, the following rejections.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention. Taking claim 1 as exemplary, the claim recites “prediction and gating circuitry including a predictor circuit” yet the specification and drawings appear to also describe “probability and gating circuitry” without any correlation, for example, between “prediction” and “probability.” It may appear that prediction and gating circuitry relates to “improved probability of successful prediction” as recited, for example, in paragraphs [0011, 0047, 0052] and claims 6 and 15. Yet, how “prediction and gating circuitry” (see, for example, paragraph [0042] and FIG. 2) which includes a predictor circuit (see, for example, FIG. 1 and paragraphs [0042, 0051, 0057, 0059, 0067]) satisfactorily resolved into “probability and gating circuitry” (see, for example, paragraphs [0045, 0046, 0058, 0059] and FIG. 2) is not conclusive but rather raises doubt as to possession of the claimed invention at the time of filing.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9-13 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over HUANG et al. [US 2021/0389952 A1] in view of Ham [US 2006/0132185 A1].
Taking claim 1 as exemplary of claims 1, 11, 20 [FIG. 9], Huang et al. teach a method, comprising:
for a circuit block of a circuit design [FIG. 1 multi-bit storage system 110], wherein the circuit block has a plurality of signals [In_A…In_N, Clock Signal 155, Trigger Signal 105, Trigger Enable Signal 135, Out_A…Out_N], selecting one or more signals of the plurality of signals [In_A…In_N, IN_A1, IN_A2…IN_N2, IN_N1, paragraph 0046 receive];
generating, by computer hardware, prediction and gating circuitry [prediction circuit 130 and clock gating circuit 150] including a predictor circuit [prediction circuit 130, paragraph 0018 prediction circuit 130 can be substituted by any component that can perform the functionalities] configured to generate a prediction of an output of the circuit block based on the one or more signals as selected [paragraph 0016 these components may operate together to predict whether at least one of the outputs will change a state, FIG. 2 Out_A IN_A1, In_A IN_A2, In_N IN_N2, Out_N IN_N1] and gate the circuit block based on the prediction of the output of the circuit block [FIG. 1 OUT clock gating circuit 150, paragraphs 0019-0020, paragraph 0047 generate prediction signals];
wherein the prediction and gating circuitry includes an output circuit configured as the output of the circuit block responsive to gating the circuit block by the predictor circuit [FIG. 1 OUT, EN_OUT, and Out_A … Out_N, FIGS. 2 and 5, paragraphs 0021 and 0032 components operate together, includes more, fewer, or different components, paragraphs 0047-0054 in a power efficient manner]; and
inserting, by the computer hardware, the prediction and gating circuitry within the circuit design [paragraph 0020 dynamically or adaptively enabling and disabling the clock gating circuit 150 according to predictions from the prediction circuit 130 achieves power efficiency, paragraph 0044 method of operation, paragraph 0045 determine whether output bits predicted to change, 0055 disposing the prediction circuit and the clock gating circuit, delay can be reduced].
However, Huang et al. do not appear to teach configured to substitute a constant value.
Ham teach a method comprising clock gating, wherein the circuitry is configured to substitute a constant value [paragraphs 0004 shut off the clock, outputting a constant value, 0008 provide a constant low signal to save power].
Thus, a person having ordinary skill in the art would have found it obvious to configure the output circuit to substitute a constant value as the output of the circuit block responsive to gating the circuit block by the predictor circuit because the integrated circuit design would enable the computations to be performed in a reliable, power efficient manner [Huang et al. 0001, 0014-0015].
Therefore, considering Huang et al. teach the clock gating circuit 150 can be substituted by any component that can perform the functionalities of clock gating [paragraph 0019], the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because power consumption can be reduced.
As per claim 2, physically realizing the circuit design, including the prediction and gating circuitry, within a target hardware [Huang et al. FIG. 8, paragraph 0055].
As per claims 3 and 12, wherein the one or more signals of the plurality of signals are selected based on switching activity of the plurality of signals [Huang et al. paragraphs 0015 and 0020 toggling may cause a large amount of power consumption thus clock gating to achieve power efficiency].
As per claims 4 and 13, wherein the one or more signals of the plurality of signals are selected based on an analysis of functional information for the circuit block [0001 an integrated circuit design allows an integrated circuit to perform complex functionalities, which is interpreted as a design choice].
As per claims 9 and 18, wherein a number of the one or more signals selected is less than a number of the plurality of signals [Huang et al. 0016, 0020, 0054, design choice].
As per claims 10 and 19, wherein the number of the one or more signals selected is less than or equal to a number of inputs of a selected type of primitive of a target hardware in which the circuit design is physically realized [Huang et al. 0016, 0020, 0054, 0055 design choice].
Claims 5-8 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over HUANG et al. [US 2021/0389952 A1] in view of Ham [US 2006/0132185 A1] as applied to claims 1 and 11 above, and further in view of NAKAZATO et al. [US 2012/0226953 A1].
As per claims 5 and 14, Nakazato et al. teach a method wherein the one or more signals of the plurality of signals are selected at random [0039 PRPG, 0097]. The claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains by selecting signals at random because clock gating can be feely performed [0042], thus improving the combination of references.
As per claims 6 and 15, Nakazato et al. teach a method further comprising iteratively testing different combinations of the one or more signals of the plurality of signals to determine a combination of the one or more signals that provides an improved probability of successful prediction of the output of the circuit block [0032 at any timing and in any mode, 0034 controls whether the clock signal is applied, selected signal is input, 0036 verification, 0040 repeatedly generate, 0042 predictable]. Thus, considering that Huang et al. teach that operation speed can be improved by combination in the prediction circuit [0031], the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains by selecting signals at random because clock gating can be feely performed [0042], thus improving the combination of references for success.
As per claims 7 and 16, Nakazato et al. teach a method wherein the one or more signals of the plurality of signals are selected by prioritizing control signals of the circuit block [0021-0024, 0029-0030 control-signal selection circuits 4, segment control circuit 5, 0042 known beforehand suggests prioritizing]. The claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains by selecting signals at random because clock gating can be feely performed [0042], thus improving the combination of references.
As per claims 8 and 17, Nakazato et al. teach a method wherein the one or more signals of the plurality of signals are selected by prioritizing particular bit positions of an input provided to the circuit block [0023-0024 care bits, 0042 known beforehand suggests prioritizing]. The claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains by selecting signals at random because clock gating can be feely performed [0042], thus improving the combination of references.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEIGH M GARBOWSKI whose telephone number is (571)272-1893. The examiner can normally be reached M-F 9-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LEIGH M GARBOWSKI/Primary Examiner, Art Unit 2851
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