DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 6/30/2023 and 5/16/2024 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 through 9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 through 9 of U.S. Patent No. 11,735,487 in view of Jao (US 2007/0023915).
Claim 1 of the present application overlaps claim 1 of U.S. Patent No. 11,735,487. However, claim 1 of U.S. Patent No. 11,735,487 does not teach the testing structures are not cut during the first cutting process. Jao (US 2007/0023915) teaches testing structures (fig 1,4:20[0028,0029]) that are not cut during dicing (fig 1:[0018,0019]), note Jao states that circuit is a closed loop that detects delamination or cracking by passing a current “the electric loop, which was supposed to be a closed loop, is now open, and therefore no current is measured”, if the circuit is cut or cracked during the dicing process then the circuit would not pass current.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the testing structures taught in U.S. Patent No. 11,735,487 to not be cut during the saw process so that the testing structures can be used to evaluate delamination.
Application 18/344,857
US 11,735,487
1. A method, comprising: providing a semiconductor wafer comprising integrated circuit components, seal rings respectively encircling the integrated circuit components and testing structures disposed between the seal rings;
1. A method, comprising: providing a semiconductor wafer comprising integrated circuit components, seal rings respectively encircling the integrated circuit components and testing structures disposed between the seal rings;
performing a first cutting process at least along a first path to singulate the semiconductor wafer into a plurality of singulated integrated circuit components each comprising a testing structure among the testing structures,
performing a first wafer saw process at least along a first path to singulate the semiconductor wafer into a plurality of first singulated integrated circuit components each comprising a testing structure among the testing structures,
wherein the testing structures are not cut by a blade used in the first cutting process,
wherein, when performing the first wafer saw process, testing pads of the testing structures are located beside the first path,
such that one testing structure among the testing structures distributed in the singulated integrated circuit component is laterally spaced apart from a sidewall of the singulated integrated circuit component;
such that a testing pad of a corresponding one of the testing structures in the first singulated integrated circuit component is laterally spaced apart from a sidewall of the first singulated integrated circuit component by a distance;
and performing a second cutting process along a second path between the testing structures and the seal rings to cut the testing structures from the singulated integrated circuit components.
And performing a second wafer saw process along a second path between the testing structures and the seal rings to cut the testing structures from the first singulated integrated circuit components to obtain a plurality of second singulated integrated circuit components.
Claims 2 through 9 of application 18/344,857 are substantially the same as claims 2 through 9 of US 11,735,487.
Application 18/344,857
US 11,735,487
2. The method as claimed in claim 1, wherein providing the semiconductor wafer comprises: forming stacked structures of the testing structures over a semiconductor substrate; and forming the testing pads on the stacked structures.
2. The method as claimed in claim 1, wherein providing the semiconductor wafer comprises: forming stacked structures of the testing structures over a semiconductor substrate; and forming the testing pads on the stacked structures.
3. The method as claimed in claim 2, wherein providing the semiconductor wafer further comprises: forming interconnect wirings of the integrated circuit components over the semiconductor substrate; and forming conductive pads on the interconnect wirings, wherein the interconnect wirings and the stacked structures of the testing structures are concurrently formed at a first level height, and the conductive pads and the testing pads of the testing structures are concurrently formed at a second level height.
3. The method as claimed in claim 2, wherein providing the semiconductor wafer further comprises: forming interconnect wirings of the integrated circuit components over the semiconductor substrate; and forming conductive pads on the interconnect wirings, wherein the interconnect wirings and the stacked structures of the testing structures are concurrently formed at a first level height, and the conductive pads and the testing pads of the testing structures are concurrently formed at a second level height.
4. The method as claimed in claim 2, wherein materials of the testing pads and the stacked structures are different.
4. The method as claimed in claim 2, wherein materials of the testing pads and the stacked structures are different.
5. The method as claimed in claim 2, wherein the stacked structures of the testing structures are located beside the first path and keep a distance from the first path, such that a stacked structure of the testing structure in the singulated integrated circuit component is laterally spaced apart from the sidewall of the singulated integrated circuit component.
5. The method as claimed in claim 2, wherein the stacked structures of the testing structures are located beside the first path and keep a distance from the first path, such that a stacked structure of the testing structure in the first singulated integrated circuit component is laterally spaced apart from the sidewall of the first singulated integrated circuit component.
6. The method as claimed in claim 2, wherein the stacked structures of the testing structures are not revealed at the sidewall of the singulated integrated circuit component.
6. The method as claimed in claim 2, wherein the stacked structures of the testing structures are not revealed at the sidewall of the first singulated integrated circuit component.
7. The method as claimed in claim 1, wherein the first path is laterally spaced apart from the second path.
7. The method as claimed in claim 1, wherein the first path is laterally spaced apart from the second path.
8. The method as claimed in claim 1, further comprising: performing a testing process to qualify the integrated circuit components by testing the testing structures; and according to the testing process, bonding a qualified singulated integrated circuit component among the singulated integrated circuit components to a semiconductor device.
8. The method as claimed in claim 1, further comprising: performing a testing process to qualify the integrated circuit components by testing the testing structures; and according to the testing process, bonding a qualified first singulated integrated circuit component among the first singulated integrated circuit components to a semiconductor device.
9. The method as claimed in claim 1, wherein the second cutting process is performed using a blade.
9. The method as claimed in claim 1, wherein the first wafer saw process is performed using a blade.
Claims 10 through 12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 through 12 of U.S. Patent No. 11,735,487 in view of Jao (US 2007/0023915).
Claim 10 of the present application overlaps claim 10 of U.S. Patent No. 11,735,487. However, claim 10 of U.S. Patent No. 11,735,487 does not teach the testing structures are not in contact with the blade used in the second cutting process. Jao (US 2007/0023915) teaches testing structures (fig 1,4:20[0028,0029]) that are not in contact with the blade used in the cutting process (fig 1:[0018,0019]), note Jao states that circuit is a closed loop that detects delamination or cracking by passing a current “the electric loop, which was supposed to be a closed loop, is now open, and therefore no current is measured”, if the circuit is cut or cracked during the dicing process then the circuit would not pass current.. Further, Jao teaches cutting is performed using a blade during the wafer dicing process ([para 0019])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the testing structures taught in U.S. Patent No. 11,735,487 to not be cut during the saw process so that the testing structures can be used to evaluate delamination.
Application 18/344,857
US 11,735,487
10. A method, comprising: providing a semiconductor wafer comprising integrated circuit components, seal rings respectively encircling the integrated circuit components and testing structures disposed between the seal rings;
10. A method, comprising: providing a semiconductor wafer comprising integrated circuit components, seal rings respectively encircling the integrated circuit components and testing structures disposed between the seal rings;
performing a first cutting process at least to singulate the semiconductor wafer into a plurality of singulated integrated circuit components;
performing a first wafer saw process at least along a first path to singulate the semiconductor wafer into a plurality of first singulated integrated circuit components;
and performing a second cutting process along a path between the testing structures and the seal rings to remove the testing structures from the singulated integrated circuit components,
and performing a second wafer saw process along a second path between the testing structures and the seal rings to cut the testing structures from the first singulated integrated circuit components to obtain a plurality of second singulated integrated circuit components.
wherein the second cutting process is performed using a blade,
(a wafer saw process is a cutting process using a blade)
and the testing structures are not in contact with the blade used in the second cutting process.
Claims 11 and 12 of application 18/344,857 are substantially the same as claims 11 and 12 of US 11,735,487.
Application 18/344,857
US 11,735,487
11. The method as claimed in claim 10, wherein the testing structures are not in contact with a blade used in the first cutting process.
11. The method as claimed in claim 10, wherein the testing structures are not in contact with a blade used in the first wafer saw process.
12. The method as claimed in claim 10, wherein providing the semiconductor wafer further comprises: concurrently forming interconnect wirings of the integrated circuit components and stacked structures of the testing structures over a semiconductor substrate at a first level height; and forming conductive pads on the interconnect wirings at a second level height.
12. The method as claimed in claim 10, wherein providing the semiconductor wafer further comprises: concurrently forming interconnect wirings of the integrated circuit components and stacked structures of the testing structures over a semiconductor substrate at a first level height; and forming conductive pads on the interconnect wirings at a second level height.
Claims 14 through 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 through 12 of U.S. Patent No. 11,735,487 in view of Jao (US 2007/0023915).
Claim 14 and 15 of the present application overlaps claims 14 and 15 of U.S. Patent No. 11,735,487. However, claim 14 of U.S. Patent No. 11,735,487 does not teach the testing structures are offset from the cutting path. Jao (US 2007/0023915) teaches testing structures (fig 1,4:20[0028,0029]) that are offset from the cutting path (fig 1:[0018,0019]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the testing structures taught in U.S. Patent No. 11,735,487 to not be cut during the saw process so that the testing structures can be used to evaluate delamination.
Application 18/344,857
US 11,735,487
14 (a). A method, comprising: providing a semiconductor wafer comprising integrated circuit components and testing structures;
14. A method, comprising: providing a semiconductor wafer comprising integrated circuit components and testing structures disposed between the integrated circuit components;
14(b). and performing a cutting process to singulate the semiconductor wafer into a plurality of first pieces and a plurality of second pieces, wherein each of the first pieces respectively comprises one integrated circuit component among the integrated circuit components, and each of the second pieces respectively comprises at least one testing structure among the testing structures,
and performing a wafer saw process to singulate the semiconductor wafer into a plurality of singulated integrated circuit components and a plurality of pieces, wherein each of the singulated integrated circuit components respectively comprises one integrated circuit component among the integrated circuit components, and each of the pieces respectively comprises at least one testing structure among the testing structures,
15 (a). The method as claimed in claim 14, wherein performing the cutting process comprises: performing a first cutting process at least along a first path to singulate the semiconductor wafer into a plurality of singulated structures, wherein each of the singulated structures respectively comprises one integrated circuit component among the integrated circuit components and at least one testing structure among the testing structures;
wherein performing the wafer saw process comprises: performing a first wafer saw process at least along a first path to singulate the semiconductor wafer into a plurality of singulated structures, wherein each of the singulated structures respectively comprises one integrated circuit component among the integrated circuit components and at least one testing structure among the testing structures;
15(b) and after performing the first cutting process, performing a second cutting process along a second path to cut the testing structures from the singulated structures to obtain the first pieces and the second pieces.
and after performing the first wafer saw process, performing a second wafer saw process along a second path to cut the testing structures from the singulated structures to obtain the pieces and the singulated integrated circuit components.
14(c) wherein the testing structures are arranged along a path which is offset from a cutting path of the cutting process.
15. The method as claimed in claim 14, wherein the first path is spaced apart from the second path.
Claims 16 through 20 of application 18/344,857 are substantially the same as claims 16 through 20 of US 11,735,487.
Application 18/344,857
US 11,735,487
16. The method as claimed in claim 15, wherein during the first cutting process, the testing structures are not in contact with a blade used in the first cutting process.
16. The method as claimed in claim 14, wherein during the first wafer saw process, the testing structures are not in contact with a blade used in the first wafer saw process.
17. The method as claimed in claim 15, wherein during the second cutting process, the testing structures are not in contact with a blade used in the second cutting process.
17. The method as claimed in claim 14, wherein during the second wafer saw process, the testing structures are not in contact with a blade used in the second wafer saw process.
18. The method as claimed in claim 14, wherein the testing structures in the singulated structures are not revealed at sidewalls of the singulated structures after performing the first cutting process.
18. The method as claimed in claim 14, wherein the testing structures in the singulated structures are not revealed at sidewalls of the singulated structures after performing the first wafer saw process.
19. The method as claimed in claim 14, wherein the testing structures in the pieces are not revealed at sidewalls of the pieces after performing the second cutting process.
19. The method as claimed in claim 14, wherein the testing structures in the pieces are not revealed at sidewalls of the pieces after performing the second wafer saw process.
20. The method as claimed in claim 14, wherein the first cutting process and the second cutting process are performed using a blade.
20. The method as claimed in claim 14, wherein the first wafer saw process and the second wafer saw process are performed using a blade.
Claims 10 and 13 are rejected on the grounds of nonstatutory double patenting as being unpatentable over claims 1 and 8 of U.S. Patent No. 11,735,487 in view of Jao (US 2007/0023915).
Claim 10 of the present application overlaps claim 1 of U.S. Patent No. 11,735,487. However, claim 10 of U.S. Patent No. 11,735,487 does not teach the testing structures are not in contact with the blade. Jao (US 2007/0023915) teaches testing structures (fig 1,4:20[0028,0029]) that are not in contact with the blade (fig 1:[0018,0019]) note Jao states that circuit is a closed loop that detects delamination or cracking by passing a current “the electric loop, which was supposed to be a closed loop, is now open, and therefore no current is measured”, if the circuit is cut or cracked during the dicing process then the circuit would not pass current..
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the testing structures taught in U.S. Patent No. 11,735,487 to not be cut during the saw process so that the testing structures can be used to evaluate delamination.
Application 18/344,857
US 11,735,487
10. A method, comprising: providing a semiconductor wafer comprising integrated circuit components, seal rings respectively encircling the integrated circuit components and testing structures disposed between the seal rings;
1. A method, comprising: providing a semiconductor wafer comprising integrated circuit components, seal rings respectively encircling the integrated circuit components and testing structures disposed between the seal rings;
performing a first cutting process at least to singulate the semiconductor wafer into a plurality of singulated integrated circuit components;
performing a first wafer saw process at least along a first path to singulate the semiconductor wafer into a plurality of first singulated integrated circuit components each comprising a testing structure among the testing structures, wherein, when performing the first wafer saw process, testing pads of the testing structures are located beside the first path, such that a testing pad of a corresponding one of the testing structures in the first singulated integrated circuit component is laterally spaced apart from a sidewall of the first singulated integrated circuit component by a distance;
and performing a second cutting process along a path between the testing structures and the seal rings to remove the testing structures from the singulated integrated circuit components, wherein the second cutting process is performed using a blade,
and performing a second wafer saw process along a second path between the testing structures and the seal rings to cut the testing structures from the first singulated integrated circuit components to obtain a plurality of second singulated integrated circuit components.
and the testing structures are not in contact with the blade used in the second cutting process
Claim 13 of application 18/344,857 are substantially the same as claim 8 of US 11,735,487.
Application 18/344,857
US 11,735,487
13. The method as claimed in claim 10, further comprising: performing a testing process to qualify the singulated integrated circuit components by testing the testing structures; and according to the testing process, bonding a qualified singulated integrated circuit component among the singulated integrated circuit components to a semiconductor device.
8. The method as claimed in claim 1, further comprising: performing a testing process to qualify the integrated circuit components by testing the testing structures; and according to the testing process, bonding a qualified first singulated integrated circuit component among the first singulated integrated circuit components to a semiconductor device.
Claim Objections
Claims 10, 11, 12, 13, 16 and 17 are objected to because of the following informalities:
Claim 10 recites “the testing structures are not in contact with the blade used in the first cutting process” in lines 9 and 10. The examiner suggests “the testing structures do not contact the blade during the second cutting process.” in order to be supported by the specification (US pgpub [para 0062]).
Claim 11 recites “the testing structures are not in contact with a blade used in the first cutting process” in lines 1 and 10. The examiner suggests “the testing structures do not contact a blade during the first cutting process.” in order to be supported by the specification (US pgpub [para 0062]).
Claims 12 and 13 depend from and incorporate claim 10.
Claim 16 recites “the testing structures are not in contact with a blade” in line 2. The examiner suggests that the applicant may have intended “the testing structures do not contact a blade during the first cutting process” in order to be supported by the specification (US pgpub [para 0062]).
Claim 17 recites “the testing structures are not in contact with a blade” in line 2. The examiner suggests that the applicant may have intended “the testing structures do not contact a blade during the second cutting process” in order to be supported by the specification (US pgpub [para 0062]).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 19, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the testing pads" in line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 recites the limitation "the second cutting process" in line 2. There is insufficient antecedent basis for this limitation in the claim. The examiner will assume the applicant intended for claim 19 to depend from claim 15.
Claim 19 recites the limitation "the pieces" in lines 1 and 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 20 recites the limitation "the second cutting process" in lines 1 and 2. There is insufficient antecedent basis for this limitation in the claim. The examiner will assume the applicant intended for claim 20 to depend from claim 15.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 14 and 18 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Iwafuchi (US 2018/0240832)
Regarding claim 14.
Iwafuchi teaches a method, comprising: providing a semiconductor wafer (fig 1:11; [0044]) comprising integrated circuit components (fig 1:31; [0046]) and testing structures (fig 1:61; [0051]); and performing a cutting process (fig 1; [0047]) to singulate the semiconductor wafer (fig 1:11; [0048] into a plurality of first pieces (fig 1:21-1 to 21-6; [0044]) and a plurality of second pieces (fig 1:52; [0047]), wherein each of the first pieces (fig 1:21; [0044]) respectively comprises one integrated circuit component (fig 1:31; [0046]) among the integrated circuit components, and each of the second pieces (fig 1:52; [0047]) respectively comprises at least one testing structure (fig 1:61; [0051]) among the testing structures, wherein the testing structures (fig 1:61; [0050]) are arranged along a path which is offset from a cutting path (fig 1:51; [0048]) of the cutting process (fig 1; [0047]).
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Regarding claim 18, Iwafuchi teaches the method as claimed in claim 14, further: wherein the testing structures (fig 1:61[0050]) in the singulated structures are not revealed at sidewalls of the singulated structures after performing the first cutting process ([0047,0048]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 February 25, 2026