DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/5/2026 was filed after the mailing date of the non-final rejection on 2/27/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Status
Previous action: claims 1 through 20 rejected
Present action: claims 1 through 13 allowed, claims 15 through 20 objected, claim 14 rejected.
Terminal Disclaimer
Terminal disclaimer received 6/25/2026 has been received and approved.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 14 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Iwafuchi (US 2018/0240832).
Regarding claim 14.
Iwafuchi teaches:
A method, comprising: providing a semiconductor wafer (fig 1:11; [para 0044]) comprising integrated circuit components (fig 1:31; [para 0046]) and testing structures (fig 1:61; [para 0051]);
and performing a cutting process (fig 1; [para 0047]) to singulate the semiconductor wafer (fig 1:11; [para 0044]) into a plurality of first pieces (fig 1 annotated)and a plurality of second pieces (fig 1 annotated) separated from the first pieces (fig 1 annotated), wherein one of the first pieces (fig 1 annotated) comprises one integrated circuit component (fig 1:31; [para 0046]) among the integrated circuit components (fig 1:31; [para 0046]), and one of the second pieces (fig 1 annotated) comprises at least one testing structure (fig 1:61; [para 0051]) among the testing structures (fig 1:61; [para 0051]), wherein the testing structures (fig 1:61; [para 0051]) are arranged along a path which is offset from a cutting path of the cutting process (fig 1; [para 0047]).
PNG
media_image1.png
678
903
media_image1.png
Greyscale
Response to Arguments
The submitted terminal disclaimer overcomes the previously applied double patenting rejection in view of UD 11,735.487.
The submitted amendments to the claims overcome the previously applied objections and 112 2nd paragraph antecedence rejections.
Applicant's arguments filed 6/28/2026 have been fully considered but they are not persuasive.
The applicant argues that the amendments to claim 14 overcome Iwafuchi (US 2018/0240832).
However, as shown in the rejection above, the amendments do not overcome the applied reference.
Allowable Subject Matter
Claims 1 through 13 are allowed.
Claims 15 through 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, the prior art does not teach, in combination with other elements of the claim, a method, comprising: performing a first cutting process at least along a first path to singulate the semiconductor wafer into a plurality of singulated integrated circuit components each comprising a testing structure among the testing structures, wherein the testing structures are not cut by a blade used in the first cutting process, such that one testing structure among the testing structures distributed in the singulated integrated circuit component is laterally spaced apart from a sidewall of the singulated integrated circuit component; and performing a second cutting process along a second path between the testing structures and the seal rings to cut the testing structures from the singulated integrated circuit components.
Regarding claim 10, the prior art does not teach, in combination with other elements of the claim, a method, comprising: performing a first cutting process at least to singulate the semiconductor wafer into a plurality of singulated integrated circuit components; and performing a second cutting process along a path between the testing structures and the seal rings to remove the testing structures from the singulated integrated circuit components, wherein the second cutting process is performed using a blade, and the testing structures do not contact the blade during used in the second cutting process.
Regarding claim 15, the prior art does not teach, in combination with other elements of the claim, a method, comprising: performing a first cutting process at least along a first path to singulate the semiconductor wafer into a plurality of singulated structures, wherein each of the singulated structures respectively comprises one integrated circuit component among the integrated circuit components and at least one testing structure among the testing structures; and after performing the first cutting process, performing a second cutting process along a second path to cut the testing structures from the singulated structures to obtain the first pieces and the second pieces.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.J.G/Examiner, Art Unit 2817
/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
Prosecution Insights