DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 30 Jun 2023 for application number 18/344,860. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and Claims.
Claims 1-26 presented for examination. Elected claims 1-14 and 21-26 are examined below. Non-elected claims 15-20 have been withdrawn
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 30 Jun 2023 were filed before the mailing of this Office Action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of claims 1-14, drawn to Invention I. in the reply filed on 28 Jan 2026 is acknowledged. Further, claims 21-26 have been added.
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II., there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 28 Jan 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 8-9, 11-12, 21-22, and 25-26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. [hereinafter as Chang] (US 2023/0118990 A1).
In reference to claim 1, Chang teaches A semiconductor device, comprising:
a semiconductor substrate [substrate 100; Fig. 16, para 0012];
semiconductor nanosheets [nanosheets 116; Fig. 16, para 0017] vertically stacked upon one another, disposed above the semiconductor substrate [100], and serving as channel regions;
a gate structure [WFM layer 160; Fig. 16, para 0038] surrounding each of the semiconductor nanosheets [116];
inner spacers [inner spacer 132; Fig. 16, para 0027] laterally covering the gate structure [160] and interposed between the semiconductor nanosheets [116], wherein a bottommost inner spacer of the inner spacers underlying a bottommost semiconductor nanosheet of the semiconductor nanosheets is thinner than a topmost inner spacer of the inner spacers underlying a topmost semiconductor nanosheet of the semiconductor nanosheets [bottommost 132 is thinner than topmost 132; Fig. 16]; and
source/drain (S/D) regions [S/D regions 140; Fig. 16, para 0012] disposed over the semiconductor substrate [100] and laterally abutting the semiconductor nanosheets [116], the S/D regions [140] being separated from the gate structure [160] through the inner spacers [132].
In reference to claim 2, Chang teaches The semiconductor device of claim 1, wherein a bottommost gate section of the gate structure laterally surrounded by the bottommost inner spacer comprises a lateral dimension greater than a lateral dimension of a topmost gate section of the gate structure laterally surrounded by the topmost inner spacer [width, i.e. lateral dimension, of bottommost 160 is greater than width of topmost 160; Fig. 16].
In reference to claim 3, Chang teaches The semiconductor device of claim 1, wherein the semiconductor substrate [100] comprises: a doped layer [para 0012 discloses that 100 may be doped] physically connected to the S/D regions [140] and the bottommost inner spacer [bottommost 132].
In reference to claim 8, Chang teaches The semiconductor device of claim 1, wherein the bottommost inner spacer [bottommost 132] comprises a curved sidewall concave [bottommost 132 concave towards 140] toward the S/D regions [140].
In reference to claim 9, Chang teaches The semiconductor device of claim 8, the bottommost semiconductor nanosheet [bottommost 116] comprises a tilted sidewall [bottommost 116 sidewall is tilted] connected to the curved sidewall of the bottommost inner spacer [bottommost 132] and laterally adjoining the S/D regions [140].
In reference to claim 11, Chang teaches A semiconductor device, comprising:
a semiconductor substrate [substrate 100; Fig. 16, para 0012]; and
a device layer [semiconductor stack 102; Fig. 16, para 0013] disposed on the semiconductor substrate [100], the device layer comprising:
channel regions [channel members 116; Fig. 16, para 0037] vertically stacked upon one another;
a gate structure [gate dielectric 152/WFM layer 160/gate spacer 128; Fig. 16, paras 0025, 0037-0038] surrounding each of the channel regions [116], the gate structure [152/160/128] comprising a topmost gate section [topmost 160] and a bottommost gate section [bottommost 160] between the topmost gate section [topmost 160] and the semiconductor substrate [100], and a lateral dimension of the bottommost gate section [bottommost 160] being greater than [width of bottommost 160 is greater than width of topmost most 160; Fig. 16] that of the topmost gate section [topmost 160];
S/D regions [S/D regions 140; Fig. 16, para 0012] disposed on the semiconductor substrate [100] and laterally coupled to the channel regions [116]; and
inner spacers [inner spacer 132; Fig. 16, para 0027] laterally separating the S/D regions [140] from the gate structure [160/152/128].
In reference to claim 12, Chang teaches The semiconductor device of claim 11, wherein the inner spacers [132] comprises: a topmost inner spacer [topmost 132] laterally surrounding the topmost gate section [topmost 160]; and a bottommost inner spacer [bottommost 132] laterally surrounding the bottommost gate section [bottommost 160], wherein the bottommost inner spacer is thinner than the topmost inner spacer [bottommost 132 is thinner than topmost 132; Fig. 16].
In reference to claim 21, Chang teaches A semiconductor device, comprising:
a doped layer [semiconductor stack 102; Fig. 16, para 0013] overlying a semiconductor substrate [bottom portion of substrate 100; Fig. 16, para 0012]; a first gate section [bottommost WFM layer 160, below bottommost channel member 116; Fig. 16, para 0038] overlying a fin [fin 110; Fig. 16, para 0017] of the doped layer [102];
a first inner spacer [inner spacer 132, for example, bottommost 132; Fig. 16, para 0027] overlying the fin [110] of the doped layer [102] and laterally surrounding the first gate section [bottommost 160, below bottommost 116];
a first channel layer [channel members 116, for example, bottommost 116; Fig. 16, para 0037] overlying the first gate section [bottommost 160, below bottommost 116] and the first inner spacer [bottommost 132];
S/D regions [S/D regions 140; Fig. 16, para 0012] disposed over a recess of the doped layer [102] and coupled to the first inner spacer [bottommost 132] and the first channel layer [bottommost 116] in a first direction; and
a second inner spacer [for example, topmost 132] disposed on the first channel layer [bottommost 116], wherein a first lateral dimension of the first inner spacer [bottommost 132] measured in the first direction is less than [bottommost 132 is thinner than topmost 132; Fig. 16] a second lateral dimension of the second inner spacer [for example, topmost 132] measured in the first direction.
In reference to claim 22, Chang teaches The semiconductor device of claim 21, further comprising: a second gate section [for example, topmost 160] overlying the first channel layer [bottommost 116] and surrounded by the second inner spacer [topmost 132] in the first direction, wherein a third lateral dimension of the first gate section [bottommost 160] measured in the first direction is greater than [width of bottommost 160 is greater than width of topmost 160] a fourth lateral dimension of the second gate section [topmost 160] measured in the first direction.
In reference to claim 25, Chang teaches The semiconductor device of claim 21, wherein the recess of the doped layer [102] comprises a surface concaved [recess of 102 is concaved toward 100; Fig. 16] toward the semiconductor substrate [100], and the S/D regions [140] are disposed over the surface.
In reference to claim 26, Chang teaches The semiconductor device of claim 21, wherein the semiconductor substrate comprises a p-type region and an n-type region [n and p-type regions of 140; paras 0029-0030], and a doping concentration of the doped layer overlying the p-type region is different from a doping concentration of the doped layer overlying the n-type region [paras 0029-0030 disclose n and p-type regions and varying doping concentrations].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4-7, 13-14, and 23-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Chang et al. [hereinafter as Lin] (US 2022/0336612 A1).
In reference to claim 4, Chang teaches the invention of claim 1.
However, Chang does not explicitly teach The semiconductor device of claim 1, further comprising: a bottom isolation structure vertically interposed between the semiconductor substrate and the S/D regions.
Lin teaches a bottom isolation structure [bottom dielectric region 112; Fig. 2P, para 0020] vertically interposed between the semiconductor substrate [semiconductor substrate 102; Fig. 2P, para 0018] and the S/D regions [source/drain region 110; Fig. 2P, para 0019].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Chang and Lin before the effective filing date of the claimed invention, to include the bottom isolation structure as disclosed by Lin into the nanosheet semiconductor device of Chang in order to obtain a nanosheet semiconductor device with a bottom isolation structure.
One of ordinary skill in the art would be motivated to obtain a nanosheet semiconductor device with a bottom isolation structure to provide the predictable result of ensuring leakage currents do not flow from source/drain regions into the semiconductor substrate, thereby greatly enhancing efficiency and reducing power consumption and heat generation [Lin, para 0021].
In reference to claim 5, Chang and Lin teach the invention of claim 4.
Lin further teaches The semiconductor device of claim 4, wherein the bottom isolation structure [112] physically connected to at least a lower region of the bottommost inner spacer [bottommost inner spacer layer 148; Fig. 2P, para 0050].
In reference to claim 6, Chang and Lin teach the invention of claim 4.
Lin further teaches The semiconductor device of claim 4, wherein the semiconductor substrate [semiconductor substrate 102; Fig. 2P, para 0018] comprises a p-type region [102 of first transistor 106 (which is P-type); Fig. 2P, para 0025] and an n-type region [102 of first transistor 104 (which is N-type); Fig. 2P, para 0025], and the bottom isolation structure [112] is disposed in at least one selected from a group of the p-type region and the n-type region [112 is present in 104 but not 106; para 0024].
In reference to claim 7, Chang and Lin teach the invention of claim 4.
Lin further teaches The semiconductor device of claim 4, further comprising: an epitaxial structure [epitaxial semiconductor regions 152/154; Fig. 2P, para 0051] vertically interposed between the semiconductor substrate [102] and the bottom isolation structure [112], the epitaxial structure [152/154] being substantially dopant-free [152/154 may be undoped; para 0052].
In reference to claim 13, Chang teaches the invention of claim 11.
However, Chang does not explicitly teach The semiconductor device of claim 11, wherein the semiconductor substrate comprises: a doped layer physically connected to the S/D regions and the bottommost gate section.
Lin teaches wherein the semiconductor substrate comprises: a doped layer [bottom dielectric region 112; Fig. 2P, para 0020; paras 0056-0057 disclose that dielectric layer 156 (with which 112 is made) is doped] physically connected to the S/D regions [source/drain region 110; Fig. 2P, para 0019] and the bottommost gate section [bottommost gate line layer 186/gate fill material 188/inner spacer 148; Fig. 2P, paras 0079, 0050].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Chang and Lin before the effective filing date of the claimed invention, to include the doped layer as disclosed by Lin into the nanosheet semiconductor device of Chang in order to obtain a nanosheet semiconductor device with a doped layer.
One of ordinary skill in the art would be motivated to obtain a nanosheet semiconductor device with a doped layer to provide the predictable result of ensuring leakage currents do not flow from source/drain regions into the semiconductor substrate, thereby greatly enhancing efficiency and reducing power consumption and heat generation [Lin, para 0021].
In reference to claim 14, Chang teaches the invention of claim 11.
However, Chang does not explicitly teach The semiconductor device of claim 11, further comprising: a bottom isolation structure vertically separating the S/D regions from the semiconductor substrate.
Lin teaches a bottom isolation structure [bottom dielectric region 112; Fig. 2P, para 0020] vertically separating the S/D regions [source/drain region 110; Fig. 2P, para 0019] from the semiconductor substrate [semiconductor substrate 102; Fig. 2P, para 0018].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Chang and Lin before the effective filing date of the claimed invention, to include the bottom isolation structure as disclosed by Lin into the nanosheet semiconductor device of Chang in order to obtain a nanosheet semiconductor device with a bottom isolation structure.
One of ordinary skill in the art would be motivated to obtain a nanosheet semiconductor device with a bottom isolation structure to provide the predictable result of ensuring leakage currents do not flow from source/drain regions into the semiconductor substrate, thereby greatly enhancing efficiency and reducing power consumption and heat generation [Lin, para 0021].
In reference to claim 23, Chang teaches the invention of claim 21.
However, Chang does not explicitly teach The semiconductor device of claim 21, wherein the S/D regions comprise an undoped region interfaced with the doped layer.
Lin teaches wherein the S/D regions comprise an undoped region [epitaxial semiconductor region 152/154; Fig. 2P, para 0052 disclose that 152/154 may be undoped] interfaced with the doped layer [fins in which channel region 107 are; Fig. 2P, para 0019].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Chang and Lin before the effective filing date of the claimed invention, to include the undoped region as disclosed by Lin into the nanosheet semiconductor device of Chang in order to obtain a nanosheet semiconductor device with an undoped region.
One of ordinary skill in the art would be motivated to obtain a nanosheet semiconductor device with an undoped region to provide the predictable result of preventing leakage currents and minimize parasitic capacitance.
In reference to claim 24, Chang and Lin teach the invention of claim 23.
Lin teaches The semiconductor device of claim 23, wherein the undoped region [152/154] is interfaced with the doped layer [fins in which 107 are] in the first direction [into and out of the page; Fig. 2P] and a second direction [vertical direction; Fig. 2P], and the second direction is a thickness direction of the semiconductor substrate [semiconductor substrate 102; Fig. 2P, para 0018].
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Ando et al. [hereinafter as Ando] (US 2021/0328013 A1).
In reference to claim 10, Chang teaches the invention of claim 1.
However, Chang does not explicitly teach The semiconductor device of claim 1, wherein the semiconductor substrate comprises a p-type region and an n-type region, and a thickness of the bottommost inner spacer in the p-type region is different from that of the bottommost inner spacer in the n-type region.
Ando teaches wherein the semiconductor substrate comprises a p-type region [Fig. 11B, para 0061] and an n-type region [Fig. 10B, para 0061], and a thickness of the bottommost inner spacer [bottommost inner spacer 111; Fig. 11B, para 0061] in the p-type region is different from that of the bottommost inner spacer [bottommost inner spacer 111; Fig. 10B, para 0061] in the n-type region [thickness of bottommost inner spacers 111 of n-type and p-type regions is different; Figs. 10-11A-B].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Chang and Ando before the effective filing date of the claimed invention, to include the different inner spacers as disclosed by Ando into the nanosheet semiconductor device of Chang in order to obtain a nanosheet semiconductor device with different inner spacer thickness between n and p-type regions.
One of ordinary skill in the art would be motivated to obtain a nanosheet semiconductor device with different inner spacer thickness between n and p-type regions to provide the predictable result of accommodating for the characteristics of a low-voltage device [Ando, paras 0067-0073].
Examiner’s Note
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure as follows. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR § 1.111(0).
Lin et al. (US-11923409-B2) discloses varying inner spacer/void widths [Fig. 9].
Kim (US-20250006817-A1) discloses varying inner spacer widths [Fig. 6A].
Conclusion
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/ANDREW CHUNG/
Examiner, Art Unit 2898
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