DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-16, 21-27, 30- is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (U.S. Publication No. 2022/0359427) in view of Wu et al. (U.S. Publication No. 2023/0060716)(“Wu2”).
Regarding claim 15, Wu teaches a method of forming a package structure, the method comprising:
forming an interposer (Fig. 10, interposer 100) including a front side (bottom side in Fig. 10) and a back side opposite the front side (top side in Fig. 10);
attaching a semiconductor die (Fig. 18, die 352) on the front side of the interposer (Fig. 18);
attaching a plurality of substrate portions (Fig. 12, substrate portions 200A and 200B) to the back side of the interposer such that conductive layers of the plurality of substrate portions are electrically coupled to the semiconductor die through the interposer (Fig. 18); and
forming a lower molding layer (Fig. 16, molding layer 224) around side surfaces of each of the plurality of substrate portions on the back side of the interposer (Fig. 16, molding 224 is between and around both substrate portions 200A and 200B).
Wu does not specifically teach forming an upper molding layer around the semiconductor die on the front side of the interposer. However, Wu2 teaches a similar package including forming an upper molding layer (not shown, but see Wu2 paragraph [0084]) around the semiconductor die on the front side of the interposer (Wu2 paragraph [0084]). It would have been obvious to a person of skill in the art at the time of the effective filing date that an encapsulant could have been formed over the die structure because this increases the bonding force and protects the chips from external effects such as moisture.
Regarding claim 16, Wu in view of Wu2 teaches the method of claim 15, wherein the forming of the interposer comprises:
forming a front-side redistribution layer (RDL) interposer portion (Fig. 4, front side RDL portion 108A) on a first carrier substrate (carrier 102;
forming a molded interposer portion (Fig. 8, molded portion 106E) on the front-side RDL interposer portion (Fig. 8); and
forming a back-side RDL interposer portion (Fig. 8, backside portion 108B) on the molded interposer portion.
Wu does not specifically teach the material of the layer 106E, and therefore does not specifically teach that it is molded. However, Wu2 teaches that a similar layer can be molding compound (Wu2 paragraph [0045]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the unknown dielectric of Wu could have been the known molding compound of Wu2 because it would have been a simple substitution of one material for another with predictable results.
Regarding claim 21, Wu in view of Wu2 teaches a method of making a package structure, comprising:
forming an interposer (Fig. 10, interposer 200);
forming a semiconductor die (Fig. 18, die 352) on the interposer; and
forming a lower molded structure (Fig. 16, lower molded structure 200/224) on the interposer opposite the upper molded structure (Fig. 18), the lower molded structure comprising:
a plurality of substrate portions (substrate portions 200A/200B) electrically coupled to the semiconductor die through the interposer (Fig. 18); and
molding material disposed in gaps between adjacent substrate portions (Fig. 16, molding material 224) such that adjacent substrate portions are separated from one another by the molding material (see Fig. 16).
Wu does not teach forming an upper molded structure. However, Wu2 teaches a similar package including forming an upper molding layer (not shown, but see Wu2 paragraph [0084]) around the semiconductor die on the front side of the interposer (Wu2 paragraph [0084]). It would have been obvious to a person of skill in the art at the time of the effective filing date that an encapsulant could have been formed over the die structure because this increases the bonding force and protects the chips from external effects such as moisture.
Regarding claim 22, Wu in view of Wu2 teaches the method of claim 21, wherein the forming of the interposer comprises:
forming a back-side redistribution layer (RDL) portion (Fig. 10, back side RDL portion 108B);
forming a molded portion (Fig. 8, molded portion 106E) on the back-side RDL portion; and
forming a front-side RDL interposer portion on the molded portion (Fig. 10, front side RDL portion 108A).
Wu does not specifically teach the material of the layer 106E, and therefore does not specifically teach that it is molded. However, Wu2 teaches that a similar layer can be molding compound (Wu2 paragraph [0045]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the unknown dielectric of Wu could have been the known molding compound of Wu2 because it would have been a simple substitution of one material for another with predictable results.
Regarding claim 23, Wu in view of Wu2 teaches the method of claim 22, wherein the forming of the molded portion of the interposer comprises attaching a device (Fig. 8, device 110) to the back-side RDL portion and forming an encapsulating layer (encapsulating layer 106E) around the device.
Wu does not specifically teach that the device 110 is an interconnect device. However, Wu2 teaches that a similar device can be a bridge/interconnect device (Wu2 Fig. 2, interconnect device 120, paragraph [0022]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the device of Wu could have been an interconnect device because this allows for communication between adjacent dies with low resistance and transmission time.
Regarding claim 24, Wu in view of Wu2 teaches the method of claim 23, wherein the forming of the upper molded structure comprises attaching the semiconductor die to the front-side RDL portion and forming an upper encapsulating layer on the front-side RDL portion around the semiconductor die (see Wu2 paragraph [0084]).
Regarding claim 25, Wu in view of Wu2 teaches the method of claim 23, wherein the semiconductor die comprises a plurality of semiconductor dies (see Wu Fig. 18) and the forming of the upper molded structure is performed such that the plurality of semiconductor dies are interconnected by the interconnect device through the front-side RDL portion (see Wu2 Fig. 2).
Regarding claim 26, Wu in view of Wu2 teaches the method of claim 25, wherein the forming of the lower molded structure is performed such that the plurality of substrate portions are separated by a first distance (see Wu Fig. 18), and the forming of the upper molded structure is performed such that the plurality of semiconductor dies are separated by a second distance less than the first distance (see Wu Fig. 18 and 30C).
Regarding claim 27, Wu in view of Wu2 teaches the method of claim 21, wherein the plurality of substrate portions comprises a plurality of organic substrate portions (see Wu paragraph [0047]) and the forming of the lower molded structure comprises forming a lower encapsulating layer around and between the plurality of organic substrate portions (see Wu Fig. 16).
Regarding claim 30, Wu in view of Wu2 teaches the method of claim 29, further comprising:
attaching a connector (Hu Fig. 9B, connector 67, Wu Fig. 18, connector 316) to the lower molded structure adjacent the plurality of components (Hu Fig. 9B), wherein the connector is electrically coupled to the semiconductor die through the interposer (Hu Fig. 9B, Wu Fig. 18).
Claims 17 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Wu2, further in view of Cheng et al. (U.S. Publication No. 2023/0187364).
Regarding claim 17, Wu in view of Wu2 teaches the method of claim 16, further comprising:
bonding a second carrier substrate (Fig. 17, second carrier 302) to the back-side RDL interposer portion (Fig. 17, indirectly bonded through substrate 200) and debonding the first carrier substrate from the front-side RDL interposer portion (Fig. 17), wherein the attaching of the semiconductor die comprises attaching the semiconductor die to the front-side RDL interposer portion (Fig. 18) and the forming of the upper molding layer comprises forming the upper molding layer on the front-side RDL interposer portion (see Wu2 paragraph [0084]).
Wu in view of Wu2 does not specifically teach planarizing an upper surface of the upper molding layer to be substantially coplanar with an upper surface of the semiconductor die. However, Cheng teaches a similar package method in which the molding layer is planarized to be coplanar with the upper surface of the die (see Cheng Fig. 18A-18B). It would have been obvious to a person of skill in the art at the time of the effective filing date that the top of the molding compound could have been planarized because this allows for the top of the chip to be exposed for more effective heat shedding.
Regarding claim 32, Wu in view of Wu2 teaches the method of claim 21, further comprising:
attaching a cooling structure to the upper molded structure.
However, Cheng teaches a similar package in which a heat sink is attached to the top of the upper molded structure (see Cheng paragraph [0087]). It would have been obvious to a person of skill in the art at the time of the effective filing date that a heat sink could have been attached because this allows for more effective head shedding from the package.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Wu2, further in view of Hu (U.S. Publication No. 2017/003943).
Regarding claim 29, Wu in view of Wu2 teaches the method of claim 21, further comprising:
attaching a plurality of components on the lower molded structure, wherein the plurality of components are electrically coupled to the plurality of substrate portions.
However, Hu teaches a similar package in which a chip over interposer over substrate (Fig. 9B, chip 662 over interposer RDL1 over substrate RDL2) has a plurality of components on the lower molded structure (Hu Fig. 9B, components 681/682), wherein the plurality of components are electrically coupled to the plurality of substrate portions (Hu Fig. 9B). It would have been obvious to a person of skill in the art at the time of the effective filing date that components could have been attached to the bottom of the substrate because this allows for increased density of devices in the same package footprint.
Claims 33-34 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Hu.
Regarding claim 33, Wu teaches a method of making a package structure, comprising:
forming an interposer (Fig. 1, interposer 100);
forming an upper molded structure (upper molded structure 350) including a semiconductor die (die 352) on the interposer (Fig. 18);
forming a lower molded structure (lower molded structure 200/224) on the interposer opposite the upper molded structure, the lower molded structure comprising:
a substrate portion (substrate portion 200) embedded in molding material of the lower molded structure (see Fig. 16).
Wu does not teach attaching a plurality of components on the lower molded structure and electrically coupled to the substrate portion. However, Hu teaches a similar package in which a chip over interposer over substrate (Fig. 9B, chip 662 over interposer RDL1 over substrate RDL2) has a plurality of components on the lower molded structure (Hu Fig. 9B, components 681/682), wherein the plurality of components are electrically coupled to the plurality of substrate portions (Hu Fig. 9B). It would have been obvious to a person of skill in the art at the time of the effective filing date that components could have been attached to the bottom of the substrate because this allows for increased density of devices in the same package footprint.
Regarding claim 34, Wu in view of Hu teaches the method of claim 33, further comprising:
attaching a connector (Hu Fig. 9B, connector 67, Wu Fig. 18, connector 316) to the lower molded structure adjacent the plurality of components (Hu Fig. 9B), wherein the connector is electrically coupled to the semiconductor die through the interposer (Hu Fig. 9B, Wu Fig. 18).
Response to Arguments
Applicant's arguments filed 5/18/2026 have been fully considered but they are not persuasive. Applicant primarily argues that Wu fails to teach the substrate portions being surrounded by the molding material. Examiner disagrees. Wu Fig. 16 clearly shows that molding material 224 is formed completely surrounding the side surfaces of all substrate portions, including between substrate portions 200A and 200B. See Fig. 13-14 which show the substrate portions prior to molding process, where the is a gap between and around the substrate portions, which has been replaced by the molding material 224 in Fig. 16.
Allowable Subject Matter
Claims 18-19, 28, 31 and 35 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 18-19, the prior art, alone or in combination, fails to teach or suggest bonding a third carrier substrate to the upper molding layer and debonding the second carrier substrate from the back-side RDL interposer portion.
Regarding claim 28, the prior art, alone or in combination, fails to teach or suggest wherein the lower molded structure further comprises a dummy unit and the forming of the lower molded structure further comprises forming the lower encapsulating layer between the plurality of organic substrate portions and the dummy unit.
Regarding claims 31 and 35, the prior art, alone or in combination, fails to teach or suggest forming an underlayer molding material on the lower molded structure, wherein the plurality of components and the connector are located in the underlayer molding material.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Evan G Clinton whose telephone number is (571)270-0525. The examiner can normally be reached Monday-Friday at 8:30am to 5:30pm.
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/EVAN G CLINTON/ Primary Examiner, Art Unit 2899
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