DETAILED ACTION
This application, 18/345001, attorney docket GF2023004-US-NP, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Global Foundries U.S. Inc. and has an effective filing date of 6/30/2023 based on the application date. Applicant's election without traverse of Group I, claims 1-14 in the reply filed on 11/24/2025 is acknowledged. Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7-9, 11 and 12 are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Chuang et al. (U.S. 8558278).
As for claim 1,Chuang teaches in figure 8f a structure, comprising:
a substrate (2),a first transistor (NMOS, right side) on the substrate and a second transistor (PMOS, left side) on the substrate,
the second transistor spaced apart from the first transistor by an isolation region (10);
at least one dielectric liner (14) over the first transistor and the second transistor (16);
an opening (over10) through the at least one dielectric liner over at least the isolation region;
and a dielectric layer (ILD) in at least a portion of the opening.
As for claim 2,
Chuang teaches the structure of claim 1, and teaches that the at least one dielectric liner includes at least one stress-inducing liner (both are stress liners [co5 ln40; co8 ln34]).
As for claim 3. The structure of claim 2, and teaches that the at least one stress-inducing liner includes a first stress-inducing liner over the first transistor and a second stress-inducing liner over the second transistor ([co5 ln40; co8 ln34]).
As for claim 4,
Chuang teaches the structure of claim 3, and teaches that the first transistor is an n-type transistor and the first stress-inducing liner induces a tensile stress, and the second transistor is a p-type transistor and the second stress-inducing liner induces a compressive stress [co5 ln40; co8 ln34]).
As for claim 5,
Chuang teaches the structure of claim 2, and teaches that the opening in the at least one stress-inducing liner is over at least a first portion of the first transistor and over at least a second portion of the second transistor (the opening extends over the s/d on both transistors).
As for claim 7,
Chuang teaches the structure of claim 5,
and teaches that a first end of the at least one stress-inducing liner is over the at least the first portion of the first transistor and a second end of the at least one stress-inducing liner is over the at least the second portion of the second transistor, and the first end and the second end are spaced apart over the isolation region. (shown in figure 8f )
As for claim 8,
Chuang teaches the structure of claim 1, and teaches that the isolation region includes a region of the substrate. (Isolation 10 is an STI, shown in the substrate).
As for claim 9,
Chuang teaches the structure of claim 1, and teaches that the isolation region includes a trench isolation in the substrate. (Isolation 10 is an STI, shown in the substrate)
As for claim 11,
Chuang teaches in figure 8F,structure, comprising:
a substrate (2);
a n-type transistor on the substrate ; (NMOS, right side) ;
a p-type transistor on the substrate (PMOS, left side),
the p-type transistor spaced apart from the n-type transistor by an isolation region (10);
a tensile stress-inducing liner (16) over the n-type transistor;
a compressive stress-inducing liner over the p-type transistor (14 [co5 ln40; co8 ln34]));
an opening (over10) through the tensile stress-inducing liner and the compressive stress-inducing liner, the opening over at least a first portion of the n-type transistor and over at least a second portion of the p-type transistor (shown over the s/d of both devices);
and a dielectric layer (ILD) in at least a portion of the opening.
As for claim 12.
Chuang teaches the structure of claim 11, and teaches that a first end of the tensile stress-inducing liner is over the at least the first portion of the n-type transistor and a second end of the compressive stress-inducing liner is over the at least the second portion of the p-type transistor, and the first end and the second end are spaced apart over the isolation region (shown in figure 8f).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 14 rejected under 35 U.S.C. 103 as being unpatentable over Chuang in view of Noble (U.S. 6229342).
As for claim 6,
Chuang teaches the structure of claim 2, but does not teach
a third transistor on the substrate and a fourth transistor on the substrate, the third transistor spaced apart from the fourth transistor by another isolation region, and wherein the at least one stress-inducing liner is over the third transistor, the fourth transistor and the another isolation region between the third and fourth transistors, and wherein the first and second transistors have a higher threshold voltage than the third and fourth transistors.
However, additional sets of transistors with the associated isolation and stress control is a duplication of parts. It has been held that mere duplication or arrangement of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bermis Co., 193 USPQ8. In re Harza establishes "a mere duplication of parts has no patentable significance unless a new and unexpected result is produced." 274 F.2d 669, 124 USPQ 378 (CCPA 1960); See, MPEP 2144.04 (VI)(C).Here, the applicant has not disclosed any unexpected results, and the additional devices merely expand the capacity of the device. Therefore, it would have been obvious to one skilled in the art at the invention was made to add the additional subregions.
Chuang does not make obvious using different threshold voltages for different transistors.
However, Noble teaches a third and fourth NMOS/PMOS transistors with different threshold voltages (Noble, claims 17 and 19).
It would have been obvious to one skilled in the art at the effective filing date of this application to design a CMOS circuit with different threshold voltages to allow for high and low voltage control in the same device. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 14,
Chuang teaches the structure of claim 11,
but does not teach: another n-type transistor on the substrate and another p-type transistor on the substrate, the another n-type transistor spaced apart from the another p-type transistor by another isolation region, and wherein the tensile stress-inducing liner is over the another n-type transistor, and the compressive stress-inducing liner is the another p-type transistor and the another isolation region, and wherein the n-type and p-type transistors have a higher threshold voltage than the another n-type and p-type transistors.
However, additional sets of transistors with the associated isolation and stress control is a duplication of parts. It has been held that mere duplication or arrangement of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bermis Co., 193 USPQ8. In re Harza establishes "a mere duplication of parts has no patentable significance unless a new and unexpected result is produced." 274 F.2d 669, 124 USPQ 378 (CCPA 1960); See, MPEP 2144.04 (VI)(C).Here, the applicant has not disclosed any unexpected results, and the additional devices merely expand the capacity of the device. Therefore, it would have been obvious to one skilled in the art at the invention was made to add the additional subregions.
Chuang does not make obvious using different threshold voltages for different devices.
However, Noble teaches a third and fourth NMOS/PMOS transistors with different threshold voltages (Noble, claims 17 and 19).
It would have been obvious to one skilled in the art at the effective filing date of this application to design a CMOS circuit with different threshold voltages to allow for high and low voltage control in the same device. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claims 10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang in view of Mouli (U.S. 2004/0038488).
As for claim 10,
Chuang teaches the structure of claim 1,But does not teach deuterium in an interface of a gate conductor of a gate and a gate dielectric layer in the first transistor and the second transistor.
However, Mouli teaches deuterium in the gate insulator (Mouli [0050]).
It would have been obvious to one skilled in the art at the effective filing date of this application add deuterium to the gate insulator to electrically stress the CMOS device. (Mouli [0050]) One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 13,
Chuang teaches the structure of claim 11, but does not teach deuterium in an interface of a gate conductor of a gate and a gate dielectric layer in the n-type transistor and the p-type transistor.
However, Mouli teaches deuterium in the gate insulator (Mouli [0050]).
It would have been obvious to one skilled in the art at the effective filing date of this application add deuterium to the gate insulator to electrically stress the CMOS device. (Mouli [0050]) One skilled in the art would have combined these elements with a reasonable expectation of success.
Conclusion
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/JOHN A BODNAR/Primary Examiner, Art Unit 2893