DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I, claims 1-14 and 21-26, in the reply filed on 1 December 2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i).
Information Disclosure Statement
This office acknowledges receipt of the following items from the applicant: Information Disclosure Statement (IDS) filed on 15 April 2025. The references cited on the PTOL 1449 form have been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 8, 21, 24 and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Or-Bach et al. (U.S. Patent Application Publication 2013/0122672).
Referring to Claim 8, Or-Bach teaches in Fig. 52A-52D (par. 5 and 337-344) teaches a device (see Fig. 52D) comprising: a first source/drain region (5228) in a first transistor layer (pull-up pMOS; 5216); a first conductive line (wiring) in a dielectric layer (ILD) over the first source/drain region (5228); a second source/drain region (5230) over the first conductive line (wiring), the second source/drain region (5230) being disposed in a second transistor layer (nMOS pass transistors; 5204); a first source/drain contact (middle portion of 5210) extending through the first source/drain region (5228) and touching the first conductive line (wiring); and a second source/drain contact (upper portion of 5210) extending through the second source/drain region (5230) and touching the first conductive line (wiring), wherein the first source/drain region (5228) is electrically connected to the second source/drain region (5230) by the first source/drain contact (middle portion of 5210), the second source/drain contact (5210), and the first conductive line (wiring). See annotated Fig. 52D below showing the examiner’s interpretation of the claim elements for claim 8.
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Interpretation of Fig. 52D for claim 8
Referring to Claim 21, Or-Bach teaches in Fig. 52A-52D (par. 5 and 337-344), a device comprising: a first gate electrode (shown but not labeled) disposed in a first transistor layer (pull-down nMOS; 5202); a second gate electrode (5218) disposed in a second transistor layer (pull-up pMOS; 5216), wherein the first transistor layer (5202) and the second transistor layer (5202) are vertically stacked; an interconnect structure between the first transistor layer (5202) and the second transistor layer (5216), the interconnect structure comprising a first conductive line (wiring); a first gate contact (shown but not labeled) electrically connected to the first gate electrode (shown but not labeled); and a second gate contact (5220) electrically connected to the second gate electrode (5218), wherein the first conductive line (wiring) extends from a surface (top) of the first gate contact (shown but not labeled) to a surface (bottom) of the second gate contact (5220). See annotated figures of Fig. 52C and 52D below showing the examiner’s interpretation of the claim elements for claim 21 and dependent claims thereof.
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Interpretation of Fig. 52C for claims 21, 24 and 26
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Interpretation of Fig. 52D for claims 21, 24 and 26
Referring to Claim 24, Or-Bach further teaches a first source/drain region (5226) in the first transistor layer (pull-down nMOS; 5202); a second source/drain region (5228) in the second transistor layer (pull-up pMOS; 5216); a first source/drain contact (lower portion of 5210) electrically connected to the first source/drain region (5226); and a second source/drain contact (middle portion of 5210) electrically connected to the second source/drain region (5228), wherein a second conductive line (wiring; par. 342) in the interconnect structure electrically connects the first source/drain contact (lower portion of 5210) to the second source/drain contact (middle portion of 5210).
Referring to Claim 26, Or-Bach further teaches wherein the first conductive line (wiring) and the second conductive line (wiring) are disposed in a same dielectric layer (ILD) of the interconnect structure (between the pull-down nMOS 5202 and pull-up pMOS 5216 transistor layers).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (U.S. Patent Application Publication 2013/0122672).
Referring to Claim 9, Or-Bach teaches the limitations of claim 8, but does not explicitly state wherein the first source/drain contact and the second source/drain contact each comprises tungsten (W), cobalt (Co), or ruthenium (Ru). However, Or-Bach teaches the known use of tungsten (W) material for the electrical connections between multiple device layers (par. 304, 305, 336, 404 and 430). Therefore, it would have been obvious to one having ordinary skill in the art before the invention was effectively filed to utilize the well-known tungsten material as taught for the source/drain contacts based on it’s known suitability in the art for providing electrical connections between transistor layers due to its ability to withstand high temperature processing for wiring (par. 336, last two sentences; par. 430). It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Allowable Subject Matter
Claims 1-7 are allowable.
Claims 10-14, 22, 23 and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 1, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the device comprising: the first gate contact extending along a sidewall of the first gate electrode from a top surface of the first gate electrode to the first conductive line; and wherein the first gate electrode is electrically connected to the second gate electrode by the first gate contact, the second gate contact, and the first conductive line in combination with all of the limitations of claim 1. Claims 2-7 include the limitations of claim 1.
Regarding Claim 10, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the device further comprising: a third source/drain contact electrically connected to the first source/drain region, wherein the first source/drain contact extends through the third source/drain contact; and a fourth source/drain contact electrically connected to the second source/drain region, wherein the second source/drain contact extends through the fourth source/drain contact in combination with all of the limitations of claims 8 and 10. Claim 11 includes the limitations of claim 10.
Regarding Claim 12, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the device further comprising: a first silicide region on a sidewall of the first source/drain contact and a sidewall of the first source/drain region; and a second silicide region on a sidewall of the second source/drain contact and a sidewall of the second source/drain region in combination with all of the limitations of claims 8 and 12.
Regarding Claim 13, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the device further comprising: a first gate contact extending through the first gate electrode to the second conductive line; wherein the first gate electrode is electrically connected to the second gate electrode by the first gate contact, the second gate contact, and the second conductive line in combination with all of the limitations of claims 8 and 13.
Regarding Claim 14, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the device of claim 8 further comprising: a gate contact extending through the first gate electrode, the dielectric layer, and the second gate electrode, wherein the first gate electrode is electrically connected to the second gate electrode by the gate contact in combination with all of the limitations of claims 8 and 14.
Regarding Claim 22, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the device, wherein the first gate contact extends through the first gate electrode in combination with all of the limitations of claims 21 and 22. Claim 23 includes the limitations of claim 22.
Regarding Claim 25, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the device further comprising wherein the first source/drain contact extends through the first source/drain region in combination with all of the limitations of Claim 21, 24 and 25.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896